Agilent 5991-4082EN Mechanism of Jitter Amplification in Clock Channels [24] free download

File name 5991-4082EN Mechanism of Jitter Amplification in Clock Channels [24].pdf

DesignCon 2014 Mechanism of Jitter Amplification in Clock Channels Fangyi Rao, Agilent Technologies, Inc. [email protected] 408-553-4373 Sammy Hindi, Juniper Networks [email protected] 408-936-1280 Abstract Jitter amplification in clock channels is analyzed analytically in terms of signal transfer function or channel S-parameters. The periodicity of the clock pattern eliminates the inter-symbol-interference jitter so jitter at the channel output is entirely induced by input jitter. A phase modulation (PM) approach is employed to derive the jitter transfer function and amplification factors for sinusoidal jitter (SJ), duty-cycle-distortion (DCD) and random jitter (RJ). Results demonstrate that jitter amplification is the consequence of smaller attenuation at the jitter lower sideband (LSB) than at the fundamental, which is at a higher frequency than the LSB. Scaling equations of DCD and RJ amplifications with channel loss is obtained by employing an exponential loss model. It is shown that jitter is amplified by lossy channels at any frequency below Nyquist and the effect grows exponentially with jitter frequency and data rate. Amplification factors of SJ, DCD and RJ are also derived within the square wave representation of clock signals, and the results are shown to recover those using the PM approach when high order harmonics are neglected. The theory is verified by simulations. Author(s) Biography Fangyi Rao is a master engineer at Agilent Technologies. He received his Ph.D. degree in theoretical physics from Northwestern University. He joined Agilent EEsof in 2006 and works on Analog/RF and SI simulation technologies in ADS and RFDE. From 2003 to 2006 he was with Cadence Design Systems, where he developed the company's Harmonic Balance technology and perturbation analysis of nonlinear circuits. Prior to 2003 he worked in the areas of EM simulation, nonlinear device modeling, and medical imaging. Sammy Hindi is a senior electrical engineer at Juniper Networks. Prior to Juniper he was a technical leader at Cisco System for more than 11 years and a principal engineer at Rambus Inc. for six years. Prior to Rambus he was a design engineer at different firms including Tandem Computer and Philips. He received his BS degree in Electrical Engineering from University of Baghdad. 1. Introduction High speed interconnect performance is increasingly influenced by jitter as data rate advances. The amount of jitter is modulated by channel dispersion as signals propagate in the system. It is observed in both measurements and simulations that jitter can be amplified by a lossy channel even when the channel is linear, passive and noiseless [1]- [5]. The effect happens to different jitter types including sinusoidal jitter (SJ), duty-cycle- distortion (DCD) and random jitter (RJ). In particular, DCD and RJ amplifications in clock signals are found to scale uniquely with channel loss [2], indicating that loss is responsible for the effect. The mec