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File name: | 5991-2056EN W1717 SystemVue Hardware Design Kit - Data Sheet c20141023 [9].pdf [preview 5991-2056EN W1717 SystemVue Hardware Design Kit - Data Sheet c20141023 [9]] |
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Model: | 5991-2056EN W1717 SystemVue Hardware Design Kit - Data Sheet c20141023 [9] 🔎 |
Original: | 5991-2056EN W1717 SystemVue Hardware Design Kit - Data Sheet c20141023 [9] 🔎 |
Descr: | Agilent 5991-2056EN W1717 SystemVue Hardware Design Kit - Data Sheet c20141023 [9].pdf |
Group: | Electronics > Other |
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File name 5991-2056EN W1717 SystemVue Hardware Design Kit - Data Sheet c20141023 [9].pdf Keysight Technologies W1717 SystemVue Hardware Design Kit Data Sheet From Algorithm to Implementation of Digital Signal Processing Systems Overview The W1717 SystemVue Hardware Design Kit (HDK) is a hardware design flow personality that adds onto the core W1461 SystemVue core environment to accelerate the design and verification of digital signal processing (DSP) algorithms in communications and aerospace defense systems. It allows system architects and algorithm developers to create baseband models quickly and validate their performance at the system-level against RF models, test equipment, Standards references, and other signals and conditions. The W1717 HDK enables a model-based design approach to FPGA rapid prototyping and integrates easily into mainstream design and verification flows. It includes a synthesizable fixed-point model library, and offers a rich set of example designs, ranging from basic filters to realistic communications physical layer design. 03 Keysight W1717 SystemVue Hardware Design Kit Data Sheet Key Features Design and Verification Productivity System-level modelers and verification engineers can take advantage of SystemVue's comprehensive integration into hardware design and verification flows. A fixed-point simulation library predicts hardware-like effects without committing to a targeted implementation, and generates synthesizable, hierarchical, RTL-level Verilog and VHDL that is bit-true and cycle accurate. This provides a path to implementation and creates a verification wrapper for poly- morphic model-based design flows moving from algorithm to fixed point to RTL and to instantiated hardware. The ability to co-simulate with external hardware description language (HDL) simulators or real hardware is included free with the SystemVue core environment. Figure 2. The HDK provides the fastest hardware design flow, enabling high performance and high productivity 04 Keysight W1717 SystemVue Hardware Design Kit Data Sheet Fixed Point Design Mapping signal-processing algorithms to dedicated hardware with The fixed-to-float and float-to-fixed conversion parts provide fixed-point arithmetic is often an integral part of the algorithm a means of interfacing fixed-point components with other design and analysis flow. Hardware Design Parts, available in the SystemVue blocks. Hardware Design Parts can also be configured HDK, can be used to build, simulate and analyze fixed-point sys- to automatically collect information on dynamic range, overflows tems. A library of over 45 functions, from low-level logic elements and underflows. The parts can be shown in the Fixed-Point to more advanced signal-processing parts such as filters and fast Analysis Table to help eng |
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