Agilent 5990-9111EN Simulating High-Speed Serial Channels with IBIS-AMI Models c20140829 [19] free download

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Keysight Technologies Simulating High-Speed Serial Channels with IBIS-AMI Models Bob Sullivan, Michael Rose, Jason Boh Application Note Introduction The Input/Output Buffer Information Specification (IBIS) has been an essential component of the electrical simulation toolbox for nearly two decades. Many design engineers are familiar with the application of IBIS models and for the most part, the models have provided an accurate, easy-to-use alternative to SPICE-based transistor models. In fact, most IBIS models are simple behavioral translations of a vendor's SPICE buffer model. However, as serial interface bit rates increase, critical limitations with IBIS models have become more acute. With the current (version 5.0) of the IBIS specification, an important algorithmic modeling component has been added to the conventional behavioral analog IBIS model. Several earlier efforts were made to add a mixed-signal model capability with limited success. IBIS-Algorithmic Modeling Interface (AMI) represents an important milestone in the IBIS mixed-signal evolution. This paper reviews some of the benefits and limitations of using IBIS models and introduces the new AMI extensions to the latest IBIS version 5.0 specification. Additionally, it illustrates how to perform several simulations of a typical backplane system using the Advanced Design System 2011 (ADS2011) toolset. IBIS Historical Perspective The first version of IBIS was released in 1993 through the IBIS Open Forum. There are many reasons for the popularity of IBIS models; namely, that they are widely available, standardized (ANSI/EIA-656 and GEIA-STD-0001), and the specification is controlled by an open forum with a membership of top tier EDA and silicon vendors and equipment manufacturers. Since IBIS models are behavioral, simula- tion times are usually very fast and do not suffer from convergence issues. Unlike un-encrypted SPICE transistor-level circuit models, IBIS models do not expose the intellectual property (IP) of the silicon vendor or foundry. In addition, transistor- level models are generally encrypted for a single specific EDA tool. In contrast, IBIS models are portable allowing them to run on any EDA tool that supports the standard. IC vendors are not burdened with generating and supporting one model for each EDA tool. And, integration support