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File name CXA1992AR.pdf

CXA1992AR RF Signal Processing Servo Amplifier Description The CXA1992AR is a bipolar IC developed for CD player RF signal processing and servo control. Features · Automatic focus bias adjustment circuit · Automatic tracking balance and gain adjustment circuits · RF level control circuit · Interruption countermeasure circuit · Sled overrun prevention circuit · Anti-shock circuit · Defect detection and prevention circuits · RF 1-V amplifier, RF amplifier · APC circuit · Focus and tracking error amplifier · Focus, tracking and sled servo control circuits · Focus OK circuit · Mirror detection circuit · Single power supply and dual power supplies Applications CD players Structure Bipolar silicon monolithic IC 52 pin LQFP (Plastic) Absolute Maximum Ratings (Ta = 25°C) 12 V · Supply voltage VCC · Operating temperature Topr ­20 to +75 °C · Storage temperature Tstg ­65 to +150 °C · Allowable power dissipation PD 600 mW Recommended Operating Conditions Operating supply voltage VCC ­ VEE 3.0 to 5.5 V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. ­1­ E96X16-PS CXA1992AR Block Diagram RF_M RFTC RF_O RF_I CC1 PD2 39 38 37 VEE 36 35 34 33 32 31 30 29 28 CC2 PD1 LD CB 27 PD2 IV AMP PD1 IV AMP RF SUMMING AMP FE_BIAS 40 VCC APC IIL VCC TTL FOK PD CP 26 SENS2 F 41 F IV AMP VEE LASER POWER CONTROL 25 SENS1 E 42 E IV AMP VCC FE AMP VCC 24 C. OUT VEE DFCT IFB2 IFB3 IFB1 IFB4 IFB5 EI 43 BAL1 BAL2 BAL3 BAL4 IFB6 23 VEE LEVEL S XRST VEE VEE TOG1 TOG2 TOG3 TOG4 VEE 44 TGFL VEE FO. BIAS WINDOW COMP. VCC TEO 45 TRK. GAIN WINDOW COMP. 22 DATA MIRR IIL TTL FOK TTL IIL 21 XLT LDON TGFL LPCL TEI 47 ATSC 48 ATSC WINDOW COMP. TZC COMP. TZC 49 DFCT TM1 TDFCT 50 TG1 VCC TRACKING PHASE COMPENSATION FOH FOL TGH TGL BALH BALL ATSC TZC FZC LPC IIL DATA REGISTER INPUT SHIFT REGISTER ADDRESS DECODER SENS SELECTOR OUTPUT DECODER VCC CC1 LPFI 46 MIRR DFCT1 E-F BALANCE WINDOW COMP. 20 CLK 19 LOCK 18 VCC DFCTO IFB1-6 BAL1-4 TOG1-4 FS1-4 TG1-2 TM1-7 PS1-4 ISET 17 ISET VCC TM4 VCC 16 TM6 SL_O VC 51 VCC VCC VEE FZC 52 FOCUS PHASE COMPENSATION FS1 TM3 VEE FS2 DFCT FZC COMP. FS4 Charge up TG2 TM5 VEE TM2 TM7 15 SL_M 14 SL_P FSET VEE 1 FEO 2 FEI 3 FDFCT 4 FGD 5 FLB 6 FE_O 7 FE_M 8 SRCH 9 TGU 10 TG2 11 FSET 12 TA_M 13 TA_O ­2­ CXA1992AR Pin Description Pin No. Symbol I/O Equivalent circuit Description 10µ 25p 147 1 174k 300µ 10µ 1 FEO O Focus error amplifier output. Connected internally to the window comparator input for bias adjustment. 2 FEI I 2 147 100k 147 Focus error input. 3 FDFCT I 3 3µ Capacitor connection pin for defect time constant. 4 FGD