IBM SY31-0458-3 Section 03 Main Storage Processor free download

File name SY31-0458-3_Section_03_Main_Storage_Processor.pdf

Contents MAIN STORAGE PROCESSOR 3-1 Command Instructions 3-46 DATA FLOW AND CLOCK 3-2 Jump on Condition (JC) 3-46 Data Flow 3-2 Load Program Mode Register (LPMR) 3-47 Parity Checking and Generation 3-2 Supervisor Call (SVC) 3-48 Clock 3-4 FUNCTIONAL UNITS 3-50 OPERATIONS . 3-6 Main Storage 3-51 Instruction and Execution Cycles 3-6 Main Storage Address Register 3-51 Sequential Instruction Execution 3-6 Operation Register . 3-51 I/O Data Movement . 3-6 Q-Backup Register 3-51 I nstruction Formats 3-6 Q-Register 3-51 Instruction Fetch Operation 3-8 X-Registers. 3-51 Addressing 3-10 V-Register 3-51 Direct Addressing . 3-10 Arithmetic and Logic Unit. 3-51 Indexing 3-10 Arithmetic and Logic Unit Parity Predict 3-51 Address Translation 3-10 Incrementer or Decrementer 3-51 INSTRUCTION EXECUTION 3-12 Decimal Correct . 3-52 Arithmetic Instructions 3-13 Local Storage Register 3-52 Zero and Add Zoned (ZAZ) . 3-13 Program Status Register 3-53 Add Zoned Decimal (AZ) . 3-15 Status Byte Registers 3-54 Subtract Zoned Decimal (SZ) 3-16 Status Byte 0 (Sense Only) 3-54 Recomplement Cycle 3-18 Status Byte 1 (Load Only) 3-54 Add Logical Characters (ALC) . 3-21 Status Byte 2 . 3-54 Subtract Logical Characters (SLC) 3-22 Status Byte 3 . 3-54 Add to Register (A) 3-24 Backup Mode Register . 3-54 Data Control Instructions 3-26 Configuration Control Register 3-54 Move Hexadecimal Character (MVX) . 3-26 Address Compare Register 3-54 Move Characters (MVC) 3-28 Address Translation 3-55 Edit (ED) . 3-30 Address Translation Registers 3-55 Insert and Test Characters (lTC) 3-32 Program Mode Register 3-55 Move Logical Immediate (MV!) 3-34 Control Mode Register. 3-55 Set Bits On Masked (SBN) 3-35 ERROR CONDITIONS 3-56 Set Bits Of