Philips 74HC574 free download

File name 74HC_HCT574_CNV_2.pdf

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: · The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT574 Octal D-type flip-flop; positive edge-trigger; 3-state Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state FEATURES · 3-state non-inverting outputs for bus oriented applications · 8-bit positive edge-triggered register · Common 3-state output enable input · Independent register and 3-state buffer operation · Output capability: bus driver · ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT574 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT574 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and non-inverting 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. 74HC/HCT574 The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The "574" is functionally identical to the "564", but has non-inverting outputs. The "574" is functionally identical to the "374", but has a different pinning. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD Ч VCC2 Ч fi + (CL Ч VCC2 Ч fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL Ч VCC2 Ч fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay CP to Qn maximum clock frequency input capacitance power dissipation capacitance per flip-flop notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 14 123 3.5 22 HCT 15 76 3.5 25 ns MHz pF pF UNIT December 1990 2 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state PIN DESCRIPTION PIN NO. 1 2, 3, 4, 5, 6, 7, 8, 9 10 11 19, 18, 17, 16, 15, 14, 13, 12 20 SYMBOL OE D0 to D7 GND CP Q0 to Q7 VCC NAME AND FUNCTION 74HC/HCT574 3-state output enable input (active LOW) data inputs ground (0 V) clock input (LOW-to-HIGH, edge-triggered) 3-state flip-flop outputs positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990