Fairchild CD4081BC/MC14081BCP free download

File name CD4081BC.pdf

CD4071BC · CD4081BC Quad 2-Input OR Buffered B Series Gate · Quad 2-Input AND Buffered B Series Gate October 1987 Revised January 1999 CD4071BC · CD4081BC Quad 2-Input OR Buffered B Series Gate · Quad 2-Input AND Buffered B Series Gate General Description The CD4071BC and CD4081BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outputs which improve transfer characteristics by providing very high gain. All inputs protected against static discharge with diodes to VDD and VSS. Features s Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS s 5V­10V­15V parametric ratings s Symmetrical output characteristics s Maximum input leakage 1 µA at 15V over full temperature range Ordering Code: Order Number CD4071BCM CD4071BCN CD4081BCM CD4081BCN Package Number M14A N14A M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices are also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagrams Pin Assignments for DIP and SOIC CD4071B CD4081B Top View Top View © 1999 Fairchild Semiconductor Corporation DS005977.prf www.fairchildsemi.com CD4071BC · CD4081BC Schematic Diagrams CD4071B 1 /4 of device shown J=A+B Logical "1" = HIGH Logical "0" = LOW *All inputs protected by standard CMOS protection circuit. CD4081B 1/ 4 of device shown J=A·B Logical "1" = HIGH Logical "0" = LOW All inputs protected by standard CMOS protection circuit. www.fairchildsemi.com 2 CD4071BC · CD4081BC Absolute Maximum Ratings(Note 1) (Note 2) Voltage at Any Pin Power Dissipation (PD) Dual-In-Line Small Outline VDD Range Storage Temperature (TS) Lead Temperature (TL) (Soldering, 10 seconds) 260°C (Note 2) 700 mW 500 mW -0.5 VDC to +18 VDC -65°C to +150°C -0.5V to VDD +0.5V Recommended Operating Conditions Operating Range (VDD ) Operating Temperature Range (TA) CD4071BC, CD4081BC -40°C to +85°C Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation. Note 2: All voltages measured with respect to VSS unless otherwise specified. 3 VDC to 15 VDC DC Electrical Characteristics CD4071BC/CD4081BC Symbol IDD Parameter Quiescent Device Current VOL LOW Level Output Voltage VOH HIGH Level Output Voltage VIL LOW Level Input Voltage VIH HIGH Level Input