InterM System2120 & 2240 free download

File name InterM-System2120_2240 poweramp.pdf

SERVICE MANUAL M U LT I P. A C O M B I N AT I O N AMPLIFIER SYSTEM-2120/2240 www.inter-m.com MADE IN KOREA NO: 9007919920 ELECTRICAL ADJUSTMENT PROCEDURE 1. IDLE CURRENT POINT ADJUSTMENT SVR701 TEST POINT AMP IDLE CURRENT LEVEL R773 4mV 2. DECK SPEED ADJUSTMENT CONDITION (USE MCC-112 TEST TAPE) POINT ADJUSTMENT SVR301 TEST POINT DECK SPEED OUTPUT LEVEL 30000±50Hz CONTENTS Electrical Adjustment Procedure Micom Data (CD) Micom Data (TUNER) Micom Data (DECK) Specifications Electrical Parts List Top and Bottom View of P.C. Board Wiring Diagram Block Diagram Schematic Diagram Schematic Diagram Exploded View of Cabinet & Chassis / Mechanical Parts List Ass'y Drawing 1 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 13, 14, 15, 16 17, 18, 19, 20 21, 22 23, 24, 25, 26, 27, 28, 29 30, 31, 32, 33, 34, 35, 36 37 38 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52 53, 54 55, 56 1 MICOM DATA (CD) KA9258D 4-Channel Motor Driver 28-SSOPH-375 PIN DEFINITIONS Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name DO1.1 DO1.2 DI1.1 DI1.2 REG REO MUTE GND1 DI2.1 DI2.2 DO2.1 DO2.2 GND2 OPOUT OPIN(­) OPIN(+) DO3.1 DO3.2 DI3.1 DI3.2 VCC1 VCC2 VREF DI4.1 DI4.2 DO4.1 DO4.2 GND3 I/O O O I I ­ O I ­ I I O O ­ O I I O O I I ­ ­ I I I O O ­ Pin Function Description Diver output Diver output Diver input Diver input Regulator Regulator output Mute Ground 1 Diver input Diver input Diver output Diver output Ground 2 Op-amp output Op-amp input (­) Op-amp input (+) Diver output Diver output Diver input Diver input Supply voltage Supply voltage 2.5V bias voltage Diver input Diver input Diver output Diver output Ground 3 PIN ASSIGNMENTS 2 3 KA3082 Bi-Directional DC Motor Driver 10-SIP INTERNAL BLOCK DIAGRAM PIN ASSIGNMENTS PIN DEFINITIONS Pin Number 1 2 3 4 5 6 7 8 9 10 Pin Name GND VO1 VZ1 VCTL VIN1 VIN2 SVCC PVCC CZ2 VOZ I/O ­ O ­ I I I ­ ­ ­ O Pin Function Description Ground Output 1 Phase compensation Motor speed control Input 1 Input 2 Supply voltage (Signal) Supply voltage (Power) Phase compensation Output 2 4 5 CXD2589Q CD Digital Signal Processor 80 pin QFP (Plastic) PIN CONFIGURATIONS BLOCK DIAGRAM 6 7 PIN DEFINITIONS Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Symbol VSS LMUT RMUT SQCK SQSO SENS DATA XLAT CLOC SEIN CNIN DATO XLTO CLKO SPOA SPOB XLON FOK VDD VSS MDP PWMI TEST TES1 VPCO VCKI V16M VCTL PCO FILO FILI AVSS CLTV AVDD RF BIAS ASYI ASYO LRCK LRCKI PCMD PCMDI BCK BCKI VSS I/O ­ O O I O O I I I I I O O O I I O I ­ 1,0 1,0 1,0 1,0 Description GND Left-channel zero detection flag Right-channel zero detectio flag SQSO readout clock input Sub Q 80-bit serial output SENS output to CPU Serial data input from CPU Latch input from CPU. Serial data is latched at the falling edge Serial data transfer clock input from CPU SENS input from SSP Track jump count signal input Serial data output to SSP Serial data latch output to SSP