File information: | |
File name: | Vestel DVD 2200.zip [preview Vestel DVD 2200] |
Size: | 1298 kB |
Extension: | |
Mfg: | Vestel |
Model: | Vestel DVD 2200 🔎 |
Original: | |
Descr: | Vestel DVD 2200 scheme |
Group: | Electronics > Consumer electronics > DVD |
Uploaded: | 14-07-2004 |
User: | voivoda |
Multipart: | No multipart |
Information about the files in archive: | ||
Decompress result: | OK | |
Extracted files: | 1 | |
File name Vestel DVD 2200.pdf Production - STi5508/80 DECMEM MA[0..13] MD[0..15] SMICLK #SMICS0 #SMIRAS #SMICAS #SMIWE SMIDQML SMIDQMU 05-DECMEM FRONT PANEL FPCLK FPDATA FPSTB FPIR SCL SDA 14-FRONT PANEL AUDIO OUT #BPRESET SPDIF_OUT DAC_PCMCLK DAC_SCLK DAC_LRCLK DAC_DATA0 DAC_DATA1 DAC_DATA2 DAC_DATA SCL SDA BPPIO0 BPPIO1 BPPIO2 BPPIO3 11-AUDIO OUT VIDEO OUT RED GREEN BLUE STANDBY CHROMA LUMA CVBS 12-VIDEO OUT SEEPROM RST SCL SDA POWERON 20-SEEPROM RST EXTPLL #BPRESET ML MD MC PCMCLK PIXCLK AUDCLK 09-EXTPLL PIXCLK AUDCLK 02-5508 I²C Add.: E²PROM RTC/WD NV-MEM TVM502 ML MD MC 22-POWER POWERON BPPIO0 BPPIO1 BPPIO2 BPPIO3 FPCLK FPDATA FPSTB FPIR SMIDQML SMIDQMU DQML DQMH #SMIWE #SDWE #SMIRAS #SMICAS #SDRAS #SDCAS #SMICS0 #SDCS0 SMICLK RAMCLK MD[0..15] MD[0..15] DATA[0..15] DATA[0..15] MA[0..13] ADR[0..20] ADR[0..20] STi5508 MA[0..13] RAMCLK #SDCS0 #SDRAS #SDCAS #SDWE INITIAL RELEASE SYSMEM ADR[0..20] DATA[0..15] DQML DQMH 04-SYSMEM FLASHROM ADR[0..20] DATA[0..15] #CE3 #OE #WE #RESET #CE3 #OE #WE #RESET 03-FLASHROM RS232 RTS CTS TXD RXD RTS CTS TXD RXD 10-RS232 #BPRESET SPDIF_OUT DAC_SCLK DAC_LRCLK DAC_DATA0 DAC_DATA1 DAC_DATA2 DAC_DATA FRONTEND ADR[0..20] DATA[0..15] #FERESET #CE1 R/#W #ATAPI_WR #ATAPI_RD FEINT RED GREEN BLUE CHROMA LUMA CVBS OPEN CLOSE #SENSE #PUSH DATA BCLK FLAG SYNC SCL SDA #FERESET #CE1 R/#W #ATAPI_WR #ATAPI_RD FEINT OPEN CLOSE #SENSE #PUSH DATA BCLK FLAG SYNC SCL SDA 06-FRONTEND POWER 0xA0 0xDE 0xAE 0x30 Production - Overview of Decoder Board MA[0..13] +2V5-PCM VCC3 R1 10K JP1 10K R5 0R0 0R0 R7 RAMCLK #SDCS0 R347 10K ADR1 ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 ADR8 ADR9 ADR10 ADR11 ADR12 ADR13 ADR14 ADR15 ADR16 ADR17 ADR18 ADR19 ADR20 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 +2V5 +2V5-PLL JUMPER3 R2 TP1 VCC3 DATA[0..15] DATA[0..15] MA[0..13] ADR[0..20] ADR[0..20] +2V5-DENC MD[0..15] MD[0..15] POWERON 4 47 81 107 136 159 184 161 162 163 164 165 166 167 168 169 170 173 174 175 176 177 178 179 180 181 182 183 141 142 143 144 145 146 147 148 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 U2 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 0R0 0R0 0R0 0R0 0R0 0R0 95 SMICLKOUT 82 SMICLKIN CE1 CE2 CE3 OE R10 R12 R14 R15 R17 0R0 0R0 0R0 0R0 0R0 74 75 76 77 78 79 80 SMICS0 SMICS1 SMIRAS SMICAS SMIWE SMIDQML SMIDQMU ADR1 ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 ADR8 ADR9 ADR10 ADR11 ADR12 ADR13 ADR14 ADR15 ADR16 ADR17 ADR18 ADR19 ADR20 ADR21 0R0 151 152 153 154 155 156 157 158 #JTAG_RESET U1 1 4 2 TC4S81F R3 NS VDD_PCM 48 VDD_RGB 23 VDD_YCC 30 #SMIRAS #SMICAS #SMIWE SMIDQML SMIDQMU #SMIRAS #SMICAS #SMIWE SMIDQML SMIDQMU R6 R8 R9 R11 R13 SMICLK SMICLK R16 VDD2_5 14 VDD2_5 37 VDD2_5 64 VDD2_5 94 VDD2_5 119 VDD2_5 149 VDD2_5 171 VDD2_5 198 VDD_PLL 122 #SMICS0 #SMICS0 R4 VCC3 RAMCLK 118 CAS1/SDCS0 140 RAS1/SDCS1 138 RAS0/SDRAS 135 CAS0/SDCAS 139 R/W/SDWE 130 BE0/DQML 128 BE1/DQMH 129 WAIT 131 #SDRAS #SDCAS #SDWE DQML DQMH R/#W #WE #CE1 #CE3 #OE #ATAPI_RD #ATAPI |
Date | User | Rating | Comment |