Acer 7110 9410 9420 free download

File name 06203-MP ACER 7110_9410_9420.pdf

A B C D E MYALL2 Block Diagram CLK GEN. IDT CV125 4 Project Code TV Out PCB 4 Intel Mobile CPU Yonah 478 Celeron M 14 91.4G901.001 06203-MP CRT LCD 3 G792 19 4~5 14 FSB 400/533/667 MHz DDR II SO-DIMM 1 11 ~ 12 RAM BUS 533/667 MHz 13 CPU DC/DC ISL6262 37 ~ 38 INPUTS OUTPUTS DDR II SO-DIMM 2 11 ~ 12 3 Calistoga 945PM / 940GML 6 ~ 10 DMI 100 MHz PEG Nvidia G72M-V 46 ~ 48 , 51 ~ 55 VRAMx4 49 ~ 50 VCC_CORE DCBATOUT 0.844~1.3V 27A PCI BUS TI PCI7412 24 ~ 25 PWR SW CP2211 25 SYSTEM DC/DC PCMCIA SLOT 27 Card Reader26 MAX8744 INPUTS DCBATOUT OUTPUTS 3D3V_S5 5V_S5 35 3 a. Line In b. Mic In c. INT Mic Codec ALC883 29 28 HDA 1394 d. Line Out e. INT.SPKR 29 OP AMP G1421B MODEM MDC Card Intel 82801 GBM ICH7-M Mini-PCI 30 26 APL5331-KAC APL5912-KAC APL5308-25AC 40 INPUTS OUTPUTS 1D5V_S5 1D8V_S3 3D3V_S5 3D3V_S0 1D05V_S0 1D5V_S0 1D5V_S5 2D5V_S0 TV & Video-In WIRELESS TXFM 29 30 30 2 21 PCIE x 1 LAN RTL8111B 22 ~ 23 23 RJ45 23 APW7057-KC TPS51100DGQ APL5331-KAC 41 INPUTS OUTPUTS 5V_S5 5V_S5 5V_S5 1D8V_S0 3D3V_S5 1D8V_S3 0D9V 1D2V_S0 2 MINI CARD PCIE x 1 LPC BUS 26 SATA DEBUG CONN34 15 ~ 18 SIO NS87381 32 KBC KB3910 31 X BUS CHARGER ISL6255 INPUTS 42 OUTPUTS BT+ 16.8V 3A 1 FIR PCB Layer Stackup 1 32 BIOS 34 Touch INT. KB CIR Pad 33 33 33 DCBATOUT xa L1: Signal 1 L2: VCC L3: Signal 2 L4: Signal 3 L5: GND L6: Signal 4 A PATA USB Date: Tuesday, April 11, 2006 B C D Sheet E 1 he MYALL2 in Size Document Number f@ 21 13 BLOCK DIAGRAM ho Rev 24 ~ 25 20 20 Title tm MP of 57 SATA HDD CDROM MINI USB BlueTooth USB 4 Port21 CAMERA ai 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. l.c om Wistron Corporation A B ICH7-M EDS 17837 1.5V1 C D E ICH7M Integrated Pull-up and Pull-down Resistors EE_DIN, EE_DOUT, GNT[3:0], GPIO[25], GNT[4]#/GPIO48, GNT[5]#/GPO17, PME#, 954305D 27Mhz/LCDCLK Spread and Frequency Selection Table SS3 Byte9 bit 7 0 0 0 0 0 SS2 bit6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SS1 bit5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SS0 bit4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Spread Amount% -0.50 Down -1.00 Down -1.50 Down -2.00 Down -0.75 Down -1.25 Down -1.75 Down page 3 Calistoga Strapping Signals and EDS 17050 0.71 Configuration page 7 Pin Name CFG[2:0] Strap Description FSB Frequency Select 001 = FSB533 011 = FSB667 others = Reserved CFG[4:3] CFG5 CFG6 CFG7 CPU Strap Reserved Reserved DMI x2 Select Reserved 0 = Reserved 1 =Mobile CPU(Default) 0 = DMI x2 1 = DMI x4 (Default) Configuration ICH7 internal 20K pull-ups LAD[3:0]#/FHW[3:0]#, LAN_RXD[2:0] 4 LDRQ[0], LDRQ[1]/GPIO[41], PWRBTN#, TP[3] DD[7], DDREQ ACZ_BIT_CLK, ACZ_RST#, ACZ_SDIN[2:0], ACZ_SDOUT, ACZ_SYNC, DPRSLPVR/GPIO16, EE_CS,SPI_ARB, SPI_CLK, SPKR, USB[7:0][P,N] SATALED# LAN_CLK ICH7 internal 15K pull-downs ICH7 internal 11.5K pull-downs 4 0 ICH7 internal 20K pull-downs 0 0 1 1 1 ICH7 internal 15K pull-up ICH7 internal 100K pull-down 1 1 1 1 -2.25 Down +-0.25 Center CFG8 CFG9 PCI Express