Acer Aspire 5738 free download

File name ACER ASPIRE 5738.pdf

5 4 3 2 1 JV50 Block Diagram D Project code: 91.4CG01.001 PCB P/N : 48.4CG01.0SA REVISION : 08245-SA SYSTEM DC/DC ISL62392 INPUTS 5V_S5(6A) 3D3V_S5(7A) DCBATOUT 5V_AUX_S5 3D3V_AUX_S5 42 OUTPUTS CLK GEN. ICS9LPRS365B 3 Mobile CPU Penryn 4, 5 SMSC EMC2102 34 TOP GND S S PCB STACKUP SYSTEM DC/DC L1 L2 L3 L4 L5 L6 TPS51124 INPUTS DCBATOUT 43 OUTPUTS D 1D05V_S0(9A) 1D5V_S3(12A) HOST BUS 667/800/[email protected] VRAM 64MbX16X4 512M GND BOTTOM RT9026 1D5V_S3 44 DDR_VREF_S3 (1.2A) DDR3 800/1066 16,17 MHz Cantiga AGTL+ CPU I/F DDR Memory I/F INTEGRATED GRAHPICS LVDS, CRT I/F PCIex16 VGA N10M-GE-1 52~57 HDMI 20 RT9018 1D5V_S3 44 1D1V_S0(2A) DDR3 800/1066 16,17 MHz LCD 18 6,7,8,9,10,11 CRT 19 TPS51117 DCBATOUT FBVDD(4A) 45 X4 DMI 400MHz C-Link0 USB CardBus RTS5159 31 MS/MS Pro/xD /MMC/SD CHARGER ISL88731A INPUTS 47 OUTPUTS C C ICH9M LINE IN 29 6 PCIe ports PCI/PCI BRIDGE ACPI 2.0 4 SATA 12 USB 2.0/1.1 ports ETHERNET (10/100/1000MbE) DCBATOUT BT+ Giga LAN BCM5764 25 LAN TXFM 26 RJ45 26 CPU DC/DC ISL6266A INPUTS DCBATOUT 41 OUTPUTS VCC_CORE 38A Int MIC 18 Codec ALC888S 27 AZALIA High Definition Audio LPC I/F Serial Peripheral I/F Matrix Storage Technology(DO) Active Managemnet Technology(DO) New Card 32 PWR SW TPS2231 32 VGA_CORE RT8202A INPUTS DCBATOUT MIC In 29 47 OUTPUTS VGA_CORE 13A PCIe Mini 1 Card Wire LAN 33 Mini 2 Card 33 3G card INT.SPKR 1.5W 12,13,14,15 OP AMP MAX9789A 30 GFXCORE ISL6263A 46 OUTPUTS VCC_GFXCORE (7A) B B 29 LPC BUS LINE OUT 29 INPUTS SATA USB Mini USB Blue Tooth 23 RJ11 MODEM MDC Card 30 HDD SATA 21 Camera USB 4 Port 24 Winbond WPCE773 35 KBC SPI BIOS DCBATOUT (2MB) 36 MEDIA KEY 38 LPC DEBUG 36 CONN. SATA ODD SATA 22 Finger Printer 37 Touch Pad 37 INT. KB 35 A A JV50 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title BLOCK DIAGRAM Size A2 Date: 5 4 3 2 Document Number Rev JV50 Thursday, January 08, 2009 1 SB Sheet 1 of 60 A Signal HDA_SDOUT Usage/When Sampled XOR Chain Entrance/ PCIE Port Config1 bit1, Rising Edge of PWROK PCIE config1 bit0, Rising Edge of PWROK. PCIE config2 bit2, Rising Edge of PWROK. Reserved ESI Strap (Server Only) Rising Edge of PWROK Comment B page 92 ICH9M Functional Strap DefinitionsRev.1.5 ICH9 EDS 642879 ICH9M Integrated Pull-up and Pull-down Resistors ICH9 EDS 642879 C E CantigaDchipset and ICH9M I/O controller Hub strapping configuration Montevina Platform Design guide 22339 Rev.1.5 Pin Name CFG[2:0] Strap Description FSB Frequency Select Configuration 000 = FSB1067 011 = FSB667 010 = FSB800 others = Reserved page 218 0.5 Allows entrance to XOR Chain testing when TP3 pulled low.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers: offset 224h). This signal has weak internal pull-down This signal has a weak internal pull-down. Sets bit0 of RPC.PC(Config Registers:Offset 224h) This signal has a weak internal pull-up. Sets bit2 o