xerox 810622 Dandilion RS232 DMA Problems free download

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Date: 22 June 1981 1:14 pm PDT (Monday) From: Ogus.PA Subject: Dandelion RS232C DMA problem To: Wick. Lauer cc: Schwartz, Danielson, Garlick, Hutson, Charnley, DDavies, Yamanaka, Ogus I am forwarding Dan's message which sums up the findings of his RS232C DMA testing. Basically, due to an (undocumented) incompatibility between the Zilog SIO chip and the Intel DMA controller, it is not possible to reliably implement DMA transfers in the current system. There are two problems (see below), the first of which could perhaps be worked around in software. The second is not possible to fix reliably. Dan lists four approaches to attempt to obtain 56 kbps data ratcs. The first (Dan's #2) is to attempt to do so without using the Dma controller. using the current interrupt mechanism. The current code could be streamlirt(;u. and perhaps unnecessary function 1emoved throui:;h the use 0,' overlays. This would work with with the current hardware. all would be the quickest soluton to the problem. I recommend that this approach be focused on right now. The second (Dan's # 1) would be to ignore the setup time problem and to implement the software workaround. This solution would probably work in a lot of machines. but would not work in general. It cannot be used in a product. The third and fourth solutions involve redesign of hardware. The first redesign would involve attempting to salvage the DMA function through the use of other chips instead of the SIO. We would result in an another Options card which had the Dma capability, but still had the limitations of the current Options card (only one RS232C channel). There is also some risk in that the alternate chips are not yet available. The fourth approach is to expand the Dandelion by adding a high speed serial port which could handle several RS232C ports, including one (or more) at 56 kbps. We do not recommend designing another limited Options card, but favor the approach of "doing it right" and building the expanded RS232C capability. This would save the extra development effort and cost, and not produce an extra board which would soon be obsolete. We are working on the expanded system design schedule, and will need to discuss with you the match with the 56 kbps schedule requirements. Roy'. Date: 18 June 1981 2:20 pm PDT (Thursday) From: DDavies.PA Subject: Zilog SIO in Intel System To: Ogus cc: Garner, BELLEVILLE, DDavies Dandelion RS232C DMA problem 2 Roy, The Zilog SIO chip cannot be used in applications requiring DMA in our current Intel system. There are two fundemental problems. 1. The Zilog DMA chip inserts 3 clock cycles before any activity. The Intel 8257 does not. In a Zilog system, the SIO would have time after any access to prepare for the next one. The Intel DMA chip may start an access to the SIO one clock cycle after the processor has finished one. The exact SIO response to this is not known (we can't look inside t