AT&T Ethernet Expansion Board Theory of Operation free download

File name Ethernet_Expansion_Board_Theory_of_Operation.pdf

Contents Ethernet Expansion Board 1 Ethernet Interface 3 Interface I/O Description 3 Status and Command Circuitry 4 CPU Read/Write Access 4 LANCE Interrupt Status 4 Read/Write Control Register 4 State Machine Control Circuitry 4 LANCE Interface 6 Ethernet Interface 6 Software Interface 6 Expansion Slot 7 On-Board Addressing 7 Contents Interface Registers and Command Descriptions 7 ID Register (Base Address 03FFFF - 03FFCO) 8 Software Reset 8 LANCE Data Latch 9 Status Ring Address 9 Control Register 9 LANCE Register Address and Data Ports 10 Software Operation 10 Troubleshooting 11 I/O Cycle 11 Register Read/Write Cycle 13 Board ID Read-Only Cycle 14 CPU LANCE Read/Write Cycle 14 DMA Cycle 14 DMA Read/Write (Single) 15 DMA Read/Write (Burst) 17 Interrupt Cycle 17 Contents Figures 1 Expansion Board Block Diagram 2 2 Ethernet State Diagram 12 3 Expansion Board Cycle Diagram 16 4 CPU non-LANCE Read-Timing Diagram 18 5 CPU non - L ..~.NCE lA]y-;+-=-'T';TTl;-nrr ""'.&. ... ':;:11 ...L ' - " " " Diagram 19 6 CPU LANCE Read-Timing Diagram 20 7 CPU LANCE Write-Timing Diagram 21 8 LANCE DMA Read Cycle 22 9 LANCE DMA Write Cycle 23 Tables 1 Ethernet IS-Pin D Connector 6 2 Expansion Slot Offset Addresses 7 3 State Assignments 13 Ethernet Expansion Board Theory of Operation This overview summarizes the major functions performed by the UNIXTM PC Ethernet Expansion Board hardware. The topics covered here include: o Interface I/O description o Status and command ci