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DISCRETE SEMICONDUCTORS
DATA SHEET
BF904WR
N-channel dual-gate MOS-FET
Product specification 2010 Sep 15
Supersedes data of 1995 Apr 25
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF904WR
FEATURES PINNING
Specially designed for use at 5 V supply voltage PIN SYMBOL DESCRIPTION
Short channel transistor with high forward transfer 1 s, b source
admittance to input capacitance ratio
2 d drain
Low noise gain controlled amplifier up to 1 GHz
3 g2 gate 2
Superior cross-modulation performance during AGC.
4 g1 gate 1
APPLICATIONS
VHF and UHF applications with 3 to 7 V supply voltage handbook, halfpage d
such as television tuners and professional
communications equipment. 3 4
DESCRIPTION g2
Enhancement type field-effect transistor in a plastic g1
microminiature SOT343R package. The transistor
consists of an amplifier MOS-FET with source and 2 1
substrate interconnected and an internal bias circuit to
ensure good cross-modulation performance during AGC. Top view MAM192 s,b
Marking code: MC* * = - : made in Hong Kong
CAUTION * = p : made in Hong Kong
* = t : made in Malaysia
The device is supplied in an antistatic package. The
gate-source input must be protected against static
Fig.1 Simplified outline (SOT343R) and symbol.
discharge during transport or handling.
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VDS drain-source voltage 7 V
ID drain current 30 mA
Ptot total power dissipation 280 mW
Tj operating junction temperature 150 C
yfs forward transfer admittance 22 25 30 mS
Cig1-s input capacitance at gate 1 2.2 2.6 pF
Crs reverse transfer capacitance f = 1 MHz 25 35 fF
F noise figure f = 800 MHz 2 dB
2010 Sep 15 2
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF904WR
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDS drain-source voltage 7 V
ID drain current 30 mA
IG1 gate 1 current 10 mA
IG2 gate 2 current 10 mA
Ptot total power dissipation up to Tamb = 50 C; see Fig.2; 280 mW
note 1
Tstg storage temperature 65 +150 C
Tj operating junction temperature +150 C
Note
1. Device mounted on a printed-circuit board.
MLD150
300
handbook, halfpage
Ptot
(mW)
200
100
0
0 50 100 150 200
Tamb ( oC)
Fig.2 Power derating curve.
2010 Sep 15 3
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF904WR
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth j-a thermal resistance from junction to ambient note 1 350 K/W
Rth j-s thermal resistance from junction to soldering point Ts = 91 C; note 2 210 K/W
Notes
1. Device mounted on a printed-circuit board.
2. Ts is the temperature at the soldering point of the source lead.
STATIC CHARACTERISTICS
Tj = 25 C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V(BR)G1-SS gate 1-source breakdown voltage VG2-S = VDS = 0; IG1-S = 10 mA 6 15 V
V(BR)G2-SS gate 2-source breakdown voltage VG1-S = VDS = 0; IG2-S = 10 mA 6 15 V
V(F)S-G1 forward source-gate 1 voltage VG2-S = VDS = 0; IS-G1 = 10 mA 0.5 1.5 V
V(F)S-G2 forward source-gate 2 voltage VG1-S = VDS = 0; IS-G2 = 10 mA 0.5 1.5 V
VG1-S(th) gate 1-source threshold voltage VG2-S = 4V; VDS = 5 V; ID = 20 A 0.3 1 V
VG2-S(th) gate 2-source threshold voltage VG1-S = VDS = 5 V; ID = 20 A 0.3 1.2 V
IDSX drain-source current VG2-S = 4 V; VDS = 5 V; RG1 = 120 k; 8 13 mA
note 1
IG1-SS gate 1 cut-off current VG2-S = VDS = 0; VG1-S = 5 V 50 nA
IG2-SS gate 2 cut-off current VG1-S = VDS = 0; VG2-S = 5 V 50 nA
Note
1. RG connects gate 1 to VGG = 5 V.
DYNAMIC CHARACTERISTICS
Common source; Tamb = 25 C; VDS = 5 V; VG2-S = 4 V; ID = 10 mA; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
yfs forward transfer admittance pulsed; Tj = 25 C 22 25 30 mS
Cig1-s input capacitance at gate 1 f = 1 MHz 2.2 2.6 pF
Cig2-s input capacitance at gate 2 f = 1 MHz 1 1.5 2 pF
Cos drain-source capacitance f = 1 MHz 1 1.3 1.6 pF
Crs reverse transfer capacitance f = 1 MHz 25 35 fF
F noise figure f = 200 MHz; GS = 2 mS; BS = BSopt 1 1.5 dB
f = 800 MHz; GS = GSopt; BS = BSopt 2 2.8 dB
2010 Sep 15 4
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF904WR
MLD268 MRA769
40 0
gain
handbook, halfpage
Y fs reduction
(mS) (dB)
10
30
20
20
30
10 40
50
0
50 0 50 100 150 0 1 2 3 4
o VAGC (V)
T j ( C)
f = 50 MHz.
Tj = 25 C.
Fig.3 Forward transfer admittance as a function Fig.4 Typical gain reduction as a function of
of junction temperature; typical values. AGC voltage.
MRA771 MLD270
120 20
handbook, halfpage
Vunw ID V G2 S = 4 V 3V 2.5 V
(dB V) (mA)
2V
110 15
100 10
1.5 V
90 5
1V
80 0
0 10 20 30 40 50 0 0.4 0.8 1.2 1.6 2.0
gain reduction (dB) V G1 S (V)
VGG = 5 V; fw = 50 MHz.
funw = 60 MHz; Tamb = 25 C; RG1 = 120 k
VDS = 5 V.
Fig.5 Unwanted voltage for 1% cross-modulation Tj = 25 C.
as a function of gain reduction; typical
values; see Fig.19. Fig.6 Transfer characteristics; typical values.
2010 Sep 15 5
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF904WR
MLD269 MLD271
20
handbook, halfpage
150
handbook, halfpage
ID V G1 S = 1.4 V V G2 S = 4 V
(mA) I G1 3.5 V
16 (A)
1.3 V
100 3V
1.2 V
12
1.1 V
2.5 V
8
1.0 V
50
0.9 V 2V
4
0 0
0 2 4 6 8 10 0 0.5 1.0 1.5 2.0 2.5
V DS (V) V G1 S (V)
VDS = 5 V.
VG2-S = 4 V. Tj = 25 C.
Tj = 25 C.
Fig.8 Gate 1 current as a function of gate 1
Fig.7 Output characteristics; typical values. voltage; typical values.
MLD272 MLD273
40 16
handbook, halfpage handbook, halfpage
y fs ID
(mS) (mA)
V G2 S = 4 V
30 12
3.5 V
3V
20 2.5 V 8
10 4
2V
0 0
0 4 8 12 16 20 0 10 20 30 40 50
I D (mA) I G1 (A)
VDS = 5 V. VDS = 5 V; VG2-S = 4 V.
Tj = 25 C. Tj = 25 C.
Fig.9 Forward transfer admittance as a Fig.10 Drain current as a function of gate 1 current;
function of drain current; typical values. typical values.
2010 Sep 15 6
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF904WR
MLD275 MLD274
12
handbook, halfpage 20
handbook, halfpage
ID R G1 = 47 k 68 k
ID
(mA) 82 k
(mA)
15
100 k
8
120 k
150 k
10
180 k
220 k
4
5
0 0
0 1 2 3 4 5 0 2 4 6 8
VGG (V) V GG = V DS (V)
VDS = 5 V; VG2-S = 4 V. VG2-S = 4 V.
RG1 = 120 k (connected to VGG); Tj = 25 C. RG1 connected to VGG; Tj = 25 C.
Fig.11 Drain current as a function of gate 1 Fig.12 Drain current as a function of gate 1
supply voltage (= VGG); typical values; (= VGG) and drain supply voltage;
see Fig.19. typical values; see Fig.19.
MLD276
MLB945
12 40
handbook, halfpage handbook, halfpage
V GG = 5 V
4.5 V I G1
ID
(A) V GG = 5 V
(mA) 4V
3.5 V 30
4.5 V
8 3V
4V
20 3.5 V
3V
4
10
0 0
0 2 4 6 0 2 4 6
V G2 S (V) V G2 S (V)
VDS = 5 V; Tj = 25 C. VDS = 5 V; Tj = 25 C.
RG = 120 k (connected to VGG). RG = 120 k (connected to VGG).
Fig.13 Drain current as a function of gate 2 voltage; Fig.14 Gate 1 current as a function of gate 2
typical values; see Fig.19. voltage; typical values; see Fig.19.
2010 Sep 15 7
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF904WR
MLD277 MLD278
10 2
handbook, halfpage 10 3 10 3
y is y rs rs
(mS) (S) (deg)
rs
10 10 2 10 2
b is y rs
1 10 10
g is
10 1 1 1
10 102 f (MHz) 10 3 10 102 f (MHz) 10 3
VDS = 5 V; VG2 = 4 V. VDS = 5 V; VG2 = 4 V.
ID = 10 mA; Tamb = 25 C. ID =10 mA; Tamb = 25 C.
Fig.15 Input admittance as a function of frequency; Fig.16 Reverse transfer admittance and phase as
typical values. a function of frequency; typical values.
MLD279 MLD280
10 2 10 2 10
handbook, halfpage
yos
y fs fs (mS)
y fs (deg) bos
(mS)
1
10 fs 10
gos
10 1
1 1 10 2
10 102 10 3 10 102 f (MHz) 10 3
f (MHz)
VDS = 5 V; VG2 = 4 V. VDS = 5 V; VG2 = 4 V.
ID = 10 mA; Tamb = 25 C. ID = 10 mA; Tamb = 25 C.
Fig.17 Forward transfer admittance and phase as Fig.18 Output admittance as a function of
a function of frequency; typical values. frequency; typical values.
2010 Sep 15 8
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF904WR
VAGC
R1
10 k C1
4.7 nF C3 12 pF
C2 L1 RL
DUT
450 nH 50
R GEN R2 4.7 nF C4
R G1
50 50
4.7 nF
VI
VGG V DS MLD171
Fig.19 Cross-modulation test set-up.
2010 Sep 15 9
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF904WR
Table 1 Scattering parameters: VDS =5 V; VG2-S = 4 V; ID = 10 mA
s11 s21 s12 s22
f
(MHz) MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE
(ratio) (deg) (ratio) (deg) (ratio) (deg) (ratio) (deg)
40 0.989 3.4 2.420 175.7 0.000 79.9 0.993 1.6
100 0.985 8.3 2.414 169.1 0.001 78.3 0.992 3.9
200 0.976 16.4 2.368 158.8 0.003 80.3 0.987 7.8
300 0.958 24.1 2.301 148.5 0.004 73.7 0.980 11.4
400 0.942 32.0 2.251 138.8 0.005 70.7 0.974 15.2
500 0.918 39.3 2.170 129.5 0.005 67.2 0.966 18.7
600 0.899 46.0 2.080 120.7 0.005 67.8 0.958 22.2
700 0.876 52.6 2.001 112.1 0.005 68.6 0.951 25.5
800 0.852 58.8 1.924 103.2 0.005 72.9 0.944 28.9
900 0.823 64.9 1.829 94.7 0.005 78.7 0.937 32.1
1000 0.800 70.9 1.747 86.5 0.005 88.3 0.933 35.2
1200 0.750 82.4 1.621 70.7 0.005 120.5 0.928 41.7
1400 0.719 92.7 1.535 54.6 0.008 139.8 0.930 48.4
1600 0.682 102.5 1.424 39.4 0.010 137.8 0.924 54.9
1800 0.642 109.8 1.349 22.5 0.013 156.8 0.928 62.9
2000 0.602 116.5 1.283 1.1 0.018 175.1 0.928 73.1
2200 0.547 124.9 1.130 15.1 0.014 172.6 0.887 81.0
2400 0.596 128.7 1.018 49.1 0.040 163.9 0.837 95.8
2600 0.682 132.6 0.979 79.4 0.077 164.0 0.778 109.6
2800 0.771 142.5 0.804 116.2 0.120 178.8 0.629 119.5
3000 0.793 157.5 0.541 153.5 0.149 158.3 0.479 119.9
Table 2 Noise data: VDS = 5 V; VG2-S = 4 V; ID = 10 mA
f Fmin opt
rn
(MHz) (dB) (ratio) (deg)
800 2.00 .686 49.6 50.40
2010 Sep 15 10
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF904WR
PACKAGE OUTLINE
Plastic surface-mounted package; reverse pinning; 4 leads SOT343R
D B E A X
y HE v M A
e
3 4
Q
A
A1
c
2 1
w M B bp b1 Lp
e1
detail X
0 1 2 mm
scale
DIMENSIONS (mm are the original dimensions)
A1
UNIT A bp b1 c D E e e1 HE Lp Q v w y
max
1.1 0.4 0.7 0.25 2.2 1.35 2.2 0.45 0.23
mm 0.1 1.3 1.15 0.2 0.2 0.1
0.8 0.3 0.5 0.10 1.8 1.15 2.0 0.15 0.13
OUTLINE REFERENCES EUROPEAN
ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION
97-05-21
SOT343R
06-03-16
2010 Sep 15 11
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF904WR
DATA SHEET STATUS
DOCUMENT PRODUCT
DEFINITION
STATUS(1) STATUS(2)
Objective data sheet Development This document contains data from the objective specification for product
development.
Preliminary data sheet Qualification This document contains data from the preliminary specification.
Product data sheet Production This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
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2010 Sep 15 12
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF904WR
Limiting values Stress above one or more limiting Quick reference data The Quick reference data is an
values (as defined in the Absolute Maximum Ratings extract of the product data given in the Limiting values and
System of IEC 60134) will cause permanent damage to Characteristics sections of this document, and as such is
the device. Limiting values are stress ratings only and not complete, exhaustive or legally binding.
(proper) operation of the device at these or any other
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Characteristics sections of this document is not warranted.
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Constant or repeated exposure to limiting values will
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2010 Sep 15 13
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