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MSI
Dual 4-bit static shift register
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
· The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC · The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4015B MSI Dual 4-bit static shift register
Product specification File under Integrated Circuits, IC04 January 1995
Philips Semiconductors
Product specification
Dual 4-bit static shift register
DESCRIPTION The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (O0 to O3) and an overriding asynchronous master reset input (MR). Information
HEF4015B MSI
present on D is shifted to the first register position, and all the data in the register is shifted one position to the right on the LOW-to-HIGH transition of CP. A HIGH on MR clears the register and forces O0 to O3 to LOW, independent of CP and D. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
Fig.2 Pinning diagram.
HEF4015BP(N): HEF4015BD(F): HEF4015BT(D): Fig.1 Functional diagram.
16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
PINNING DA, DB MRA, MRB CPA, CPB O0A, O1A, O2A, O3A O0B, O1B, O2B, O3B serial data input master reset input (active HIGH) clock input (LOW-to-HIGH edge-triggered) parallel outputs parallel outputs
FAMILY DATA, IDD LIMITS category MSI See Family Specifications
APPLICATION INFORMATION Some examples of applications for the HEF4015B are: · Serial-to-parallel converter · Buffer stores · General purpose register
January 1995
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Philips Semiconductors
Product specification
Dual 4-bit static shift register
LOGIC DIAGRAM (one register)
HEF4015B MSI
Fig.3 Logic diagram.
FUNCTION TABLE INPUTS n 1 2 3 4 CP D D1 D2 D3 D4 X X X MR L L L L L H L O0 D1 D2 D3 D4 OUTPUTS O1 X D1 D2 D3 O2 X X D1 D2 O3 X X X D1
Note 1. H = HIGH state (the more positive voltage) 2. L = LOW state (the less positive voltage) 3. X = state is immaterial 4. 5. = positive-going transition = negative-going transition
6. Dn = either HIGH or LOW 7. n = number of clock pulse transitions
no change L L L
January 1995
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Philips Semiconductors
Product specification
Dual 4-bit static shift register
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays CP On HIGH to LOW 5 10 15 5 LOW to HIGH MR On HIGH to LOW Output transition times HIGH to LOW 10 15 5 10 15 5 10 15 5 LOW to HIGH Set-up time D CP Hold time D CP Minimum clock pulse width; LOW Minimum MR pulse width; HIGH Recovery time for MR Maximum clock pulse frequency 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 fmax tRMR tWMRH tWCPL thold tsu 25 25 20 40 20 15 60 30 20 80 30 24 50 30 20 7 15 22 tTLH tTHL tPHL tPLH tPHL 130 55 40 120 55 40 105 45 35 60 30 20 60 30 20 -15 -10 -5 20 10 8 30 15 10 40 15 12 20 10 5 15 30 44 260 110 80 240 110 80 210 90 70 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz 103 ns + 44 ns + 32 ns + 93 ns + 44 ns + 32 ns + 78 ns + 34 ns + 27 ns + 9 ns + 6 ns + 10 ns + 9 ns + 6 ns + SYMBOL MIN. TYP. MAX.
HEF4015B MSI
TYPICAL EXTRAPOLATION FORMULA (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (0,42 ns/pF) CL (0,28 ns/pF) CL (1,0 ns/pF) CL (0,42 ns/pF) CL (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
see waveforms Figs 4 and 5
January 1995
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Philips Semiconductors
Product specification
Dual 4-bit static shift register
HEF4015B MSI
VDD V Dynamic power dissipation per package (P) 5 10 15
TYPICAL FORMULA FOR P (µW) 1 500 fi + (foCL) × VDD2 6 300 fi + (foCL) × 17 000 fi + (foCL) × VDD2 VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V)
Fig.4
Waveforms showing set-up times, hold times and minimum clock pulse width. Set-up and hold times are shown as positive values but may be specified as negative values.
Fig.5 Waveforms showing recovery time for MR and minimum MR pulse width.
January 1995
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