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INTEGRATED CIRCUITS
DATA SHEET
TDA8043 Satellite Demodulator and Decoder (SDD)
Preliminary specification File under Integrated Circuits, IC02 1997 Feb 25
Philips Semiconductors
Preliminary specification
Satellite Demodulator and Decoder (SDD)
FEATURES · One chip Digital Video Broadcasting (DVB) compliant demodulator and concatenated Viterbi/Reed-Solomon decoder with de-interleaver and de-randomizer · 3.3 V supply voltage (up to 5 V allowed) · Internal clock divider · On-chip crystal oscillator · QPSK/BPSK demodulator: Interpolator to handle variable symbol rates without an external anti-aliasing filter On-chip Automatic Gain Control (AGC) of the analog input I and Q baseband signals or tuner AGC control Two on-chip matched A/D converters (7 bits) Square-Root Raised-Cosine Nyquist filter with programmable roll-off factor High maximum symbol frequency: 32 Msymbols/s Can be used at low channel Es/No (Symbol energy-to-noise ratio) Internal carrier recovery, clock recovery and AGC loops with programmable loop filters Two carrier recovery loops enabling phase tracking of the incoming symbols Different modulation schemes: Quarter Phase Shift Keying (QPSK) and Bi-phase Shift Keying (BPSK) Signal-to-noise ratio (S/R) estimation External indication of demodulator lock · Viterbi decoder: Rate 1/2 convolutional code based Constraint length K = 7 with G1 = 171oct and G2 = 133oct Supported puncturing code rates: 1/2, 2/3, 3/4, 4/5, 5/6, 6/ , 7/ and 8/ 7 8 9 4 bit inputs for `soft decision' for both I and Q Truncation length: 144 Automatic synchronization Channel BER (Bit Error Rate) estimation External indication of Viterbi sync lock Differential decoding supported · Reed Solomon (RS) decoder: (204, 188, T = 8) Reed Solomon code
TDA8043
Automatic (I2C-bus configurable) synchronization of bytes, transport packets and frames Internal convolutional de-interleaving (I = 12; using internal memory) De-randomizer based on Pseudo Random Binary Sequence (PRBS) External indication of RS decoder sync lock External indication of uncorrectable errors (transport error indicator is set) Indication of the number of lost blocks Indication of the number of corrected blocks/bytes · I2C-bus interface: I2C-bus interface initializes and monitors the demodulator and Forward Error Correction (FEC) decoder with stand-by mode; when no I2C-bus is used, default mode is defined 4 bits I/O expander for flexible access to and from the I2C-bus · Package: PLCC84 · Boundary scan test. APPLICATIONS · Demodulation and error correction for digital satellite TV.
1997 Feb 25
2
Philips Semiconductors
Preliminary specification
Satellite Demodulator and Decoder (SDD)
GENERAL DESCRIPTION This document specifies a DVB compliant demodulator and error correction decoder IC for reception of QPSK and BPSK modulated signals for satellite applications. The SDD (Satellite Demodulator and Decoder) can handle variable symbol rates without adapting the analog filters within the tuner. Typical applications for this device are: · Single-cast: one QPSK/BPSK modulated signal in a single channel · Multi-cast: two or more QPSK/BPSK modulated signals in a single channel · Simul-cast: QPSK/BPSK modulated signal together with a Frequency Modulated (FM) signal in a single channel. The SDD requires the two I and Q analog quadrature demodulated baseband signals as an input and provides 8-bit wide MPEG2 transport packet data at the output. The output of the SDD can be directly connected to the descrambler (SAA7206) or the demultiplexer (SAA7205). QUICK REFERENCE DATA SYMBOL VDDA VDDD IDD fclk rs IL Ptot Tstg Tamb Tj S/N Notes 1. This implementation was measured in a laboratory environment. 2. These values are specified for a symbol rate of 27.5 MSymbols/s. ORDERING INFORMATION TYPE NUMBER TDA8043K 1997 Feb 25 PACKAGE NAME PLCC84 DESCRIPTION plastic leaded chip carrier; 84 leads 3 PARAMETER analog supply voltage digital supply voltage supply current clock frequency symbol rate implementation loss Nyquist roll-off (programmable) total power dissipation storage temperature operating ambient temperature operating junction temperature signal-to-noise ratio for locking the SDD (QPSK) Tamb = 70°C Tamb = 70°C; note 2 note 2 VDD = 3.3 V; note 2 CONDITIONS(1) MIN. 3.0 3.0 - - 3 - - - -55 - - tbf TYP. 3.3 3.3 480 - - 0.3 1.5 - - - -
TDA8043
The output can also be used to monitor internal data, for example I/Q after demodulation, data after Viterbi decoding and data after de-interleaving. The SDD requires a single clock frequency which is independent to the received symbol rate as long as the clock frequency is slightly higher than twice the highest symbol frequency. This makes it possible to use a clock signal which already exists within the complete system. All loops to recover the data from the received symbols are internal. No external loop components are required. Loop parameters for the clock and carrier recovery can be controlled by I2C-bus. The SDD can be controlled and monitored by I2C-bus. An I2C-bus default mode is specified which makes it possible to use the device with a minimum of software control. A 4-bit bidirectional I/O expander and an interrupt line is available. By sending an interrupt signal, the SDD can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C-bus.
MAX. 3.6 3.6 - 65 32 - tbf +150 70 125 - V V mA
UNIT
MHz Msymbols/s dB % mW °C °C °C dB
35 or 50 50
VERSION SOT189-2
Philips Semiconductors
Preliminary specification
Satellite Demodulator and Decoder (SDD)
PINNING SYMBOL VDDD1 VSSD1 VAGC VDDD2 VDDD3 OUTSD I0 I1 I2 I3 VSSD2 I4 I5 I6 Q0 VDDD4 Q1 Q2 Q3 Q4 VSSD3 Q5 Q6 VSSD4 VDDD5 VDDD6 PRESET P3 P2 P1 P0 VDDD7 PKTBCLK PKTDAT0 PKTDAT1 PKTDAT2 VSSD5 PKTDAT3 PKTDAT4 PKTDAT5 1997 Feb 25 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O - - O - - O I I I I - I I I I - I I I I - I I - - - I I/O I/O I/O I/O - O O O O - O O O digital supply voltage 1 digital ground 1 AGC output voltage digital supply voltage 2 digital supply voltage 3 general purpose Sigma-Delta output digital bypass I-input ADC (bit 0) digital bypass I-input ADC (bit 1) digital bypass I-input ADC (bit 2) digital bypass I-input ADC (bit 3) digital ground 2 digital bypass I-input ADC (bit 4) digital bypass I-input ADC (bit 5) digital bypass I-input ADC (bit 6) digital bypass Q-input ADC (bit 0) digital supply voltage 4 digital bypass Q-input ADC (bit 1) digital bypass Q-input ADC (bit 2) digital bypass Q-input ADC (bit 3) digital bypass Q-input ADC (bit 4) digital ground 3 digital bypass Q-input ADC (bit 5) digital bypass Q-input ADC (bit 6) digital ground 4 digital supply voltage 5 digital supply voltage 6 set device into default mode quasi-bidirectional I/O port (bit 3) quasi-bidirectional I/O port (bit 2) quasi-bidirectional I/O port (bit 1) quasi-bidirectional I/O port (bit 0) digital supply voltage 7 output clock for transport stream bytes (to SAA7205H) parallel data output to SAA7205H (bit 0) parallel data output SAA7205H (bit 1) parallel data output SAA7205H (bit 2) digital ground 5 parallel data output SAA7205H (bit 3) parallel data output SAA7205H (bit 4) parallel data output SAA7205H (bit 5) 4 DESCRIPTION
TDA8043
Philips Semiconductors
Preliminary specification
Satellite Demodulator and Decoder (SDD)
TDA8043
SYMBOL PKTDAT6 VDDD8 VSSD6 VDDD9 VDDD10 PKTDAT7 PKTBAD PKTDATV PKTSYNC VSSD7 SCL SDA INT A0 RSLOCK VLOCK DLOCK VDDD11 TEST TRST TCK VDDD12 VDDD13 VSSD8 VSSD9 TMS TDO TDI VDDD14 VSSD10 VSSD(AD) VDDD(AD) Vref(N) VSSA1 QA Vref(M) IA VSSA2 IBIAS VDDA VDDCL 1997 Feb 25
PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81
I/O O - - - - O O O O - I I/O O I O O O - I I I - - - - I O I - - - - I - I I I - I - - digital supply voltage 8 digital ground 6 digital supply voltage 9 digital supply voltage 10
DESCRIPTION parallel data output SAA7205H (bit 6)
parallel data output SAA7205H (bit 7) transport error indicator SAA7205H data valid indicator SAA7205H transport packet synchronisation signal SAA7205H digital ground 7 serial clock of I2C-bus serial data of I2C-bus interrupt output (active LOW) I2C hardware address Reed-Solomom lock indicator Viterbi lock indicator demodulator lock indicator digital supply voltage 11 test pin (normally connected to ground) optional asynchronous resettlement (normally connected to ground) dedicated test clock (normally connected to ground) digital supply voltage 12 digital supply voltage 13 digital ground 8 digital ground 9 input control signal (normally connected to ground) serial test data out serial test data in (normally connected to ground) digital supply voltage 14 digital ground 10 digital ground A/D converter digital supply A/D converter negative reference voltage for ADC analog ground 1 analog input Q mid-range reference voltage for ADC analog input I analog ground 2 external reference current for ADC analog supply voltage supply voltage for crystal oscillator 5
Philips Semiconductors
Preliminary specification
Satellite Demodulator and Decoder (SDD)
TDA8043
SYMBOL XTALI XTALO VDDXTAL
PIN 82 83 84
I/O I O - clock oscillator input clock oscillator output
DESCRIPTION
supply voltage for crystal oscillator
84 VDDXTAL
6 OUTSD
5 VDDD3
4 VDDD2
1 VDDD1
81 VDDCL
75 QA 74 VSSA1 73 Vref(N) 72 VDDD(AD) 71 VSSD(AD) 70 VSSD10 69 VDDD14 68 TDI 67 TDO 66 TMS 65 VSSD9 64 VSSD8 63 VDDD13 62 VDDD12 61 TCK 60 TRST 59 TEST 58 VDDD11 57 DLOCK 56 VLOCK 55 RSLOCK 54 A0 INT 53
MGD963
handbook, full pagewidth
I4 12 I5 13 I6 14 Q0 15 VDDD4 16 Q1 17 Q2 18 Q3 19 Q4 20 VSSD3 21 Q5 22 Q6 23 VSSD4 24 VDDD5 25 VDDD6 26 PRESET 27 P3 28 P2 29 P1 30 P0 31 VDDD7 32 PKTBCLK 33 PKTDAT0 34 PKTDAT1 35 PKTDAT2 36 VSSD5 37 PKTDAT3 38 PKTDAT4 39 PKTDAT5 40 PKTDAT6 41 VDDD8 42 VSSD6 43 VDDD9 44 VDDD10 45 PKTDAT7 46 PKTBAD 47 PKTDATV 48 PKTSYNC 49 VSSD7 50 SCL 51 SDA 52
TDA8043
Fig.1 Pin configuration.
1997 Feb 25
6
76 Vref(M)
11 VSSD2
2 VSSD1
83 XTALO
78 VSSA2
3 VAGC
82 XTALI
80 VDDA
79 IBIAS
77 IA
10 I3
9 I2
8 I1
7 I0
Philips Semiconductors
Preliminary specification
Satellite Demodulator and Decoder (SDD)
APPLICATION INFORMATION
TDA8043
B(1)
handbook, full pagewidth +3.3 V
VDDD 15 µF B(1) 15 pF VDD(AD) 15 µF VDDD C(3) VDDD C(3) 10 nF 4.7 pF L(4)
+3.3 V B(1) 10 10 nF 15 µF 100 nF 100 nF 220 nF 100 nF +3.3 V
+3.3 V
XTAL(2)
11 12 13 14 15 VDDD 16 C(3) 17 18 19 20 21 22 23 VDDD 24 25 26 C(3) 27 28 29 30 31 VDDD 32 C(3) 33
10
9
8
7
6
5
4
3
2
1
84
83
82
81
80
79
78
77
76
75 74 73 72 71 70 69 68 67 66 65 VDDD C(3) VDD(AD) C(3) C(3)
TDA8043
64 63 62 61 60 59 58 57 56 55 54 VDDD C(3) VDDD C(3)
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
C(3) VDDD packet data and control outputs I2C-bus
interrupt
MGG995
(1) B = SMB bead type CBD8.9/3/3 Grade 4S2. (2) X-tal = 65 MHz, 3rd harmonic.
(3) C = 6.8 nF, SMD. (4) L = 560 nH, Talyo Yuden LAL02.
Fig.2 Application diagram
1997 Feb 25
7
Philips Semiconductors
Preliminary specification
Satellite Demodulator and Decoder (SDD)
TDA8043
handbook, full pagewidth
4 Mbit EPROM
4 Mbit DRAM
16 Mbit SDRAM
16 8+3 I TUNER Q TDA8043 (SDD) 8 SAA7205 or SAA 7206 8 Ctrl SAA7201 H, V valid
16
I2S-bus
AUDIO DA
L R
27 MHz CVBS I2C-bus high speed data H, V TTX/TTXRQ
YUV
CVBS SAA7183 (EURO-DENC)
MGG996
Y/C RGB
Fig.3 Satellite set-top decoder concept.
1997 Feb 25
8
Philips Semiconductors
Preliminary specification
Satellite Demodulator and Decoder (SDD)
TDA8043
handbook, full pagewidth
TSA5522
×
Vtune SYNTHESIZER switch output
ADC SAW SAW
AFC DET.
AGC DET.
×
TDA8042
×
AGC DET.
AGC current
FM DEMODULATOR
TDA8012
TUNER
CVBS
XTAL OSC
ADC LOOP FILTER AND AGC
ADC I2C-bus
QPSK DEMODULATOR
FORWARD ERROR CORRECTION
TDA8043 (SDD)
MGG997
Control for external AGC is also available using the internal sigma-delta converter.
Fig.4 Application of satellite demodulator and decoder including tuner.
1997 Feb 25
9
Philips Semiconductors
Preliminary specification
Satellite Demodulator and Decoder (SDD)
PACKAGE OUTLINE PLCC84: plastic leaded chip carrier; 84 leads
TDA8043
SOT189-2
eD y 74 75 X 54 53 Z E A
eE
bp b1 w M 84 HE A A4 A1 (A 3) k1 Lp detail X 12 e D HD 0 5 scale DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT
mm
1
pin 1 index e
E
k
11 32 ZD
33
v M A B v M B 10 mm
A
4.57 4.19
A1 min.
0.51
A3
0.25
A4 max.
3.30
bp
0.53 0.33
b1
0.81 0.66
D (1)
E (1)
e
eD
eE
HD
HE
k
k1 max.
0.51
Lp
1.44 1.02
v
0.18
w
0.18
y
0.10
Z D(1) Z E (1) max. max.
2.16 2.16
29.41 29.41 28.70 28.70 30.35 30.35 1.22 1.27 29.21 29.21 27.69 27.69 30.10 30.10 1.07
45 o
0.180 inches 0.020 0.01 0.165
1.130 1.130 1.195 1.195 0.048 0.057 0.021 0.032 1.158 1.158 0.020 0.05 0.007 0.007 0.004 0.085 0.085 0.13 1.090 1.090 1.185 1.185 0.042 0.040 0.013 0.026 1.150 1.150
Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. OUTLINE VERSION SOT189-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-03-11
1997 Feb 25
10
Philips Semiconductors
Preliminary specification
Satellite Demodulator and Decoder (SDD)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all PLCC packages. The choice of heating method may be influenced by larger PLCC packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering
TDA8043
Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: · A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. · The longitudinal axis of the package footprint must be parallel to the solder flow. · The package footprint must incorporate solder thieves at the downstream corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.
1997 Feb 25
11
Philips Semiconductors
Preliminary specification
Satellite Demodulator and Decoder (SDD)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA8043
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1997 Feb 25
12
Philips Semiconductors
Preliminary specification
Satellite Demodulator and Decoder (SDD)
NOTES
TDA8043
1997 Feb 25
13
Philips Semiconductors
Preliminary specification
Satellite Demodulator and Decoder (SDD)
NOTES
TDA8043
1997 Feb 25
14
Philips Semiconductors
Preliminary specification
Satellite Demodulator and Decoder (SDD)
NOTES
TDA8043
1997 Feb 25
15
Philips Semiconductors a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 © Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547047/1200/01/pp16
Date of release: 1997 Feb 25
Document order number:
9397 750 01357