Philips TDA8043 free download

File name TDA8043.pdf

INTEGRATED CIRCUITS DATA SHEET TDA8043 Satellite Demodulator and Decoder (SDD) Preliminary specification File under Integrated Circuits, IC02 1997 Feb 25 Philips Semiconductors Preliminary specification Satellite Demodulator and Decoder (SDD) FEATURES · One chip Digital Video Broadcasting (DVB) compliant demodulator and concatenated Viterbi/Reed-Solomon decoder with de-interleaver and de-randomizer · 3.3 V supply voltage (up to 5 V allowed) · Internal clock divider · On-chip crystal oscillator · QPSK/BPSK demodulator: ­ Interpolator to handle variable symbol rates without an external anti-aliasing filter ­ On-chip Automatic Gain Control (AGC) of the analog input I and Q baseband signals or tuner AGC control ­ Two on-chip matched A/D converters (7 bits) ­ Square-Root Raised-Cosine Nyquist filter with programmable roll-off factor ­ High maximum symbol frequency: 32 Msymbols/s ­ Can be used at low channel Es/No (Symbol energy-to-noise ratio) ­ Internal carrier recovery, clock recovery and AGC loops with programmable loop filters ­ Two carrier recovery loops enabling phase tracking of the incoming symbols ­ Different modulation schemes: Quarter Phase Shift Keying (QPSK) and Bi-phase Shift Keying (BPSK) ­ Signal-to-noise ratio (S/R) estimation ­ External indication of demodulator lock · Viterbi decoder: ­ Rate 1/2 convolutional code based ­ Constraint length K = 7 with G1 = 171oct and G2 = 133oct ­ Supported puncturing code rates: 1/2, 2/3, 3/4, 4/5, 5/6, 6/ , 7/ and 8/ 7 8 9 ­ 4 bit inputs for `soft decision' for both I and Q ­ Truncation length: 144 ­ Automatic synchronization ­ Channel BER (Bit Error Rate) estimation ­ External indication of Viterbi sync lock ­ Differential decoding supported · Reed Solomon (RS) decoder: ­ (204, 188, T = 8) Reed Solomon code TDA8043 ­ Automatic (I2C-bus configurable) synchronization of bytes, transport packets and frames ­ Internal convolutional de-interleaving (I = 12; using internal memory) ­ De-randomizer based on Pseudo Random Binary Sequence (PRBS) ­ External indication of RS decoder sync lock ­ External indication of uncorrectable errors (transport error indicator is set) ­ Indication of the number of lost blocks ­ Indication of the number of corrected blocks/bytes · I2C-bus interface: ­ I2C-bus interface initializes and monitors the demodulator and Forward Error Correction (FEC) decoder with stand-by mode; when no I2C-bus is used, default mode is defined ­ 4 bits I/O expander for flexible access to and from the I2C-bus · Package: PLCC84 · Boundary scan test. APPLICATIONS · Demodulation and error correction for digital satellite TV. 1997 Feb 25 2 Philips Semiconductors Preliminary specification Satellite Demodulator and Decoder (SDD) GENERAL DESCRIPTION This document specifies a DVB compliant demodulator and error correction decoder IC for reception of QPSK and BPSK modulated signals for satellite applications. The SDD (Satellite Demodulator and Decoder) can handle variable symbol rates without ad