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6x86MX BIOS WRITER’S GUIDE
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Application Note 103 6x86MX BIOS WRITER'S GUIDE
Table of Contents 1.0 1.1 1.2 1.3 2.0 3.0 3.1 3.2 3.3 3.4 3.5 4.0 4.1 4.2 4.3 4.4 4.5 5.0 5.1 5.2 5.3 6.0 6.1 6.2 6.3 6.4 6.5 Introduction Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Cyrix Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Summary of 6x86MX and 6x86 Differences . . . . . . . . . . . . . . . . . . . . . 6 Cache Unit Cyrix 6x86MX CPU Detection Detecting the Cyrix 6x86MX - Method 1 . . . . . . . . . . . . . . . . . . . . . . . 8 Detecting the Cyrix 6x86MX - Method 2 . . . . . . . . . . . . . . . . . . . . . . 10 EDX Value Following Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Determining 6x86MX Operating Frequency . . . . . . . . . . . . . . . . . . . . 13 Device Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6x86MX Configuration Register Index Assignments Accessing a Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6x86MX Configuration Register Index Assignments . . . . . . . . . . . . . 15 Configuration Control Registers (CCR0-6) . . . . . . . . . . . . . . . . . . . . . 17 Address Region Registers (ARR0-7) . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Region Control Registers (RCR0-7) . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Recommended 6x86MX Configuration Register Settings PC Memory Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 General Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Recommended Bit Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Model Specific Registers Time Stamp Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Performance Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Performance Monitoring Counters 1 and 2 . . . . . . . . . . . . . . . . . . . . . 44 Counter Event Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 PM Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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Cyrix 6x86MX Application Note 103 - BIOS WRITER'S GUIDE
7.0 7.1 7.2 7.3 7.4
Programming Model Differences Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Configuring Internal 6x86MX Features . . . . . . . . . . . . . . . . . . . . . . . 50 INVD and WBINVD Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Control Register 0 (CR0) CD and NW Bits . . . . . . . . . . . . . . . . . . . . 51
Appendixes Appendix A -Sample Code: Detecting a Cyrix CPU . . . . . . . . . . . . . . . . . . . 52 Appendix B -Sample Code: Determining CPU MHz . . . . . . . . . . . . . . . . . . . 54 Appendix C -Example CPU Type and Frequency Detection Program . . . . . . 57 Appendix D -Sample Code: Programming 6x86MX Configuration Registers 59 Appendix E -Sample Code: Controlling the L1 Cache. . . . . . . . . . . . . . . . . . 60 Appendix F -Example Configuration Register Settings . . . . . . . . . . . . . . . . . 61 Appendix G -Sample Code: Detecting L2 Cache Burst Mode . . . . . . . . . . . . 62
Cyrix 6x86MX Application Note 103 - BIOS WRITER'S GUIDE
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APPLICATION NOTE 103
BIOS Writer's Guide
1 Introduction 1.1 Scope
This document is intended for 6x86MX system BIOS writers. It is not a stand-alone document, but a supplement to other Cyrix documentation including the 6x86MX Data Book, and Cyrix SMM Programmer's Guide. This document highlights the programming differences between the 6x86 and the 6x86MX. Recommendations for 6x86MX detection and configuration register settings are included. The recommended settings are optimized for performance and compatibility in Windows95 or Windows NT, Plug and Play (Pnp), PCI-based system. Performance optimization, CPU detection, chipset initialization, memory discovery, I/O recovery time, and other functions are described in detail.
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Cyrix 6x86MX Application Note 103 - BIOS WRITER'S GUIDE
Cyrix Configuration Registers
1.2 Cyrix Configuration Registers
The 6x86MX uses on-chip configuration registers to control the on-chip cache, system management mode (SMM), device identification, and other 6x86MX specific features. The on-chip registers are used to activate advanced performance features. These performance features may be enabled "globally" in some cases, or by a user-defined address region. The flexible configuration of the 6x86MX is intended to fit a wide variety of systems.
The Importance of Non-Cacheable Regions
The 6x86MX has eight internal user-defined Address Region Registers. Among other attributes, the regions define cacheability of the address regions. Using this cacheability information, the 6x86MX is able to implement high performance features, that would otherwise not be possible. A non-cacheable region implies that read sourcing from the write buffers, data forwarding, data bypassing, speculative reads, and fill buffer streaming are disabled for memory accesses within that region. Additionally, strong cycle ordering is also enforced. Although negating KEN# during a memory access on the bus prevents a cache line fill, it does not fully disable these performance features. In other words, negating KEN# is NOT equivalent to establishing a non-cacheable region in the 6x86MX.
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Summary of 6x86MX and 6x86 Differences
1.3 Summary of 6x86MX and 6x86 Differences
The differences between the 6x86MX CPU and the 6x86 CPU are listed in the table below.
6X86MX L1 Cache Size CPUID (Bit 7 of CCR4) Family Code EDX Time Stamp Counter DIR0 (Register Index = FEh) DTE_EN (Bit 4 of CCR4) SLOP (Bit 1 of CCR5 LBR1 (Bit 4 of CCR5) WWO (Bit 1 of RCRx) 64 KBytes Reset Value = 1 06h Reset Value = 06 + DIR0 Yes 5xh Reserved Reserved Reserved 16 KBytes
6X86 Reset Value = 0 05h Reset Value = 05 + DIR0 No 3xh If = 1, the DTE cache is enabled. If =1, the LOOP instruction is slowed down. If =1, LBA# pin is asserted for all accesses to the 640KBytes 1MByte address region. If = 1, weak write ordering is enabled for the corresponding region.
NOTES Section 2 Section 3 Section 4 Figure 3-1 Section 3 BIOS Writer's Guide Revision 1.2 Section 3 Section 4 Section 4 Section 4
Reserved
Section 4
Summary of 6x86MX and 6x86 Differences
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Cyrix 6x86MX Application Note 103 - BIOS WRITER'S GUIDE
Summary of 6x86MX and 6x86 Differences
2. Cache Unit
The cache size of the 6x86MX has been increased to 64 KByte. This is four times larger than the 16 KByte cache of the 6x86. The cache is configured the same way as the 6x86: 4-way set associative, and 32 Byte lines.
3. Cyrix 6x86MX CPU Detection
Two methods for detecting the Cyrix 6x86MX CPU are described in Sections 3.1 and 3.2. Cyrix does not recommend other detection algorithms using the value of EDX following reset, and other signature methods of determining if the CPU is an 8086, 80286, 80386, or 80486.
Cyrix 6x86MX Application Note 103 - BIOS WRITER'S GUIDE
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Detecting the Cyrix 6x86MX - Method 1
3.1 Detecting the Cyrix 6x86MX - Method 1
This method for detecting the presence of an 6x86MX microprocessor during BIOS POST is a two step process. First, a Cyrix brand CPU must be detected. Second, the CPU's Device Identification Registers (DIRs) provide the CPU model and stepping information.
3.1.1
Cyrix CPU Detection
Detection of a Cyrix brand CPU is implemented by checking the state of the undefined flags following execution of the divide instruction which divides 5 by 2 (5÷2). The undefined flags in a Cyrix microprocessor remain unchanged following the divide. Alternate CPUs modify some of the undefined flags. Using operands other than 5 and 2 may prevent the algorithm from working correctly. Appendix A contains sample code for detecting a Cyrix CPU using this method.
3.1.2
Detecting CPU Type and Stepping
Once a Cyrix brand CPU is detected, the model and stepping of the CPU can be determined. All Cyrix CPUs contain Device Identification Registers (DIRs) that exist as part of the configuration registers. The DIRs for all Cyrix CPUs exist at configuration register indexes 0FEh and 0FFh. The table below specifies the contents of the 6x86MX DIRs. DIR0 bits [7:4] = 5h indicate an 6x86MX CPU is present, DIR0 bits [3:0] indicate the core-to-bus clock ratio, and DIR1 contains stepping information. Clock ratio information is provided to assist calculations in determining bus frequency once the CPU's core frequency has been calculated. Proper bus speed settings are critical to overall system performance.
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Cyrix 6x86MX Application Note 103 - BIOS WRITER'S GUIDE
Detecting the Cyrix 6x86MX - Method 1
DEVICE 6x86MX
CORE/BUS CLOCK RATIO 2/1 (default) 2.5/1 3/1 3.5/1
DIR0 (DEVICE ID) 51h or 59h 52h or 5Ah 53h or 5Bh 54h or 5Ch
DIR1 (REV ID) TBD
Cyrix Device Identification Registers
Cyrix 6x86MX Application Note 103 - BIOS WRITER'S GUIDE
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Detecting the Cyrix 6x86MX - Method 2
3.2 Detecting the Cyrix 6x86MX - Method 2
Unlike the 6x86, the CPUID instruction is enabled following reset. It can be disabled by clearing the CPUID bit in configuration register CCR4. It is recommended that all BIOS vendors include a CPUID enable/disable field in the CMOS setup to allow the end-user to disable the CPUID instruction. The CPUID instruction, opcode 0FA2h, provides information indicating Cyrix as the vendor and the family, model, stepping, and CPU features. The EAX register provides the input value for the CPUID instruction. The EAX register is loaded with a value to indicate what information should be returned by the instruction. Following execution of the CPUID instruction with an input value of "0" in EAX, the EAX, EBX, ECX and EDX registers contain the information shown in Figure 31. EAX contains the highest input value understood by the CPUID instruction, which for the 6x86MX is "1". EBX, ECX and EDX contain the vendor identification string "CyrixInstead". Following execution of the CPUID instruction with an input value of "1" loaded in EAX, EAX[15:0] will contain the value of 06xxh. EDX [31-0] will contain the value 0080A135h.
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Cyrix 6x86MX Application Note 103 - BIOS WRITER'S GUIDE
Detecting the Cyrix 6x86MX - Method 2
switch (EAX) { case (0): EAX := EBX := EDX := ECX := break
1 69 73 64
72 6e 61
79 49 65
43/* 'i' 'r' 'y' 'C' */ 78/* 's' 'n' 'I' 'x' */ 74/* 'd' 'a' 'e' 't' */
case (1): EAX[7:0] := EAX[15:8] := EDX[0] := EDX[1] := EDX[2] := EDX[3] := EDX[4] := EDX[5] := EDX[6] := EDX[7] := EDX[8] := EDX[9] := EDX[11-10]:= EDX[12] := EDX[13] := EDX[14] := EDX[15] := EDX[22-16]:= EDX[23] := EDX[31-24]:= break
00h 06h 1 /* 1=FPU Built In */ 0 /* 0=No V86 enhancements */ 1 /* 1=I/O breakpoints */ 0 /* 0=No page size extensions */ 1 /* 1=Time Stamp Counter */ 1 /* 1=RDMSR and WRMSR */ 0 /* 0=No physical address extensions */ 0 /* 0=No machine check exception */ 1 /* 1=CMPXCHG8B instruction */ 0 /* 0=No APIC*/ 0 /* Undefined */ 0 /* 0=No memory type range registers */ 1 /* 1=PTE global bit */ 0 /* 0=No machine check architecture */ 1 /* 1=CMOV, FCMOV, FCOMI instructions */ 0 /* Undefined */ 1 /* 1=MMX instructions */ 00h /* "documentation error was: 0080h" */
default: EAX, EBX, ECX, EDX : Undefined }
Information Returned by CPUID Instruction
Cyrix 6x86MX Application Note 103 - BIOS WRITER'S GUIDE
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EDX Value Following Reset
3.3 EDX Value Following Reset
Some CPU detection algorithms may use the value of the CPU's EDX register following reset. The 6x86MX's EDX register contains the data shown below following a reset initiated using the RESET pin: EDX[31:16] = undefined EDX[15:8] = 06h EDX[7:0] = DIR0 Refer to the table on the previous page for DIR0 values. The value in EDX does not identify the vendor of the CPU. Therefore, EDX alone cannot be used to determine if a Cyrix CPU is present. However, BIOS should preserve the contents of EDX so that applications can use the EDX value when performing a user-defined shutdown, e.g. a reset performed with data 0Ah in the Shutdown Status byte (Index 0Fh) of the CMOS RAM map.
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Cyrix 6x86MX Application Note 103 - BIOS WRITER'S GUIDE
Determining 6x86MX Operating Frequency
3.4 Determining 6x86MX Operating Frequency
Determining the operating frequency of the CPU is normally required for correct initialization of the system logic. Typically, a software timing loop with known instruction clock counts is timed using legacy hardware (the 8254 timer/counter circuits) within the PC. Once the operating frequency of the 6x86MX's core is known, DIR0 bits (2:0) can be examined to calculate the bus operating frequency.
3.4.1
Instruction Count Method
Careful selection of instructions and operands must be used to replicate the exact clock counts detailed in the Instruction Set Summary found in the 6x86MX Data Book. An example code sequence for determining the 6x86MX's operating frequency is detailed in Appendix B and Appendix C. This code sequence is identical to the recommended sequence for the 6x86. The core loop uses a series of five IDIV instructions within a LOOP instruction. IDIV was chosen because it is an exclusive instruction meaning that it executes in the 6x86MX x-pipeline with no other instruction in the y-pipeline. This allows for more predictable execution times as compared to using non-exclusive instructions. The 6x86MX instruction clock count for IDIV varies from 17 to 45 clocks for a doubleword divide depending on the value of the operands. The code example in the appendices uses "0" divided by "1" which takes only 17 clocks to complete. The LOOP instruction clock count is 1. Therefore, the overall clock count for the inner loop in this example is 86 clocks.
3.4.2
Time Stamp Counter Method
On the 6x86MX, the Time Stamp Counter (TSC) can be used as an alternative method for obtaining an exact core clock count during the software timing loop. The Time Stamp Counter is a 64-bit counter that counts internal CPU clock cycles since the last reset. The value can be read any time via the RDTSC instruction, opcode OF31h. The RDTSC instruction loads the contents of the TSC into EDX:EAX. The use of the RDTSC instruction is restricted by the Time Stamp Disable, (TSD) flag in CR4. When the TSD flag is 0, the RDTSC instruction can be executed at any privilege level. When the TSD flag is 1, the RDTSC instruction can only be executed at privilege level 0.
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Device Name
The exact core count during the software timing loop can be determined by computing the difference of the Time Stamp Counter at start of the loop and the end of the loop.
3.5 Device Name
The correspondence between core frequency, bus frequency and performance rating is shown in the table below. The device name in table below should be used by the BIOS for display during boot-up and in BIOS setup screens or utilities.
DEVICE NAME AND PART NUMBER 6x86MX - PR166GP 6x86MX - PR200GP 6x86MX - PR233GP 6x86MX - PR233GP 6x86MX - PR266GP 6x86MX - PR266GP CLOCK MULTIPLIER 2.5 2.5 2.5 3.0 3.0 3.5 FREQUENCY (MHZ) BUS 60 66 75 66 75 66 INTERNAL 150 166 188 200 225 233
Cyrix 6x86MXTM Part Numbers
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Cyrix 6x86MX Application Note 103 - BIOS WRITER'S GUIDE
Accessing a Configuration Register
4. 6x86MX Configuration Register Index Assignments
On-chip configuration registers are used to control the on-chip cache, system management mode and other 6x86MX unique features.
4.1 Accessing a Configuration Register
Access to the configuration registers is achieved by writing the index of the register to I/O port 22h. I/O port 23h is then used for data transfer. Each I/O port 23h data transfer must be preceded by an I/O port 22h register index selection, otherwise the second and later I/O port 23h operations are directed off-chip and produce external I/O cycles. Reads of I/O port 22h are always directed off-chip. Appendix D contains example code for accessing the 6x86MX configuration registers.
4.2 6x86MX Configuration Register Index Assignments
The table on the following page lists the 6x86MX configuration register index assignments. After reset, configuration registers with indexes C0-CFh and FC-FFh are accessible. In order to prevent potential conflicts with other devices which may use ports 22 and 23h to access their registers, the remaining registers (indexes 00BFh, D0-FBh) are accessible only if the MAPEN(3-0) bits in CCR3 are set to 1h. With MAPEN(3-0) set to 1h, any access to an index in the 00-FFh range does not create external I/O bus cycles. Registers with indexes C0-CFh, FC-FFh are accessible regardless of the state of the MAPEN bits. If the register index number is outside the C0-CFh or FE-FFh ranges, and MAPEN is set to 0h, external I/O bus cycles occur. The table on the next page lists the MAPEN values required to access each 6x86MX configuration register. The configuration registers are described in more detail in the following sections.
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6x86MX Configuration Register Index Assignments
REGISTER INDEX 00h-BFh C0h C1h C2h C3h C4h-C6h C7h-C9h CAh-CCh CDh-CFh D0h-D2h D3h-D5h D6h-D8h D9h-DBh DCh DDh DEh DFh E0h E1h E2h E3h E4h-E7h E8h E9h EAh EBh-FAh FBh FCh FDh FEh FFh Reserved
REGISTER NAME --
ACRONYM -- 8 8 8 8 24 24 24 24 24 24 24 24 8 8 8 8 8 8 8 8 -- 8 8 8 -- 8 8 8 8 8
WIDTH (BITS) --
MAPEN(3-0)
Configuration Control 0 Configuration Control 1 Configuration Control 2 Configuration Control 3 Address Region 0 Address Region 1 Address Region 2 Address Region 3 Address Region 4 Address Region 5 Address Region 6 Address Region 7 Region Configuration 0 Region Configuration 1 Region Configuration 2 Region Configuration 3 Region Configuration 4 Region Configuration 5 Region Configuration 6 Region Configuration 7 Reserved Configuration Control 4 Configuration Control 5 Configuration Control 6 Reserved Device Identification 2 Device Identification 3 Device Identification 4 Device Identification 0 Device Identification 1
CCR0 CCR1 CCR2 CCR3 ARR0 ARR1 ARR2 ARR3 ARR4 ARR5 ARR6 ARR7 RCR0 RCR1 RCR2 RCR3 RCR4 RCR5 RCR6 RCR7 -- CCR4 CCR5 CCR6 -- DIR2 DIR3 DIR4 DIR0 DIR1
Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care 1h 1h 1h 1h 1h 1h 1h 1h 1h 1h 1h 1h -- 1h 1h 1h -- 1h 1h 1h Don't care Don't care
Configuration Register Index Assignments
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Cyrix 6x86MX Application Note 103 - BIOS WRITER'S GUIDE
Configuration Control Registers (CCR0-6)
The 6x86MX configuration registers can be grouped into four areas:
· · · ·
Configuration Control Registers (CCRs) Address Region Registers (ARRs) Region Control Registers (RCRs) Device Identification Registers (DIRs)
CCR bits independently control 6x86MX features. ARRs and RCRs define regions of memory with specific attributes. DIRs are used for CPU detection as discussed earlier in Chapter 3. All bits in the configuration registers are initialized to zero following reset unless specified otherwise. The appropriate configuration register bit settings vary depending on system design. Optimal settings recommended for a typical PC environment are discussed in Chapter 5.
4.3 Configuration Control Registers (CCR0-6)
There are seven CCRs in the 6x86MX which control the cache, power management and other unique features. The following paragraphs describe the CCRs and associated bit definitions in detail.
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Configuration Control Registers (CCR0-6)
4.3.1
Configuration Control Register 0 (CCR0)
BIT 7 Reserved
BIT 6 Reserved
BIT 5 Reserved
BIT 4 Reserved
BIT 3 Reserved
BIT 2 Reserved
BIT 1 NC1
BIT 0 Reserved
Configuration Control Register 0 (CCR0)
BIT NAME NC1
BIT NO. 1
DESCRIPTION If = 1, designates 640KBytes -1MByte address region as non-cacheable. If = 0, designates 640KBytes -1MByte address region as cacheable.
CCR0 Bit Definitions
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Cyrix 6x86MX Application Note 103 - BIOS WRITER'S GUIDE
Configuration Control Registers (CCR0-6)
4.3.2
Configuration Control Register 1 (CCR1)
BIT 7 SM3
BIT 6 Reserved
BIT 5 Reserved
BIT 4 NO_LOCK
BIT 3 Reserved
BIT 2 SMAC
BIT 1 USE_SMI
BIT 0 Reserved
Configuration Control Register 1 (CCR1)
BIT NAME SM3 NO_LOCK
BIT NO. 7 4
DESCRIPTION If = 1, designates Address Region Register 3 as SMM address space. If = 1, all bus cycles are issued with the LOCK# pin negated except page table accesses and interrupt acknowledge cycles. Interrupt acknowledge cycles are executed as locked cycles even though LOCK# is negated. With NO_LOCK set, previously non-cacheable locked cycles are executed as unlocked cycles and therefore, may be cached. This results in higher CPU performance. See the section on Region Configuration Registers (RCR) for more information on eliminating locked CPU bus cycles only in specific address regions. If = 1, any access to addresses within the SMM address space access system management memory instead of main memory. SMI# input is ignored while SMAC is set. Setting SMAC=1 allows access to SMM memory without entering SMM. This is useful for initializing or testing SMM memory. If = 1, SMI# and SMIACT# pins are enabled. If = 0, SMI# pin is ignored and SMIACT# pin is driven inactive.
SMAC
2
USE_SMI
1
CCR1 Bit Definitions
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Configuration Control Registers (CCR0-6)
4.3.3
Configuration Control Register 2 (CCR2)
BIT 7 USE_SUSP
BIT 6 Reserved
BIT 5 Reserved
BIT 4 WPR1
BIT 3 SUSP_HLT
BIT 2 LOCK_NW
BIT 1 SADS
BIT 0 Reserved
Configuration Control Register 2 (CCR2)
BIT NAME USE_SUSP
BIT NO. 7
DESCRIPTION If = 1, SUSP# and SUSPA# pins are enabled. If = 0, SUSP# pin is ignored and SUSPA# pin floats. These pins should only be enabled if the external system logic (chipset) supports them.
WPR1 SUSP_HLT
4 3
If = 1, designates that any cacheable accesses in the 640 KBytes-1MByte address region are writeprotected. With WPR1=1, any attempted write to this range will not update the internal cache. If = 1, execution of the HLT instruction causes the CPU to enter low power suspend mode. This bit should be used with caution since the CPU must recognize and service an INTR, NMI or SMI to exit the "HLT initiated" suspend mode. If = 1, the NW bit in CR0 becomes read only and the CPU ignores any writes to this bit. If = 1, the CPU inserts an idle cycle following sampling of BRDY# and prior to asserting ADS#.
LOCK_NW SADS
2 1
CCR2 Bit Definitions
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Cyrix 6x86MX Application Note 103 - BIOS WRITER'S GUIDE
Configuration Control Registers (CCR0-6)
4.3.4
Configuration Control Register 3 (CCR3)
BIT 7
BIT 6 MAPEN
BIT 5
BIT 4
BIT 3 Reserved
BIT 2 LINBRST
BIT 1 NMI_EN
BIT 0 SMI_LOCK
Configuration Control Register 3 (CCR3)
BIT NAME MAPEN LINBRST
BIT NO. 7-4 2
DESCRIPTION If set to 0001 binary (1h), all configuration registers are accessible. If set to 0000, only configuration registers with indices C0-CFh, FEh and FFh are accessible. If = 1, the 6x86MX will use a linear address sequence when performing burst cycles. If = 0, the 6x86MX will use a "1+4" address sequence when performing burst cycles. The "1+4" address sequence is compatible with the Pentium's burst address sequence.
NMI_EN SMI_LOCK
1 0
If = 1, NMI interrupt is recognized while in SMM. This bit should only be set while in SMM, after the appropriate NMI interrupt service routine has been setup. If = 1, the CPU prevents modification of the following SMM configuration bits, except when operating in an SMM service routine: CCR1 USE_SMI, SMAC, SM3 CCR3 NMI_EN ARR3 Starting address and block size. Once set, the SMI_LOCK bit can only be cleared by asserting the RESET pin.
CCR3 Bit Definitions
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Configuration Control Registers (CCR0-6)
4.3.5
Configuration Control Register 4 (CCR4)
The 6x86 DTE cache has been eliminated on the 6x86MX. Therefore, bit 4 of CCR4 is a reserved bit.
BIT 7 CPUID
BIT 6 Reserved
BIT 5 Reserved
BIT 4 Reserved
BIT 3 Reserved
BIT 2
BIT 1 IORT
BIT 0
Configuration Control Register 4 (CCR4)
BIT NAME CPUID
BIT NO. 7
DESCRIPTION If = 1, bit 21 of the EFLAG register is write/readable and the CPUID instruction will execute normally. If = 0, bit 21 of the EFLAG register is not write/readable and the CPUID instruction is an invalid opcode.
IORT
2-0
Specifies the minimum number of bus clocks between I/O accesses (I/O recovery time). The delay time is the minimum time from the end of one I/O cycle to the beginning of the next (i.e. BRDY# to ADS# time). 0h = 1 clock 1h = 2 clocks 2h = 4 clocks 3h = 8 clocks 4h = 16 clocks 5h = 32 clocks (default value after RESET) 6h = 64 clocks 7h = no delay
CCR4 Bit Definitions
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Cyrix 6x86MX Application Note 103 - BIOS WRITER'S GUIDE
Configuration Control Registers (CCR0-6)
4.3.6
Configuration Control Register 5 (CCR5)
The 6x86 Slow Loop Instruction and Local Bus Access features have been eliminated in the 6x86MX. Therefore, bits 4 and 1 of CCR5 are reserved bits on the 6x86MX.
BIT 7 Reserved
BIT 6 Reserved
BIT 5 ARREN
BIT 4 Reserved
BIT 3 Reserved
BIT 2 Reserved
BIT 1 Reserved
BIT 0 WT_ALLOC
Configuration Control Register 5 (CCR5)
BIT NAME ARREN WT_ALLOC
BIT NO. 5 0
DESCRIPTION If = 1, enables all Address Region Registers (ARRs). If clear, disables the ARR registers. If SM3 is set, ARR3 is enabled regardless of the ARREN setting. If = 1, new cache lines are allocated for both read misses and write misses. If = 0, new cache lines are only allocated on read misses.
CCR5 Bit Definitions
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Configuration Control Registers (CCR0-6)
4.3.7
Configuration Control Register 6 (CCR6)
Configuration Control Register 6 has been added to the 6x86MX.
BIT 7 Reserved
BIT 6 N
BIT 5 Reserve
BIT 4 Reserved
BIT 3 Reserved
BIT 2 Reserved
BIT 1 WP_ARR3
BIT 0 SMM_MODE
Configuration Control Register 6 (CCR6)
BIT NAME N
BIT NO. 6
DESCRIPTION Nested SMI Enable bit: If operating in Cyrix enhanced SMM mode and: If = 1: Enables nesting of SMI's If = 0: Disable nesting of SMI's. This bit is automatically CLEARED upon entry to every SMM routine and is SET upon every SMM routine and is SET upon every RSM. Therefore enabling/disabling of nested SMI can only be done while operating in SMM mode.
WP_ARR3
1
If = 1: Memory region defined by ARR3 is write protected when operating outside of SMM mode. If = 0: Disable write protection for memory region defined by ARR3. Reset State = 0.
SMM_MODE
0
If = 1: Enables Cyrix Enhanced SMM mode. If = 0: Disables Cyrix Enhanced SMM mode.
CCR6 Bit Definitions
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Address Region Registers (ARR0-7)
4.4 Address Region Registers (ARR0-7)
The Address Region Registers (ARRs) are used to define up to eight memory address regions. Each ARR has three 8-bit registers associated with it which define the region starting address and block size. The Table "ARRx Index Assignments" below shows the general format for each ARR and lists the index assignments for the ARR's starting address and block size. The region starting address is defined by the upper 12 bits of the physical address. The region size is defined by the BSIZE(3-0) bits as shown in the Table "BSIZE (30) Bit Definitions" on the next page. The BIOS and/or its utilities should allow definition of all ARRs. There is one restriction when defining the address regions using the ARRs. The region starting address must be on a block size boundary. For example, a 128KByte block is allowed to have a starting address of 0KBytes, 128KBytes, 256KBytes, and so on.
ADDRESS REGION REGISTER ARR0 ARR1 ARR2 ARR3 ARR4 ARR5 ARR6 ARR7
STARTING ADDRESS A31-A24 BITS (7-0) C4h C7h CAh CDh D0h D3h D6h D9h A23-A16 BITS (7-0) C5h C8h CBh CEh D1h D4h D7h DAh A15-A12 BITS (7-4) C6h C9h CCh CFh D2h D5h D8h DBh
REGION BLOCK SIZE BSIZE(3-0) BITS (3-0)
ARRx Index Assignments
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Address Region Registers (ARR0-7)
BSIZE(3-0) 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh
ARR(0-6) REGION SIZE Disabled 4 KBytes 8 KBytes 16 KBytes 32 KBytes 64 KBytes 128 KBytes 256 KBytes 512 KBytes 1 MByte 2 MBytes 4 MBytes 8 MBytes 16 MBytes 32 MBytes 4 GBytes
ARR7 REGION SIZE Disabled 256 KBytes 512 KBytes 1 MByte 2 MBytes 4 MBytes 8 MBytes 16 MBytes 32 MBytes 64 MBytes 128 MBytes 256 MBytes 512 MBytes 1 GBytes 2 GBytes 4 GBytes
BSIZE (3-0) Bit Definitions
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Region Control Registers (RCR0-7)
4.5
Region Control Registers (RCR0-7)
The RCRs are used to define attributes, or characteristics, for each of the regions defined by the ARRs. Each ARR has a corresponding RCR with the general format shown below. New to the 6x86MX is the Invert Region feature. This feature is controlled by the INV_RGN bit of the Region Control Registers. If the INV_RGN bit is set, the controls specified in the RCR (RCD, WT, WG, WL) will be applied to all memory addresses outside the region specified in the corresponding ARR. If the INV_RGN bit is cleared, the 6x86MX functions identically to the 6x86 (the controls specified in the RCR will be applied to all memory addresses inside the region specified by the corresponding ARR). The INV_RGN bit is defined for RCR(0-6) only. 6x86 Weak Write Ordering and Local Bus Access features have been eliminated on the 6x86MX. Therefore, bit 5 and bit 1 are reserved bits for the 6x86MX.
BIT 7 Reserved
BIT 6 INV_RGN
BIT 5 Reserved
BIT 4 WT
BIT 3 WG
BIT 2 WL
BIT 1 Reserved
BIT 0 RCD/RCE
RCR Bit Definitions
Note: RCD is defined for RCR0-RCR6. RCE is defined for RCR7 only.
BIT NAME RCD RCE WL WG WT INV_RGN
BIT NO. 0 0 2 3 4 6
DESCRIPTION Applicable to RCR(0-6) only. If set, the address region specified by the corresponding ARR is non-cacheable. Applicable to RCR7 only. If set, the address region specified by ARR7 is cacheable and implies that address space outside of the region specified by ARR7 is non-cacheable. If set, weak locking is enabled for the corresponding region. If set, write gathering is enabled for the corresponding region. If set, write through caching is enabled for the corresponding region. Applicable to RCR(0-6) only. If set, apply controls specified in RCR to all memory addresses outside the region specified in the corresponding ARR.
RCR Bit Definitions
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Region Control Registers (RCR0-7)
4.5.1
Detailed Description of RCR Attributes
Region Cache Disable (RCD)
Setting RCD=1 defines the corresponding address region as non-cacheable. RCD prevents caching of any access within the specified region. Additionally, RCD implies that high performance features are disabled for accesses within the specified address region. Bus cycles issued to memory addresses within the specified region are single cycles with the CACHE# pin negated. If KEN# is asserted for a memory access within a region defined non-cacheable by RCD, the access is not cached.
Region Cache Enable (RCE)
Setting RCE=1 defines the corresponding address region as cacheable. RCE is applicable to ARR7 only. RCE in combination with ARR7, is intended to define the Main Memory Region. All memory outside ARR7 is non-cacheable when RCE is set. This is intended to define all unused memory space as non-cacheable. If KEN# is negated for an access within a region defined cacheable by RCE, the access is not cached.
Weak Locking (WL)
Setting WL=1 enables weak locking for the corresponding address region. With WL enabled, all bus cycles are issued with the LOCK# pin negated except for page table accesses and interrupt acknowledge cycles. WL negates bus locking so that previously non-cacheable cycles can be cached. Typically, XCHG instructions, instructions preceded by the LOCK prefix, and descriptor table accesses are locked cycles. Setting WL allows the data for these cycles to be cached. Weak Locking (WL) implements the same function as NO_LOCK except that NO_LOCK is a global enable. The NO_LOCK bit of CCR1 enables weak locking for the entire address space, whereas the WL bit enables weak locking only for specific address regions.
Write Gathering (WG)
Setting WG=1 enables write gathering for the corresponding address region. With WG enabled, multiple byte, word or dword writes to sequential addresses that would normally occur as individual write cycles are combined and issued as a sin-
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Region Control Registers (RCR0-7)
gle write cycle. WG improves bus utilization and should be used for memory regions that are not sensitive to the "gathering." WG can be enabled for both cacheable and non-cacheable regions.
Write Through (WT)
Setting WT=1 defines the corresponding address region as write-through instead of write-back. Any system ROM that is allowed to be cached by the processor should be defined as write-through.
4.5.2
Attributes for Accesses Outside Defined Regions
If an address is accessed that is not in a region defined by the ARRs and ARR7 is defined with RCE=1, the following conditions apply:
· · · · 4.5.3
The memory access is not cached regardless of the state of KEN#. Writes are not gathered. Strong locking occurs. Strong write ordering occurs.
Attributes for Accesses in Overlapped Regions
If two defined address regions overlap (including NC1 and LBR1) and conflicting attributes are specified, the following attributes take precedence:
· · · · ·
Write-back is disabled. Writes are not gathered. Strong locking occurs. Strong write ordering occurs. The overlapping regions are non-cacheable.
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Region Control Registers (RCR0-7)
Since the CCR0 bit NC1 affects cacheability, a potential exists for conflict with the ARR7 main memory region which also affects cacheability. This overlap in address regions causes a conflict in cacheability. In this case, NC1 takes precedence over the ARR7/RCE setting because non-cacheability always takes precedence. For example, for the following settings:
· · ·
NC1=1 ARR7 = 0-16 MBytes RCR7 bit RCE = 1
The 6x86MX caches accesses as shown in the table below.
ADDRESS REGION 0 to 640 KBytes 640 KBytes- 1 MByte 1 MByte - 16 MBytes 16 MBytes - 4 GBytes
CACHEABLE Yes No Yes No
COMMENTS ARR7/RCE setting. NC1 takes precedence over ARR7/RCE setting. ARR7/RCE setting. Default setting.
Cacheability for Example 1
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Region Control Registers (RCR0-7)
4.5.4
Attributes for Accesses with Conflicting Signal Pin Inputs
The characteristics of the regions defined by the ARRs and the RCRs may also conflict with indications by hardware signals (i.e., KEN#, WB/WT#). The following paragraphs describe how conflicts between register settings and hardware indicators are resolved.
Non-cacheable Regions and KEN#
Regions which have been defined as non-cacheable (RCD=1) by the ARRs and RCRs may conflict with the assertion of the KEN# input. If KEN# is asserted for an access to a region defined as non-cacheable, the access is not cached. Regions defined as non-cacheable by the ARRs and RCRs take precedence over KEN#. The NC1 bit also takes precedence over the KEN# pin. If NC1 is set, any access to the 640 KByte-1 MByte address region with KEN# asserted is not cached.
Write-Through Regions and WB/WT#
Regions which have been defined as write-through (WT=1) may conflict with the state of the WB/WT# input to the 6x86MX. Regions defined as write-through by the ARRs and RCRs remain write-through even if WB/WT# is asserted during accesses to these regions. The WT bit in the RCRs takes precedence over the state of the WB/WT# pin in cases of conflict.
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PC Memory Model
5. Recommended 6x86MX Configuration Register Settings 5.1 PC Memory Model
The table below defines the allowable attributes for a typical PC memory model. Actual recommended configuration register settings for a typical PC system are listed in Appendix F.
ADDRESS SPACE DOS Area Video Buffer Video ROM Expansion Card/ROM Area System ROM Extended Memory Unused/PCI MMIO
ADDRESS RANGE 0-9 FFFFh A 0000-B FFFFh C 0000-C 7FFFh C 8000h-D FFFFh
CACHEABLE Yes No Yes No
WEAK LOCKS No No No No
WRITE GATHERED Yes Yes No No
WRITETHROUGH No No Yes No
NOTES
Note 1 Note 2
E 0000h-F FFFFh 10 0000hTop of Main Memory Top of Main MemoryFFFF FFFFh
Yes Yes No
No No No
No Yes No
Yes No No
Note 2
Note 3
PC Memory Model
Notes 1: Video Buffer Area A non-cacheable region must be used to enforce strong cycle ordering in this area and to prevent caching of Video RAM. The Video RAM area is sensitive to bus cycle ordering. The VGA controller can perform logical operations which depend on strong cycle ordering (found in Windows 3.1 code). To guarantee that the 6x86MX performs strong cycle ordering, a non-cacheable area must be established to cover the Video RAM area. Video performance is greatly enhanced by gathering writes to Video RAM. For example, video performance benchmarks have been found to use REP STOSW instructions that would normally execute as a series of sequential 16-bit write cycles. With WG enabled, groups of four 16-bit write cycles are reduced to a single 64-bit write cycle.
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PC Memory Model
Note 2: Video ROM and System ROM Caching of the Video and System ROM areas is permitted, but is normally non-cacheable because NC1 is set. If these areas are cached, they must be cached as write-through regions. 6x86MX system benchmarking in a Windows environment has shown no benefit to caching these ROM areas. Therefore, it is recommended that these areas be set as non-cacheable using the NC1 bit in CCR0. Note 3: Top of Main Memory-FFFF FFFFh (Unused/PCI Memory Space) Unused/PCI Memory Space immediately above physical main memory must be defined as noncacheable to ensure proper operation of memory sizing software routines and to guarantee strong cycle ordering. Memory discovery routines must occur with cache disabled to prevent read sourcing from the write buffers. Also, PCI memory mapped I/O cards that may exist in this address region may contain control registers or FIFOs that depend on strong cycle ordering. The appropriate non-cacheable region must be established using ARR7. For example, if 32 MBytes (000 0000h-1FF FFFFh) are installed in the system, a non-cacheable region must begin at the 32 MByte boundary (200 0000h) and extend through the top of the address space (FFFF FFFFh). This is accomplished by using ARR7 (Base = 0000 0000h, BSize = 32 MBytes) in combination with RCE=1.
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PC Memory Model
5.2
General Recommendations
5.2.1
Main Memory
Memory discovery routines should always be executed with the L1 cache disabled. By default, L1 caching is globally disabled following reset because the CD bit in Control Register 0 (CR0) is set. Always ensure the L1 cache is disabled by setting the CD bit in CR0 or by programming an ARR to "4 GByte cache disabled" before executing the memory discovery routine. Once BIOS completes memory discovery, ARR7 should be programmed with a base address of 000 0000h and with a "Size" equal to the amount of main memory that was detected. The intent of ARR7 is to define a cacheable region for main memory and simultaneously define unused/PCI space as non-cacheable. More restrictive regions are intended to overlay the 640k to 1MByte area. Failure to program ARR7 with the correct amount of main memory can result in:
· · ·
Incorrect memory sizing by the operating system eventually resulting in failure, PCI devices not working correctly or causing the system to hang, Low performance if ARR7 is programmed with a smaller size than the actual amount of memory.
If the granularity selection in ARR7 does not accommodate the exact size of main memory, unused ARRs can be used to fill-in as non-cacheable regions. All unused/ PCI memory space must always be set as non-cacheable.
5.2.2
I/O Recovery Time (IORT)
Back-to-back I/O writes followed by I/O reads may occur too quickly for a peripheral to respond correctly. Historically, programmers have inserted several "JMP $+2" instructions in the hope that code fetches on the bus would create sufficient recovery time. The 6x86MX's Branch Target Buffer (BTB) typically eliminates these external code fetches, thus the previous method of guaranteeing I/O recovery no longer applies. For the 6x86MX, one approach to dealing with this issue is to insert I/O write cycles to a dummy port. I/O write cycles in the form of "out imm,reg" are easily implemented as shown below:
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PC Memory Model
OLD IORT out 21h,al jmp $+2 jmp $+2 jmp $+2 in al,21h
NEW IORT out 21h,al out 80h,al out 80h,al out 80h,al in al,21h
The 6x86MX incorporates an alternative method for implementing I/O recovery time using user selectable delay settings. See the section on 6x86MX IORT settings below.
5.2.3
BIOS Creation Utilities
BIOS creation utilities or setup screens must have the capability to easily define and modify the contents of the 6x86MX configuration registers. This allows OEMs and integrators to easily configure these register settings with the values appropriate for their system design.
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Recommended Bit Settings
5.3 Recommended Bit Settings
5.3.1 NC1
The NC1 bit in CCR0 controls the predefined non-cacheable region from 640K to 1 MByte. The 640K to 1MByte region should be non-cacheable to prevent L1 caching of expansion cards using memory mapped I/O (MMIO). Setting NC1 also implies that the video BIOS and system BIOS are non-cacheable. Experiments with both the 6x86MX and Pentium CPUs have shown that performance is largely unchanged whether the video BIOS and system BIOS was cached or not. This assumes that a modern operating system was used and that the measurements are taken with a recent benchmark applications, such as WinStone95. Recommended setting: NC1 = 1
5.3.2
NO_LOCK
NO_LOCK enables weak locking for the entire address space. NO_LOCK may cause failures for software that requires locked cycles in order to operate correctly. Recommended setting: NO_LOCK = 0
5.3.3
LOCK_NW
Once set, LOCK_NW prohibits software from changing the NW bit in CR0. Since the definition of the NW bit is the same for both the 6x86MX and the Pentium, it is not necessary to set this bit. Recommended setting: LOCK_NW = 0
5.3.4
WPR1
WPR1 forces cacheable accesses in the 640k to 1MByte address region to be writeprotected. If NC1 is set (recommended setting), all caching is disabled from 640k to 1MByte and WPR1 is not required. However, if ROM areas within the 640k1MByte address region are cached, WPR1 should be set to protect against errant self-modifying code. Recommended setting: WPR1 = 0 unless ROM areas are cached
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Recommended Bit Settings
5.3.5
LINBRST
Linear Burst (LINBRST) allows for an alternate address sequence for burst cycles. The system logic, L2 cache and motherboard design must also support this feature in order for the 6x86MX to function properly with this bit enabled. Linear Burst provides higher performance than the default "1+4" burst sequence, but should only be enabled if the system is designed to support it. If the system does support linear burst, BIOS should enable this feature in both the system logic and the 6x86MX prior to enabling the L1 cache. Appendix G includes sample code that can be used to detect if the L2 cache supports linear burst mode. Recommended setting: LINBRST = 0 unless linear burst supported by the system
5.3.6
MAPEN
When set to 1h, the MAPEN bits allow access to all 6x86MX configuration registers including indices outside the C0h-CFh and FCh-FFh ranges. MAPEN should be set to 1h only to access specific configuration registers and then should be cleared immediately after the access is complete. Recommended setting: MAPEN(3-0) = 0 except for specific configuration register accesses
5.3.7
IORT
I/O recovery time specifies the minimum number of bus clocks between I/O accesses for the CPU's bus controller. The system logic typically has a built-in method to select the amount of I/O recovery time. It is preferred to configure the system logic with the I/O recovery time setting and set the CPU for a minimum I/O recovery time delay. Recommended setting: IORT(2-0) = 7
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Recommended Bit Settings
5.3.8
CPUID
When set, the CPUID bit enables the CPUID instruction. By default, the CPUID instruction is enabled (CPUID = 1). When enabled, the CPUID opcode is enabled and the CPUID bit in the EFLAGS can be modified. The CPUID instruction can then be called to inspect the type of CPU present. When the CPUID instruction is disabled (CPUID = 0), the CPUID opcode 0FA2 causes an invalid opcode exception. Additionally, the CPUID bit in the EFLAGS register cannot be modified by software. Recommended setting: CPUID = 1
5.3.9
WT_ALLOC
Write Allocate (WT_ALLOC) allows L1 cache write misses to cause a cache line allocation. This feature improves the L1 cache hit rate resulting in higher performance. Especially useful for Windows applications. Recommended setting: WT_ALLOC = 1
5.3.10 ARREN
The ARREN bit enables or disables all eight ARRs. When ARREN is cleared (default), the ARRs can be safely programmed. Most systems will need to use at least one address region register (ARR). Therefore, ARREN should always be set after the ARRs and RCRs have been initialized. Recommended setting: ARREN = 1 after initializing ARR0-ARR7, RCR0-RCR7
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Recommended Bit Settings
5.3.11 ARR7 and RCR7
Address Region 7 (ARR7) defines the Main Memory Region (MMR). This region specifies the amount of cacheable main memory and it's attributes. Once BIOS completes memory discovery, ARR7 should be programmed with a base address of 000 0000h and with a "Size" equal to the amount of main memory installed in the system. Memory accesses outside of this region are defined as non-cacheable to ensure compatibility with PCI devices. Recommended settings: ARR7 Base Addr= 0000 0000h ARR7 Block Size= amount of main memory RCR7 RCE =1 RCR7 WL =0 RCR7 WG =1 RCR7 WT =0 If the granularity selection in ARR7 does not accommodate the exact size of main memory, unused ARRs can be used to fill-in as non-cacheable regions (RCD = 1) as shown in the table below. All unused/PCI memory space must always be set as non-cacheable.
MEM SIZE (MB) 8 16 24 32 40 48 64 72 80 96 128 160 192 256 ARR7 BASE (HEX) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE (MB) 8 16 32 32 64 64 64 128 128 128 128 256 256 256 0E00 0000 0E00 0000 32 32 0C00 0000 0C00 0000 32 32 0A00 0000 32 0600 0000 0600 0000 0600 0000 32 32 32 0500 0000 0500 0000 16 16 0480 0000 8 0300 0000 0300 0000 16 16 0280 0000 8 0180 0000 8 BASE (HEX) ARR6 SIZE (MB) ARR5 BASE (HEX) SIZE (MB) ARR4 BASE (HEX) SIZE (MB)
ARR Settings for Various Main Memory Sizes
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Recommended Bit Settings
5.3.12 SMM Features
The 6x86MX supports SMM mode through the use of the SMI# and SMIACT# pins, and a dedicated memory region for the SMM address space. SMM features must be enabled prior to servicing any SMI interrupts. The following paragraphs describe each of the SMM features and recommended settings.
USE_SMI
Prior to servicing SMI interrupts, SMM-capable systems must enable the SMM pins by setting USE_SMI=1. The SMM hardware pins (SMI# and SMIACT#) are disabled by default.
SMAC
If set, any access to addresses within the SMM address space are directed to SMM memory instead of main memory. Setting SMAC allows access to the SMM memory without servicing an SMI. Additionally, SMAC allows use of the SMINT instruction (software SMI). This bit may be enabled to initialize or test SMM memory but should be cleared for normal operation.
SM3 and ARR3
Address Region Register 3 (ARR3) can be used to define the System Management Address Region (SMAR). Systems that use SMM features must use ARR3 to establish a base and limit for the SMM address space. Only ARR3 can be used to establish the SMM region. Typically, SMAR overlaps normal address space. RCR3 defines the attributes for both the SMM address region and the normal address space. If SMAR overlaps main memory, write gathering should be enabled for ARR3. If SMAR overlaps video memory, ARR3 should be set as non-cacheable and write gathering should be enabled.
NMI_EN
The NMI_EN bit allows NMI interrupts to occur within an SMI service routine. If this feature is enabled, the SMI service routine must guarantee that the IDT is initialized properly to allow the NMI to be serviced. Most systems do not require this feature.
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Recommended Bit Settings
SMI_LOCK
Once the SMM features are initialized in the configuration registers, they can be permanently locked using the SMI_LOCK bit. Locking the SMM related bits and registers prevents applications from tampering with these settings. Even if SMM is not implemented, setting SMI_LOCK in combination with SMAC=0 prevents software SMIs from occurring. Once SMI_LOCK is set, it can only be cleared by a processor RESET. Consequently, setting SMI_LOCK makes system/BIOS/SMM debugging difficult. To alleviate this problem, SMI_LOCK must be implemented as a user selectable "Secure SMI (enable/disable)" feature in CMOS setup. If SMI_LOCK is not user selectable, it is recommended that SMI_LOCK = 0 to allow for system debug. Suggested settings for systems not using SMM: USE_SMI SMAC SM3 ARR3 SMI_LOCK NMI_EN =0 =0 =0 = may be used as normal address region register =0 =0
Suggested settings for systems using SMM: USE_SMI =1 SMAC =0 SM3 =1 ARR3 Base Addr = as required ARR3 Block Size = as required SMI_LOCK =0 NMI_EN =0
5.3.13 Power Management Features SUSP_HALT
Suspend on Halt (SUSP_HLT) permits the CPU to enter a low power suspend mode when a HLT instruction is executed. Although this provides some power management capability, it is not optimal.
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Recommended Bit Settings
Suggested setting: SUSP_HALT =0
USE_SUSP
In addition to the HLT instruction, low power suspend mode may be activated using the SUSP# input pin. In response to the SUSP# input, the SUSPA# output indicates when the 6x86MX has entered low power suspend mode. Systems that support the 6x86MX's low power suspend feature via the hardware pins must set USE_SUSP to enable these pins.
Suggested setting: USE_SUSP = 0 unless hardware suspend pins supported
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Time Stamp Counter
6. Model Specific Registers
The 6x86MX contains four model specific registers (MSR0 - MSR3). These 64-bit registers are listed in the table below.
MACHINE SPECIFIC REGISTER
REGISTER DESCRIPTION Time Stamp Counter (TSC) Counter Event Selection and Control Register Performance Counter #0 Performance Counter #1 MSR ADDRESS 10h 11h 12h 13h REGISTER MSR10 MSR11 MSR12 MSR13
The MSR registers can be read using the RDMSR instruction, opcode 0F32h. During an MSR register read, the contents of the particular MSR register, specified by the ECX register, is loaded into the EDX:EAX registers. The MSR registers can be written using the WRMSR instruction, opcode 0F30h. During a MSR register write the contents of EDX:EAX are loaded into the MSR register specified in the ECX register. The RDMSR and WRMSR instructions are privileged instructions.
6.1 Time Stamp Counter
The Time Stamp Counter (TSC) Register (MSR10) is a 64-bit counter that counts the internal CPU clock cycles since the last reset. The TSC uses a continuous CPU core clock and will continue to count clock cycles even when the 6x86MX is suspend mode or shutdown. The TSC can be accessed using the RDMSR and WRMSR instructions. In addition, the TSC can be read using the RDTSC instruction, opcode 0F31h. The RDTSC instruction loads the contents of the TSC into EDX:EAX. The use of the RDTSC
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Performance Monitoring
instruction is restricted by the Time Stamp Disable, (TSD) flag in CR4. When the TSD flag is 0, the RDTSC instruction can be executed at any privilege level. When the TSD flag is 1, the RDTSC instruction can only be executed at privilege level 0.
6.2 Performance Monitoring
Performance monitoring allows counting of over a hundred different event occurrences and durations. Two 48-bit counters are used: Performance Monitor Counter 0 and Performance Monitor Counter 1. These two performance monitor counters are controlled by the Counter Event Control Register (MSR11). The performance monitor counters use a continuous CPU core clock and will continue to count clock cycles even when the 6x86MX is in suspend mode or shutdown.
6.3 Performance Monitoring Counters 1 and 2
The 48-bit Performance Monitoring Counters (PMC) Registers (MSR12, MSR13) count events as specified by the counter event control register. The PMCs can be accessed by the RDMSR and WRMSR instructions. In addition, the PMCs can be read by the RDPMC instruction, opcode 0F33h. The RDPMC instruction loads the contents of the PMC register specified in the ECX register into EDX:EAX. The use of RDPMC instructions is restricted by the Performance Monitoring Counter Enable, (PCE) flag in C4. When the PCE flag is set to 1, the RDPMC instruction can be executed at any privilege level. When the PCE flag is 0, the RDPMC instruction can only be executed at privilege level 0.
6.4 Counter Event Control Register
Register MSR 11h controls the two internal counters, #0 and #1. The events to be counted have been chosen based on the micro-architecture of the 6x86MX processor. The control register for the two event counters is described on page 46.
6.5
PM Pin Control
The Counter Event Control register (MSR11) contains PM control fields that define the PM0 and PM1 pins as counter overflow indicators or counter event indicators. When defined as event counters, the PM pins indicate that one or more events
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PM Pin Control
occurred during a particular clock cycle and do not count the actual events. When defined as overflow indicators, the event counters can be preset with a value less the 248-1 and allowed to increment as events occur. When the counter overflows the PM pin becomes asserted.
6.5.1
Counter Type Control
The Counter Type bit determines whether the counter will count clocks or events. When counting clocks the counter operates as a timer.
6.5.2
CPL Control
The Current Privilege Level (CPL) can be used to determine if the counters are enabled. The CP02 bit in the MSR 11 register enables counting when the CPL is less than three, and the CP03 bit enables counting when CPL is equal to three. If both bits are set, counting is not dependent on the CPL level; if neither bit is set, counting is disabled.
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PM Pin Control
2 6 T C 1 *
2 5 P M 1
2 4 C T 1
2 3 C P 1 3
2 2 C P 1 2
21 TC1*
16
15 RESERVED
10 T C 0 *
9 P M 0
8 C T 0
7 C P 0 3
6 C P 0 2
5 TC0*
0
*Note: Split Fields
Counter Event Control Register
Counter Event Control Register Bit Definitions
BIT POSITION 25 NAME PM1 DESCRIPTION Define External PM1 Pin If = 1: PM1 pin indicates counter overflows If = 0: PM1 pin indicates counter events Counter #1 Counter Type If = 1: Count clock cycles If = 0: Count events (reset state). Counter #1 CPL 3 Enable If = 1: Enable counting when CPL=3. If = 0: Disable counting when CPL=3. (reset state) Counter #1 CPL Less Than 3 Enable If = 1: Enable counting when CPL < 3. If = 0: Disable counting when CPL < 3. (reset state) Counter #1 Event Type Reset state = 0 Define External PM0 Pin If = 1: PM0 pin indicates counter overflows If = 0: PM0 pin indicates counter events Counter #0 Counter Type If = 1: Count clock cycles If = 0: Count events (reset state). Counter #0 CPL 3 Enable If = 1: Enable counting when CPL=3. If = 0: Disable counting when CPL=3. (reset state) Counter #0 CPL Less Than 3 Enable If = 1: Enable counting when CPL < 3. If = 0: Disable counting when CPL < 3. (reset state) Counter #0 Event Type Reset state = 0
24
CT1
23
CP13
22
CP12
26, 21 - 16 9
TC1(5-0) PM0
8
CT0
7
CP03
6
CP02
10, 5 - 0
TC0(5-0)
Note: Bits 10 - 15 are reserved.
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PM Pin Control
6.5.3
Event Type and Description
The events that can be counted by the performance monitoring counters are listed in Figure 1-. Each of the 127 event types is assigned an event number. A particular event number to be counted is placed in one of the MSR 11 Event Type fields. There is a separate field for counter #0 and #1. The events are divided into two groups. The occurrence type events and duration type events. The occurrence type events, such as hardware interrupts, are counted as single events. The duration type events such as "clock while bus cycles are in progress" count the number of clock cycles that occur during the event. During occurrence type events, the PM pins are configured to indicate the counter has incremented The PM pins will then assert every time the counter increments in regards to an occurrence event. Under the same PM control, for a duration event the PM pin will stay asserted for the duration of the event.
EVENT TYPE REGISTER
NUMBER 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah COUNTER 0 yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes COUNTER 1 yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes Data Reads Data Writes Data TLB Misses Cache Misses: Data Reads Cache Misses: Data Writes Data Writes that hit on Modified or Exclusive Liens Data Cache Lines Written Back External Inquiries External Inquires that hit Memory Accesses in both pipes Cache Bank conflicts Misaligned data references Instruction Fetch Requests L2 TLB Code Misses Cache Misses: Instruction Fetch Any Segment Register Load Reserved Reserved Any Branch BTB hits Taken Branches or BTB hits Pipeline Flushes Instructions executed in both pipes Instructions executed in Y pipe Clocks while bus cycles are in progress Pipe Stalled by full write buffers Pipe Stalled by waiting on data memory reads DESCRIPTION TYPE Occurrence Occurrence Occurrence Occurrence Occurrence Occurence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Duration Duration Duration
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PM Pin Control
EVENT TYPE REGISTER (CONTINUED)
NUMBER 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Bh 2Bh 2Dh 2Dh 2Eh 2Fh 2Fh 30h 31h 32h 32h 33h 34h 34h 35h 35h 36 36 37 37 38 38 39 39 3A COUNTER 0 yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes no yes no no yes no yes yes yes no no yes no yes no yes no yes no yes no yes no yes COUNTER 1 yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes no yes no yes yes no yes no no no yes yes no yes no yes no yes no yes no yes no yes no DESCRIPTION Pipe Stalled by writes to not-Modified or not-Exclusive cache lines. Locked Bus Cycles I/O Cycles Non-cacheable Memory Requests Pipe Stalled by Address Generation Interlock Reserved Reserved Floating Point Operations Breakpoint Matches on DR0 register Breakpoint Matches on DR1 register Breakpoint Matches on DR2 register Breakpoint Matches on DR3 register Hardware Interrupts Data Reads or Data Writes Data Read Misses or Data Write Misses MMX Instruction Executed in X pipe MMX Instruction Executed in Y pipe EMMS Instruction Executed Transition Between MMX Instruction and FP Instructions Reserved Saturating MMX Instructions Executed Saturations Performed Reserved MMX Instruction Data Reads Reserved Taken Branches Reserved Reserved Reserved Reserved Reserved Reserved Reserved Returns Predicted Incorrectly Return Predicted (Correctly and Incorrectly) MMX Instruction Multiply Unit Interlock MODV/MOVQ Store Stall Due to Previous Operation Returns RSB Overflows BTB False Entries Occurrence Occurrence Duration Duration Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence TYPE Duration Occurrence Occurrence Occurrence Duration
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Cyrix 6x86MX Application Note 103 - BIOS WRITER'S GUIDE
PM Pin Control
EVENT TYPE REGISTER (CONTINUED)
NUMBER 3A 3B 3B 3C - 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h COUNTER 0 no yes no yes yes yes yes yes yes yes yes yes yes yes COUNTER 1 yes no yes yes yes yes yes yes yes yes yes yes yes yes DESCRIPTION BTB Miss Prediction on a Not-Taken Back TYPE Occurrence
Number of Clock Stalled Due to Full Write Buffers While Execut- Duration ing Stall on MMX Instruction Write to E or M Line Reserved L2 TLB Misses (Code or Data) L1 TLB Data Miss L1 TLB Code Miss L1 TLB Miss (Code or Data) TLB Flushes TLB Page Invalidates TLB Page Invalidates that hit Reserved Instructions Decoded Reserved Occurrence Duration Duration Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence
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Instruction Set
7. Programming Model Differences 7.1 Instruction Set
The 6x86MX supports the Pentium Pro instruction set plus MMX instructions. Pentium extensions for virtual mode are not supported.
7.2
Configuring Internal 6x86MX Features
The 6x86MX supports configuring internal features through I/O ports.
7.3
INVD and WBINVD Instructions
The INVD and WBINVD instructions are used to invalidate the contents of the internal and external caches. The WBINVD instruction first writes back any modified lines in the cache and then invalidates the contents. It ensures that cache coherency with system memory is maintained regardless of the cache operating mode. Following invalidation of the internal cache, the CPU generates special bus cycles to indicate that external caches should also write back modified data and invalidate their contents. On the 6x86MX, the INVD functions identically to the WBINVD instruction. The 6x86MX always writes all modified internal cache data to external memory prior to invalidating the internal cache contents. In contrast, the Pentium invalidates the contents of its internal caches without writing back the "dirty" data to system memory.
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Cyrix 6x86MX Application Note 103 - BIOS WRITER'S GUIDE
Control Register 0 (CR0) CD and NW Bits
7.4 Control Register 0 (CR0) CD and NW Bits
The CPU's CR0 register contains, among other things, the CD and NW bits which are used to control the on-chip cache. CR0, like the other system level registers, is only accessible to programs running at the highest privilege level. The table on the following page lists the cache operating modes for all possible states of the CD and NW bits. The CD and NW bits are set to one (cache disabled) after reset. For highest performance the cache should be enabled in write-back mode by clearing the CD and NW bits to 0. Sample code for enabling the cache is listed in Appendix E. To completely disable the cache, it is recommended that CD and NW be set to 1 followed by execution of the WBINVD instruction. The 6x86MX cache always accepts invalidation cycles even when the cache is disabled. Setting CD=0 and NW=1 causes a General Protection fault on the Pentium, but is allowed on the 6x86MX to globally enable write-through caching.
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Control Register 0 (CR0) CD and NW Bits
CD 1
NW 1
OPERATING MODES Cache disabled. Read hits access the cache. Read misses do not cause line fills. Write hits update the cache and system memory. Write hits change exclusive lines to modified. Shared lines remain shared after write hit. Write misses access memory. Inquiry and invalidation cycles are allowed. System memory coherency maintained. Cache disabled. Read hits access the cache. Read misses do not cause line fills. Write hits update the cache. Only write hits to shared lines and write misses update system memory. Write misses access memory. Inquiry and invalidation cycles are allowed. System memory coherency maintained. Cache enabled in Write-through mode. Read hits access the cache. Read misses may cause line fills. Write hits update the cache and system memory. Write misses access memory. Inquiry and invalidation cycles are allowed. System memory coherency mai