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2 Megabit LPC Flash
SST49LF020
SST49LF0202 Mb LPC Flash
Advance Information
FEATURES:
· Standard LPC Interface Conforms to Intel LPC Interface Specification 1.0 · Organized as 256K x8 · Flexible Erase Capability Uniform 4 KByte sectors Uniform 16 KByte overlay blocks 16 KBytes Top boot block protection Chip-Erase for PP Mode · Single 3.0-3.6V Read and Write Operations · Superior Reliability Endurance: 100,000 Cycles (typical) Greater than 100 years Data Retention · Low Power Consumption Active Read Current: 10 mA (typical) Standby Current: 10 µA (typical) · Fast Sector-Erase/Byte-Program Operation Sector-Erase Time: 18 ms (typical) Block-Erase Time: 18 ms (typical) Chip-Erase Time: 70 ms (typical) Byte-Program Time: 14 µs (typical) Chip Rewrite Time: 4 seconds (typical) Single-pulse Program or Erase Internal timing generation · Two Operational Modes Low Pin Count (LPC) Interface mode for in-system operation Parallel Programming (PP) Mode for fast production programming · LPC Interface Mode 5-signal communication interface supporting byte Read and Write 33 MHz clock frequency operation WP# and TBL# pins provide hardware write protect for entire chip and/or top boot block Standard SDP Command Set Data# Polling and Toggle Bit for End-of-Write detection 5 GPI pins for system design flexibility · Parallel Programming (PP) Mode 11 pin multiplexed address and 8 pin data I/O interface Supports fast In-System or PROM programming for manufacturing · CMOS I/O Compatibility · Packages Available 32-lead PLCC 32-lead TSOP (8mm x 14mm)
PRODUCT DESCRIPTION
The SST49LF020 flash memory device is designed to interface with the LPC bus for PC and Internet Applicance applications. It provides protection for the storage and update of code and data in addition to adding system design flexibility through five General Purpose Inputs (GPI). The SST49LF020 is in compliance with Intel Low Pin Count (LPC) Interface Specification 1.0. Two interface modes are supported: LPC Mode for In-System programming and Parallel Programming (PP) Mode for fast factory programming. The SST49LF020 flash memory device is manufactured with SST's proprietary, high performance SuperFlash Technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST49LF020 device significantly improves performance and reliability, while lowering power consumption. The SST49LF020 device writes (Program or Erase) with a single 3.0-3.6V power supply. It uses less energy during Erase and Program than alternative flash memory technologies. The total energy consumed is a function of the applied voltage, current and time of application. Since for any give voltage range, the SuperFlash technology uses
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less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. The SST49LF020 product provides a maximum Byte-Program time of 20µsec. The entire memory can be erased and programmed byte-by-byte typically in 4 seconds, when using status detection features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. The SuperFlash technology provides fixed Erase and Program time, independent of the number of Erase/Program cycles that have performed. Therefore the system software or hardware does not have to be calibrated or correlated to the cumulative number of Erase/Program cycles as is necessary with alternative flash memory technologies, whose Erase and Program time increase with accumulated Erase/Program cycles. To protect against inadvertent write, the SST49LF020 device has on-chip hardware and software data (SDP) protection schemes. It is offered with a typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. Intel is a registered trademark of Intel Corporation. These specifications are subject to change without notice.
2 Megabit LPC Flash SST49LF020
Advance Information To meet high density, surface mount requirements, the SST49LF020 device is offered in 32-lead TSOP and 32lead PLCC packages. See Figures 1 and 2 for pinouts and Table 2 for pin descriptions. At the beginning of an operation, the host may hold the LFRAME# active for several clock cycles, and even change the Start value. The LAD[3:0] bus is latched every rising edge of the clock. On the cycle in which LFRAME# goes inactive, the last latched value is taken as the Start value. CE# must be asserted one cycle before the start cycle to select the SST49LF020 for Read and Write operations. Once the SST49LF020 identifies the operation as valid (a start value of all zeros), it next expects a nibble that indicates whether this is a memory read or program cycle. Once this is received, the device is now ready for the Address and Data cycles. For Program operation the Data cycle will follow the Address cycle, and for Read operation TAR and SYNC cycles occur between the Address and Data cycles. At the end of every operation, the control of the bus must be returned to the host by a 2 clock TAR cycle.
Mode Selection and Description
The SST49LF020 flash memory device operates in two distinct interface modes: the LPC mode and the Parallel Programming (PP) mode. The Mode pin is used to set the interface mode selection. If the Mode pin is set to logic High, the device is in PP mode; while if the Mode pin is set Low, the device is in the LPC mode. The Mode selection pin must be configured prior to device operation. In LPC mode, the device is configured to its host using standard LPC interface protocol. Communication between Host and the SST49LF020 occurs via the 4-bit I/O communication signals, LAD [3:0] and LFRAME#. In PP mode, the device is programmed via an 11-bit address and an 8-bit data I/O parallel signals. The address inputs are multiplexed in row and column selected by control signal R/C# pin. The row addresses are mapped to the higher internal addresses, and the column addresses are mapped to the lower internal addresses. See Device Memory Map for address assignments.
Device Memory Hardware Write Protection
The Top Boot Lock (TBL#) and Write Protect (WP#) pins are provided for hardware write protection of device memory in the SST49LF020. The TBL# pin is used to write protect four boot sectors (16 KBytes) at the highest memory address range. WP# pin write protects the remaining sectors in the flash memory. An active low signal at the TBL# pin prevents Program and Erase operations of the top boot sectors. When TBL# pin is held high, the write protection of the top boot sectors is disabled. The WP# pin serves the same function for the remaining sectors of the device memory. The TBL# and WP# pins write protection functions operate independently of one another. Both TBL# and WP# pins must be set to their required protection states prior to starting a Program or Erase operation. A logic level change occurring at the TBL# or WP# pin during a Program or Erase operation could cause unpredictable results.
LPC MODE Device Operation
The LPC mode uses a 5-signal communication interface, a 4-bit address/data bus, LAD[3:0], and a control line, LFRAME#, to control operations of the SST49LF020. Cycle type operations such as Memory Read and Memory Write are defined in Intel Low Pin Count Interface Specification, Revision 1.0. JEDEC Standard SDP (Software Data Protection) Program and Erase commands sequences are incorporated into the standard LPC memory cycles. See Figure 8 through Figure 13 timing diagrams for command sequences. LPC operations are transmitted via the 4-bit Address/Data bus (LAD[3:0]), and follow a particular sequence, depending on whether they are Read or Write operations. The standard LPC memory cycle is defined in Table 13. Both LPC Read and Write operations start in a similar way as shown in Figures 6 and 7 timing diagrams. The host (which is the term used here to describe the device driving the memory) asserts LFRAME# for one or more clocks and drives a start value on the LAD[3:0] bus.
Reset
A VIL on INIT# or RST# pins initiates a device reset. INIT# and RST# pins have same function internally. It is required to drive INIT# or RST# pins low during a system reset to ensure proper CPU initialization. During a Read operation, driving INIT# or RST# pins low deselects the device and places the output drivers, LAD[3:0], in a high-impedance state. The reset signal must be held low for a minimal duration of time TRSTP. A reset latency will occur if a reset procedure is performed during a Program or Erase operation. See Table 12, Reset Timing Parameters, for more information. A device reset during an active Program or Erase will abort the operation and memS71175-02-000 5/01 526
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2 Megabit LPC Flash SST49LF020
Advance Information ory contents may become invalid due to data being altered had been disrupted from an incomplete Erase or Program operation. GENERAL PURPOSE INPUTS REGISTER
Pin# Bit 7:5 4 Function Reserved GPI[4] Reads status of general purpose input pin GPI[3] Reads status of general purpose input pin GPI[2] Reads status of general purpose input pin GPI[1] Reads status of general purpose input pin GPI[0] Reads status of general purpose input pin 32-PLCC 30 32-TSOP 7
LFRAME#
The LFRAME# signifies the start of a frame or the termination of a broken frame. Asserting LFRAME# for one or more clock cycle and driving a valid START value on LAD[3:0] will initiate device operation. The device enters standby mode when LFRAME# and CE# are high and no internal operations is in progress.
Abort Mechanism
If LFRAME# is driven low for one or more clock cycles during a LPC cycle, the cycle will be terminated and the device will wait for the ABORT command. The host must drive the LAD[3:0] with `1111b' (ABORT command) to return the device to the ready mode. If abort occurs during the internal write cycle, the data may be incorrectly programmed or erased. It is required to wait for the Write operation to complete prior to initiation of the abort command. It is recommended to check the write status with Data# Polling (DQ7) or Toggle Bit (DQ6) pins. One other option is to wait for the fixed write time to expire.
3
15 3 4 16
2
1
5
17
0
6
18
Registers
There is one register available on the SST49LF020. The General Purpose Inputs Register. This register appears at its respective address location in the 4 GByte system memory map.
General Purpose Inputs Register
The GPI_REG (General Purpose Inputs Register) passes the state of GPI[4:0] pins at power-up on the SST49LF020. It is recommended that the GPI[4:0] pins be in the desired state before LFRAME# is brought low for the beginning of the next bus cycle, and remain in that state until the end of the cycle. There is no default value since this is a pass-through register. The GPI register appears at FFBC0100H in the 4 GBytes system memory map. See General Purpose Inputs Register table for the GPI_REG bits and function.
CE#
The CE# pin, enables and disables the SST49LF020, controlling read and write access of the device. To enable the SST49LF020, the CE# pin must be driven low one cycle prior to LFRAME# being driven low. For write (erase or program) cycles, the CE# pin must remain low during the internal programming. When CE# is high, the SST49LF020 is placed in low-power standby-mode.
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2 Megabit LPC Flash SST49LF020
Advance Information
PARALLEL PROGRAMMING MODE Device Operation
Commands are used to initiate the memory operation functions of the device. The data portion of the software command sequence is latched on the rising edge of WE#. During the software command sequence the row address is latched on the falling edge of R/C# and the column address is latched on the rising edge of R/C#.
Block-Erase Operation
The Block-Erase Operation allows the system to erase the device in 16 KByte uniform block size. The Block-Erase operation is initiated by executing a six-byte-command load sequence for Software Data Protection with BlockErase command (50H) and block address. The internal Block-Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 21 for BlockErase timing waveforms. Any commands written during the Block-Erase operation will be ignored.
Read
The Read operation of the SST49LF020 device is controlled by OE#. OE# is the output control and is used to gate data from the output pins. Refer to the Read cycle timing diagram, Figure 15, for further details.
Chip-Erase
The SST49LF020 device provides a Chip-Erase operation only in PP Mode, which allows the user to erase the entire memory array to the "1" state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE#. During the internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 22 for Chip-Erase timing diagram, and Figure 34 for the flowchart. Any commands written during the Chip-Erase operation will be ignored.
Reset
Driving the RST# low will initiate a hardware reset of the SST49LF020.
Byte-Program Operation
The SST49LF020 device is programmed on a byte-by-byte basis. The Byte-Program operation is initiated by executing a four-byte-command load sequence for Software Data Protection with address (BA) and data in the last byte sequence. During the Byte-Program operation, the row address (A10-A0) is latched on the falling edge of R/C# and the column address (A21-A11) is latched on the rising edge of R/C#. The data bus is latched on the rising edge of WE#. The Program operation, once initiated, will be completed, within 20 µs. See Figures 7 and 19 for Program operation timing diagram and Figure 31 for its flowchart. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored.
Write Operation Status Detection
The SST49LF020 device provides two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE# which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
Sector-Erase Operation
The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The Sector-Erase operation is initiated by executing a six-bytecommand load sequence for Software Data Protection with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 20 for Sector-Erase timing waveforms. Any commands written during the Sector-Erase operation will be ignored.
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2 Megabit LPC Flash SST49LF020
Advance Information
Data# Polling (DQ7)
When the SST49LF020 device is in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. The device is then ready for the next operation. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of fourth WE# pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# pulse. See Figures 9 and 17 for Data# Polling timing diagram and Figure 33 for a flowchart.
six byte load sequence. The SST49LF020 device is shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode, within TRC.
Electrical Specifications
The AC and DC specifications for the LPC interface signals (LAD[3:0], LCLCK. LFRAME# and RST#) as defined in Section 4.2.2 of the "PCI Local Bus specification, Rev. 2.1". Refer to Table 5 for the DC voltage and current specifications. Refer to Tables 11, 12, 14, and 15 for the AC timing specifications for Clock, Read, Program, Erase and Reset operations.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating "0" and "1", i.e., toggling between "0" and "1". When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# pulse for Program operation. For Sector-, Block- or ChipErase, the Toggle Bit is valid after the rising edge of sixth WE# pulse. See Figures 10 and 18 for Toggle Bit timing diagram and Figure 32 for a flowchart.
Product Identification Mode
The product identification mode identifies the device as SST49LF020 and the manufacturer as SST. TABLE 1: PRODUCT IDENTIFICATION
Address Manufacturer's ID Device ID SST49LF020 00000H 00001H Data BFH 61H
T1.4 526
Data Protection
The SST49LF020 device provides both hardware and software features to protect nonvolatile data from inadvertent writes.
Design Considerations
SST recommends a high frequency 0.1 µF ceramic capacitor to be placed as close as possible between VDD and VSS less than 1 cm away from the VDD pin of the device. Additionally, a low frequency 4.7 µF electrolytic capacitor from VDD to VSS should be placed within 5 cm of the VDD pin. If you use a socket for programming purposes add an additional 1-10 µF next to each socket. The RST# pin must remain stable at VIH for the entire duration of an Erase operation. WP# must remain stable at VIH for the entire duration of the Erase and Program operations for non-boot block sectors. To write data to the top boot block sectors, the TBL# pin must also remain stable at VIH for the entire duration of the Erase and Program operations.
Hardware Data Protection
Noise/Glitch Protection: A WE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
Software Data Protection (SDP)
The SST49LF020 provides the JEDEC approved Software Data Protection scheme for all data alteration operation, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three byte sequence. The three byte-load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of
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2 Megabit LPC Flash SST49LF020
Advance Information
FUNCTIONAL BLOCK DIAGRAM
TBL# WP# INIT#
X-Decoder
LAD[3:0] LCLK LFRAME# GPI[4:0] R/C# A[10:0] DQ[7:0] OE# WE#
SuperFlash Memory
LPC Interface
Address Buffers & Latches Y-Decoder
Control Logic
I/O Buffers and Data Latches
Programmer Interface
MODE RST# CE#
526 ILL B1.1
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2 Megabit LPC Flash SST49LF020
Advance Information
TBL#
Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8
3FFFFH
Boot Block
3C000H 3BFFFH 38000H 37FFFH 34000H 33FFFH 30000H 2FFFFH 2C000H 2BFFFH 28000H 27FFFH 24000H 23FFFH
WP# for Block 0~14
20000H 1FFFFH Block 7 1C000H 1BFFFH Block 6 18000H 17FFFH Block 5 14000H 13FFFH Block 4 10000H 0FFFFH Block 3 0C000H 0BFFFH Block 2 Block 1 08000H 07FFFH 04000H 03FFFH 300000 02FFFH 02000H 01FFFH 01000H 00FFFH 00000H
4 KByte Sector 3 4 KByte Sector 2 4 KByte Sector 1 4 KByte Sector 0
526 ILL F52.3
Block 0 (16 KByte)
DEVICE MEMORY MAP
FOR
SST49LF020
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2 Megabit LPC Flash SST49LF020
Advance Information
NC NC NC NC (CE#) MODE (MODE) A10 (GPI4) R/C# (LCLK) VDD (VDD) NC RST# (RST#) A9 (GPI3) A8 (GPI2) A7 (GPI1) A6 (GPI0) A5 (WP#) A4 (TBL#)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Standard Pinout Top View Die Up
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE# (INIT#) WE# (LFRAME#) VDD (VDD) DQ7 (RES) DQ6 (RES) DQ5 (RES) DQ4 (RES) DQ3 (LAD3) VSS (VSS) DQ2 (LAD2) DQ1 (LAD1) DQ0 (LAD0) A0 (RES) A1 (RES) A2 (RES) A3 (RES)
526 ILL F01.2
( ) Designates LPC Mode
FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM
X
14MM)
RST# (RST#)
VDD (VDD)
R/C# (LCLK)
A8 (GPI2)
A9 (GPI3)
A7(GPI1) A6 (GPI0) A5 (WP#) A4 (TBL#) A3 (RES) A2 (RES) A1 (RES) A0 (RES) DQ0 (LAD0)
5 6 7 8 9 10 11 12 13
4
3
2
NC
1
32 31 30 29 28 27 26 25 24 23 22
A10 (GPI4)
MODE (MODE) NC (CE#) NC NC VDD (VDD) OE# (INIT#) WE# (LFRAME#) NC DQ7 (RES)
32-lead PLCC Top View
21 14 15 16 17 18 19 20 DQ3 (LAD3) DQ4 (RES) DQ5 (RES) DQ1 (LAD1) DQ2 (LAD2) DQ6 (RES) VSS (VSS)
526 ILL F02.2
( ) Designates LPC Mode
FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD PLCC
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2 Megabit LPC Flash SST49LF020
Advance Information TABLE 2: PIN DESCRIPTION
Interface Symbol A10-A0 Pin Name Address Type1 PP LPC Functions I X Inputs for low-order addresses during Read and Write operations. Addresses are internally latched during a Write cycle. For the programming interface, these addresses are latched by R/C# and share the same pins as the high-order address inputs. To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# is high. To gate the data output buffers. To control the Write operations. X This pin determines which interface is operational. When held high, programmer mode is enabled and when held low, LPC mode is enabled. This pin must be setup at power-up or before return from reset and not change during device operation. This pin is internally pulled down with a resistor between 20-100K. This is the second reset pin for in-system use. This pin is internally combined with the RST# pin; If this pin or RST# pin is driven low, identical operation is exhibited. These individual inputs can be used for additional board flexibility. The state of these pins can be read through LPC registers. These inputs should be at their desired state before the start of the PCI clock cycle during which the read is attempted, and should remain in place until the end of the Read cycle. Unused GPI pins must not be floated. When low, prevents programming boot block sectors at top of memory. When TBL# is high it disables hardware write protection for the top block sectors. To provide LPC control signals, as well as addresses and Command Inputs/Outputs data. To provide a clock input to the control unit To indicate start of a data transfer operation; also used to abort an LPC cycle in progress. To reset the operation of the device When low, prevents programming to all but the highest addressable top boot blocks. When WP# is high it disables hardware write protection for these blocks. Select for the Programming interface, this pin determines whether the address pins are pointing to the row addresses, or to the column addresses. X I I I I X X X X X X X These pins must be left unconnected. To provide power supply (3.0-3.6V) Circuit ground (OV reference) This signal must be asserted to select the device. When CE# is low, the device is enabled. When CE# is high, the device is placed in low power standby mode. Unconnected pins.
T2.3 526
DQ7-DQ0
Data
I/O
X
OE# WE# MODE
Output Enable Write Enable Interface Mode Select
I I I
X X X
INIT#
Initialize
I
X
GPI[4:0]
General Purpose Inputs
I
X
TBL# LAD[3:0] LCLK
Top Block Lock Address and Data Clock
I I/O I I I I I X X
X X X X X X
LFRAME# Frame RST# WP# R/C# RES VDD Vss CE# NC Reset Write Protect Row/Column Select Reserved Power Supply Ground Chip Enable No Connection
1. I=Input, O=Output
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Advance Information TABLE 3: OPERATION MODES SELECTION (PP MODE)
Mode Read Program Erase Reset Write Inhibit Product Identification RST# OE# VIL WE# DQ DOUT DIN X1 High Z High Z/DOUT High Z/DOUT Manufacturer's ID (BFH) Device ID2 Address AIN AIN Sector or Block address, XXH for Chip-Erase X X X A18-A1=VIL, A0=VIL A18-A1=VIL, A0=VIH
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VIH VIH VIH
VIL
VIL
VIL VIL X VIL X VIL
VIH VIH
X VIL
VIH
X
VIH
VIL
VIH
1. X can be VIL or VIH, but no other value. 2. Device ID = 61H
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command Sequence Byte-Program Sector-Erase Block-Erase Chip-Erase6 Software ID Entry7 Software ID Exit8 Software ID Exit8 1st1 Write Cycle Addr2 5555H 5555H 5555H 5555H 5555H XXH 5555H Data AAH AAH AAH AAH AAH F0H AAH 2AAAH 55H 5555H F0H
T4.5 526
2nd1 Write Cycle Addr2 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Data 55H 55H 55H 55H 55H
3rd1 Write Cycle Addr2 5555H 5555H 5555H 5555H 5555H Data A0H 80H 80H 80H 90H
4th1 Write Cycle Addr2 BA3 5555H 5555H 5555H Data Data AAH AAH AAH
5th1 Write Cycle Addr2 2AAAH 2AAAH 2AAAH Data 55H 55H 55H
6th1 Write Cycle Addr2 SAx4 BAx5 5555H Data 30H 50H 10H
1. LPC Mode use consecutive Write cycles to complete a command sequence; PP Mode use consecutive bus cycles to complete a command sequence. 2. Address format A14-A0 (Hex), Addresses A15-A21 can be VIL or VIH, but no other value, for the Command sequence in PP Mode. 3. BA = Program Byte address 4. SAx for Sector-Erase Address 5. BAx for Block-Erase Address 6. Chip-Erase is supported in PP Mode only 7. With A17-A1=0; SST Manufacturer's ID=BFH, is read with A0=0. SST49LF020 Device ID = 61H, is read with A0=1. 8. Both Software ID Exit operations are equivalent
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2 Megabit LPC Flash SST49LF020
Advance Information Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD + 1.0V Package Power Dissipation Capability (Ta=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range Commercial Ambient Temp 0°C to +85°C VDD 3.0-3.6V
AC CONDITIONS
OF
TEST1
Input Rise/Fall Time . . . . . . . . . . . . . . . 3 ns Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 25 and 26
1. LPC interface signals use PCI load condition.
TABLE 5: DC OPERATING CHARACTERISTICS (ALL INTERFACES)
Limits Symbol IDD Parameter Power Supply Current Read Write ISB Standby VDD Current (LPC Interface) Ready Mode VDD Current (LPC Interface) Input Current for IC Pin Input Leakage Current Output Leakage Current INIT# Input High Voltage INIT# Input Low Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 0.9 VDD 1.0 -0.5 -0.5 0.5 VDD 12 24 100 mA mA µA Min Max Units Test Conditions Address input=VIL/VIH, at f=1/TRC Min, VDD=VDD Max (PP Mode) OE#=VIH, WE#=VIH OE#=VIH, WE#=VIL, VDD=VDD Max (PP Mode) LFRAME#=VIH, f=33 MHz, CE#=VIH VDD=VDD Max, All other inputs 0.9 VDD or 0.1 VDD LFRAME#=VIL, f=33 MHz, VDD=VDD Max All other inputs 0.9 VDD or 0.1 VDD VIN=GND to VDD, VDD=VDD Max VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Max VDD=VDD Max VDD=VDD Min VDD=VDD Max IOL=1500 µA, VDD=VDD Min IOH=-500 µA, VDD=VDD Min
T5.5 526
IRY1 II ILI ILO VIHI VILI VIL
10 200 1 1 VDD+0.5 0.4 0.3 VDD VDD+0.5 0.1 VDD
mA µA µA µA V V V V V V
VIH
VOL VOH
1. The device is in Ready Mode when no activity is on the LPC bus.
©2001 Silicon Storage Technology, Inc.
S71175-02-000 5/01
526
11
2 Megabit LPC Flash SST49LF020
Advance Information TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ1 TPU-WRITE
1
Parameter Power-up to Read Operation Power-up to Write Operation
Minimum 100 100
Units µs µs
T6.1 526
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter
TABLE 7: PIN CAPACITANCE
Parameter CI/O
1
(VDD=3.3V, Ta=25 °C, f=1 Mhz, other pins open)
Description I/O Pin Capacitance Input Capacitance Pin Inductance
Test Condition VI/O=0V VIN=0V
Maximum 12 pF 6 pF 20 nH
T7.0 526
CIN1 LPIN
2
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. Refer to PCI Spec.
TABLE 8: RELIABILITY CHARACTERISTICS
Symbol NEND1 TDR1 ILTH1 Parameter Endurance Data Retention Latch Up Minimum Specification 10,000 100 100 + IDD Units Cycles Years mA Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78
T8.1 526
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 9: CLOCK TIMING PARAMETERS (LPC MODE)
Symbol TCYC THIGH TLOW Parameter LCLK Cycle Time LCLK High Time LCLK Low Time LCLK Slew Rate (peak-to-peak) RST# or INIT# Slew Rate Min 30 11 11 1 50 4 Max Units ns ns ns V/ns mV/ns
T9.0 526
Tcyc Thigh 0.6 VDD 0.5 VDD 0.4 VDD 0.3 VDD 0.2 VDD
526 ILL F27.0
Tlow 0.4 VDD p-to-p (minimum)
FIGURE 3: LCLK WAVEFORM
©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 526
12
2 Megabit LPC Flash SST49LF020
Advance Information
VTH
CLK
VTEST VTL TVAL
LAD [3:0] (Valid Output Data)
LAD [3:0] (Float Output Data)
TON TOFF
526 ILL F49.1
FIGURE 4: OUTPUT TIMING PARAMETERS
VTH
CLK
TSU
VTEST VTL
TDH
LAD [3:0] (Valid Input Data)
Inputs Valid
VMAX
526 ILL F50.1
FIGURE 5: INPUT TIMING PARAMETERS
TABLE 10: INTERFACE MEASUREMENT CONDITION PARAMETERS
Symbol VTH1 VTL
1
Value 0.6 VDD 0.2 VDD 0.4 VDD 0.4 VDD 1 V/ns
Units V V V V
T10.2 526
VTEST VMAX
1
Input Signal Edge Rate
1. The input test environment is done with 0.1 VDD of overdrive over VIH and VIL. Timing parameters must be met with no more overdrive than this. VMAX specifies the maximum peak-to-peak waveform allowed for measuring input timing. Production testing may use different voltage values, but must correlate results back to these parameters.
©2001 Silicon Storage Technology, Inc.
S71175-02-000 5/01
526
13
2 Megabit LPC Flash SST49LF020
Advance Information
AC CHARACTERISTICS (LPC MODE)
TABLE 11: READ/WRITE CYCLE TIMING PARAMETERS (LPC MODE), VDD=3.0-3.6V
Symbol TCYC TSU TDH TVAL TBP TSE TBE Parameter Clock Cycle Time Data Set Up Time to Clock Rising Clock Rising to Data Hold Time Clock Rising to Data Valid Byte Programming Time Sector-Erase Time Block-Erase Time Min 30 7 0 2 11 20 25 25 Max Units ns ns ns ns µs ms ms
T11.1 526
TABLE 12: RESET TIMING PARAMETERS, VDD = 3.0-3.6V
Symbol TPRST TKRST TRSTP TRSTF TRST VDD stable to Reset Active Clock Stable to Reset Active Reset Pulse Width Reset Active to Output Float Reset Inactive to Input Active Parameter Min 1 100 100 50 1 Max Units ms µs ns ns µs
T12.1 526
TABLE 13: STANDARD LPC MEMORY CYCLE DEFINITION (LPC MODE)
Field START CYCTYPE + DIR No. of Clocks 1 1 Description "0000b" appears on LPC bus to indicate the start of cycle Cycle Type: Indicates the type of cycle. Bits 3:2 must be "01b" for memory cycle. Bit 2 indicates the type of transfer "0" for Read, "1" for write. DIR: Indicates the direction of the transfer. "0b" for Read, "1b" for Write. Bit 0 is reserved. "010Xb" indicates memory Read cycle; while "011xb" indicates memory Write cycle. The last component driving LAD[3:0] will drive it to "1111b" during the first clock, and tri-state it during the second clock. Address Phase for Memory Cycle. LPC supports the 32-bit address protocol. The addresses transfer most significant nibble first and least significant nibble last. (i.e., Address[31:28] on LAD[3:0] first, and Address[3:0] on LAD[3:0] last.) Synchronize to host or peripheral by adding wait states. "0000b" means Ready, "0101b" means Short Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b" means error, other values are reserved. Data Phase for Memory Cycle. The data transfer least significant nibble first and most significant nibble last. (i.e., DQ[3:0] on LAD[3:0] first, then DQ[7:4] on LAD[3:0] last.)
T13.0 526
TAR ADDR
2 8
Sync
N
Data
2
©2001 Silicon Storage Technology, Inc.
S71175-02-000 5/01
526
14
2 Megabit LPC Flash SST49LF020
Advance Information
TCYC
LCLK CE#
RST# LFRAME#
Start Memory Read Cycle 010Xb xxxxb xxxxb xxxxb Address A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] 1111b TAR Tri-State
TVAL Sync 0000b
TSU TDH Data Next Start D[7:4] TAR 0000b 1 Clock 526 ILL F10.2
LAD[3:0]
0000b
D[3:0]
1 Clock 1 Clock
Load Address in 8 Clocks
2 Clocks
1 Clock Data Out 2 Clocks
FIGURE 6: READ CYCLE TIMING DIAGRAM (LPC MODE)
TCYC
LCLK CE# RST# LFRAME#
Start Memory Write Cycle 011Xb xxxxb xxxxb xxxxb Address A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] TSU TDH Data D[3:0] D[7:4] TAR 1111b Tri-State 2 Clocks Sync 0000b 1 Clock TAR Next Start 0000b 1 Clock 526 ILL F46.2
LAD[3:0]
0000b
1 Clock 1 Clock
Load Address in 8 Clocks
Load Data in 2 Clocks
FIGURE 7: WRITE CYCLE TIMING DIAGRAM (LPC MODE)
©2001 Silicon Storage Technology, Inc.
S71175-02-000 5/01
526
15
2 Megabit LPC Flash SST49LF020
Advance Information
LCLK RST# CE# LFRAME#
Memory Write Cycle 011Xb xxxxb xxxxb xxxxb Start next Command TAR 1 Clock
LAD[3:0]
1st Start 0000b
Address xxxxb X101b 0101b 0101b 0101b 1010b
Data 1010b
TAR 1111b
Sync
Tri-State 0000b 1 Clock
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
Write the 1st command to the device in LPC mode.
LCLK RST# = VIH CE# = VIL LFRAME#
Memory Write 2nd Start Cycle 0000b 011Xb xxxxb xxxxb xxxxb Start next Command TAR 1 Clock
LAD[3:0]
Address xxxxb X010b 1010b 1010b 1010b
Data 0101b 0101b
TAR 1111b Tri-State
Sync 0000b 1 Clock
1 Clock 1 Clock
Load Address "2AAA" in 8 Clocks
Load Data "55" in 2 Clocks
2 Clocks
Write the 2nd command to the device in LPC mode.
LCLK RST# = VIH CE# = VIL LFRAME# LAD[3:0]
3rd Start 0000b 011Xb xxxxb xxxxb xxxxb Address xxxxb X010b 1010b 1010b 1010b Data 0101b 0101b TAR 1111b Sync TAR 1 Clock Start next Command
Tri-State 0000b 1 Clock
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
Load Data "A0" in 2 Clocks 2 Clocks
Write the 3rd command to the device in LPC mode.
LCLK RST# = VIH CE# = VIL LFRAME#
Memory Write 4th Start Cycle 0000b 011Xb xxxxb xxxxb xxxxb Address A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] Data D[3:0] D[7:4] 1111b TAR Sync TAR Internal program start Internal program start
LAD[3:0]
Tri-State 0000b 1 Clock
1 Clock 1 Clock
Load Ain in 8 Clocks
Load Data in 2 Clocks
2 Clocks
Write the 4th command (target locations to be programmed) to the device in LPC mode. 526 ILL F18.3
FIGURE 8: PROGRAM CYCLE TIMING DIAGRAM (LPC MODE)
©2001 Silicon Storage Technology, Inc.
S71175-02-000 5/01
526
16
2 Megabit LPC Flash SST49LF020
Advance Information
LCLK
RST# CE# LFRAME#
Memory Write Cycle xxxxb xxxxb xxxxb Start next Command 0000b 1 Clock
LAD[3:0]
1st Start
Address A[19:16] A[15:12] A[11:8] A[7:4] A3:0] D3:0]
Data D[7:4]
TAR 1111b Tri-State
Sync 0000b 1 Clock TAR
0000b 011Xb 1 Clock 1 Clock
Load Address "An" in 8 Clocks
Load Data "Dn" in 2 Clocks 2 Clocks
Write the last command (Program or Erase) to the device in LPC mode.
LCLK RST# = VIH CE# = VIL LFRAME#
Memory Read Cycle 010Xb xxxxb xxxxb xxxxb Next start Address A[19:16] A[15:12] A[11:8] A[7:4] A3:0] TAR 1111b Tri-State Sync 0000b 1 Clock Data XXXXb D7#,xxx TAR 0000b 1 Clock
LAD[3:0]
Start 0000b
1 Clock 1 Clock
2 Clocks Load Address in 8 Clocks Read the DQ7 to see if internal write complete or not.
Data out 2 Clocks
LCLK RST# = VIH CE# = VIL LFRAME#
Start 0000b Memory Read Cycle 010Xb xxxxb xxxxb xxxxb Next start Address A[19:16] A[15:12] A[11:8] A[7:4] A3:0] TAR 1111b Tri-State 2 Clocks Sync 0000b Data XXXXb D7,xxx TAR 0000b 1 Clock 526 ILL F19.2
LAD[3:0]
1 Clock 1 Clock
Load Address in 8 Clocks When internal write complete, the DQ7 will equal to D7.
1 Clock Data out 2 Clocks
FIGURE 9: DATA# POLLING TIMING DIAGRAM (LPC MODE)
©2001 Silicon Storage Technology, Inc.
S71175-02-000 5/01
526
17
2 Megabit LPC Flash SST49LF020
Advance Information
LCLK
RST# CE# LFRAME#
Memory Write Cycle 011Xb xxxxb xxxxb xxxxb Start next Command TAR 0000b 1 Clock
LAD[3:0]
1st Start 0000b
Address A[19:16] A[15:12] A[11:8] A[7:4] A3:0] D3:0]
Data D[7:4]
TAR 1111b Tri-State 2 Clocks
Sync 0000b 1 Clock
1 Clock 1 Clock
Load Address "An" in 8 Clocks
Load Data "Dn" in 2 Clocks
Write the last command (Program or Erase) to the device in LPC mode.
LCLK RST# = VIH CE# = VIL LFRAME#
Memory Read Cycle 010Xb xxxxb xxxxb xxxxb Next start Address A[19:16] A[15:12] A[11:8] A[7:4] A3:0] TAR 1111b Tri-State 2 Clocks Sync 0000b 1 Clock Data XXXXb X,D6#,XXb TAR 0000b 1 Clock
LAD[3:0]
Start 0000b
1 Clock 1 Clock
Load Address in 8 Clocks Read the DQ6 to see if internal write complete or not.
LCLK RST# = VIH CE# = VIL LFRAME#
Start 0000b Memory Read Cycle 010Xb xxxxb xxxxb xxxxb Next start Address A[19:16] A[15:12] A[11:8] A[7:4] A3:0] TAR 1111b Tri-State Sync 0000b Data XXXXb X,D6,XXb TAR 0000b 1 Clock 526 ILL F20.2
LAD[3:0]
1 Clock 1 Clock
Load Address in 8 Clocks When internal write complete, the DQ6 will stop toggle.
2 Clocks
1 Clock Data out 2 Clocks
FIGURE 10: TOGGLE BIT TIMING DIAGRAM (LPC MODE)
©2001 Silicon Storage Technology, Inc.
S71175-02-000 5/01
526
18
2 Megabit LPC Flash SST49LF020
Advance Information
LCLK RST# CE# LFRAME# LAD[3:0]
1st Start 0000b Memory Write Cycle 011Xb xxxxb xxxxb xxxxb Address xxxxb X101b 0101b 0101b 0101b Data 1010b 1010b TAR 1111b Sync TAR 1 Clock Start next Command
Tri-State 0000b 1 Clock
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
Write the 1st command to the device in LPC mode.
LCLK RST# = VIH CE# = VIL LFRAME#
2nd Start 0000b Memory Write Cycle 011Xb xxxxb xxxxb xxxxb Address xxxxb X010b 1010b 1010b 1010b Data 0101b 0101b 1111b TAR Sync TAR 1 Clock Start next Command
LAD[3:0]
Tri-State 0000b 1 Clock
1 Clock 1 Clock
Load Address "2AAA" in 8 Clocks
Load Data "55" in 2 Clocks
2 Clocks
Write the 2nd command to the device in LPC mode.
LCLK RST# = VIH CE# = VIL LFRAME#
3rd Start Memory Write Cycle xxxxb xxxxb xxxxb
Address xxxxb X101b 0101b 0101b 0101b
Data 0000b 1000b
TAR 1111b Tri-State
Sync 0000b 1 Clock TAR
Start next Command 1 Clock
LAD[3:0]
0000b 011Xb 1 Clock 1 Clock
Load Address "5555" in 8 Clocks
Load Data "80" in 2 Clocks
2 Clocks
Write the 3rd command to the device in LPC mode.
LCLK RST# = VIH CE# = VIL LFRAME#
4th Start
Memory Write Cycle xxxxb xxxxb xxxxb
Address xxxxb X101b 0101b 0101b 0101b
Data 1010b 1010b
TAR 1111b Tri-State
Sync 0000b 1 Clock TAR
Start next Command 1 Clock
LAD[3:0]
0000b 011Xb 1 Clock 1 Clock
Load Address "5555" in 8 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
Write the 4th command to the device in LPC mode.
LCLK RST# = VIH CE# = VIL LFRAME#
5th
Memory Write Cycle xxxxb xxxxb xxxxb
Address xxxxb X010b 1010b 1010b 1010b
Data 0101b 0101b
TAR 1111b Tri-State 2 Clocks
Sync 0000b 1 Clock TAR
Start next Command 1 Clock
LAD[3:0]
0000b 011Xb 1 Clock 1 Clock
Load Address "2AAA" in 8 Clocks
Load Data "55" in 2 Clocks
Write the 5th command to the device in LPC mode.
LCLK RST# = VIH CE# = VIL LFRAME#
6th Start Memory Write Cycle xxxxb xxxxb xxxxb Address A[19:16] SAX XXXXb XXXXb XXXXb Data 0000b 0011b TAR 1111b Tri-State Sync 0000b 1 Clock TAR Internal erase start Internal erase start
LAD[3:0]
0000b 011Xb 1 Clock 1 Clock
Load Sector Address in 8 Clocks
Load Data "30" in 2 Clocks
2 Clocks
Write the 6th command (target sector to be erased) to the device in LPC mode. SAX = Sector Address
526 ILL F23.3
FIGURE 11: SECTOR-ERASE TIMING DIAGRAM (LPC MODE)
©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 526
19
2 Megabit LPC Flash SST49LF020
Advance Information
LCLK
RST# CE# LFRAME#
1st Start Memory Write Cycle 011Xb xxxxb xxxxb xxxxb
Address xxxxb X101b 0101b 0101b 0101b
Data 1010b 1010b
TAR 1111b
Sync TAR
Start next Command 1 Clock
LAD[3:0]
0000b
Tri-State 0000b 1 Clock
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
Write the 1st command to the device in LPC mode.
LCLK RST# = VIH CE# = VIL LFRAME#
2nd Start
Memory Write Cycle 011Xb xxxxb xxxxb xxxxb
Address xxxxb X010b 1010b 1010b 1010b
Data 0101b 0101b
TAR 1111b Tri-State 2 Clocks
Sync 0000b 1 Clock TAR
Start next Command 1 Clock
LAD[3:0]
0000b
1 Clock 1 Clock
Load Address "2AAA" in 8 Clocks
Load Data "55" in 2 Clocks
Write the 2nd command to the device in LPC mode.
LCLK RST# = VIH CE# = VIL LFRAME#
3rd Start
Memory Write Cycle 011Xb xxxxb xxxxb xxxxb
Address xxxxb X101b 0101b 0101b 0101b
Data 0000b 1000b
TAR 1111b Tri-State 2 Clocks
Sync 0000b 1 Clock TAR
Start next Command 1 Clock
LAD[3:0]
0000b
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
Load Data "80" in 2 Clocks
Write the 3rd command to the device in LPC mode.
LCLK RST# = VIH CE# = VIL LFRAME#
4th Start Memory Write Cycle xxxxb xxxxb xxxxb Address xxxxb X101b 0101b 0101b 0101b Data 1010b 1010b 1111b TAR Tri-State Sync 0000b 1 Clock TAR 1 Clock
LAD[3:0]
Start next Command
0000b 011Xb 1 Clock 1 Clock
Load Address "5555" in 8 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
Write the 4th command to the device in LPC mode.
LCLK RST# = VIH CE# = VIL LFRAME#
5th Memory Write Cycle 011Xb xxxxb xxxxb xxxxb Address xxxxb X010b 1010b 1010b 1010b Data 0101b 0101b TAR 1111b Tri-State Sync 0000b 1 Clock TAR 1 Clock
LAD[3:0]
Start next Command
0000b
1 Clock 1 Clock
Load Address "2AAA" in 8 Clocks
Load Data "55" in 2 Clocks
2 Clocks
Write the 5th command to the device in LPC mode.
LCLK RST# = VIH CE# = VIL LFRAME#
6th Start Memory Write Cycle 011Xb xxxxb xxxxb Address XXXXb xxxxb A[19:16] BAX Load Block Address in 8 Clocks XXXXb XXXXb Data 0000b 0101b TAR 1111b Sync TAR Internal erase start Internal erase start
LAD[3:0]
0000b
Tri-State 0000b 1 Clock
1 Clock 1 Clock
Load Data "50" in 2 Clocks
2 Clocks
Write the 6th command (target sector to be erased) to the device in LPC mode. BAX = Block Address
526 ILL F47.3
FIGURE 12: BLOCK-ERASE TIMING DIAGRAM (LPC MODE)
©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 526
20
2 Megabit LPC Flash SST49LF020
Advance Information
LCLK RST# CE# LFRAME# LAD[3:0]
Start 0000b Memory Read Cycle 010Xb 1111b 1111b 1011b Address 1100b 0000b 0001b 0000b 0000b TAR 1111b Tri-State Sync 0000b 1 Clock Data D[3:0] D[7:4] TAR Start next 0000b 1 Clock
1 Clock 1 Clock
Load Address "FFBC0100(hex)" in 8 Clocks
2 Clocks
Data out 2 Clocks
Note: Read the DQ[4:0] to capture the states (High or Low) of the GPI[4:0] input pins. The DQ[7:5] are reserved pins.
526 ILL F24.1
FIGURE 13: GPI REGISTER READOUT TIMING DIAGRAM (LPC MODE)
VDD LCLK
TPRST
TKRST
RST#/INIT#
TRSTF
TRSTP
TRST
LAD[3:0]
LFRAME#
526 ILL F25.0
FIGURE 14: RESET TIMING DIAGRAM (LPC MODE)
©2001 Silicon Storage Technology, Inc.
S71175-02-000 5/01
526
21
2 Megabit LPC Flash SST49LF020
Advance Information
AC CHARACTERISTICS (PP MODE)
TABLE 14: READ CYCLE TIMING PARAMETERS VDD=3.0-3.6V (PP MODE)
Symbol TRC TRST TAS TAH TAA TOE TOLZ TOHZ TOH Parameter Read Cycle Time RST# High to Row Address Setup R/C# Address Set-up Time R/C# Address Hold Time Address Access Time Output Enable Access Time OE# Low to Active Output OE# High to High-Z Output Output Hold from Address Change 0 0 35 Min 270 1 45 45 120 60 Max Units ns µs ns ns ns ns ns ns ns
T14.1 526
TABLE 15: PROGRAM/ERASE CYCLE TIMING PARAMETERS VDD=3.0-3.6V (PP MODE)
Symbol TRST TAS TAH TCWH TOES TOEH TOEP TOET TWP TWPH TDS TDH TIDA TBP TSE TBE TSCE Parameter RST# High to Row Address Setup R/C# Address Setup Time R/C# Address Hold Time R/C# to Write Enable High Time OE# High Setup Time OE# High Hold Time OE# to Data# Polling Delay OE# to Toggle Bit Delay WE# Pulse Width WE# Pulse Width High Data Setup Time Data Hold Time Software ID Access and Exit Time Byte Programming Time Sector-Erase Time Block-Erase Time Chip-Erase Time 100 100 50 5 150 20 25 25 100 Min 1 50 50 50 20 20 40 40 Max Units µs ns ns ns ns ns ns ns ns ns ns ns ns µs ms ms ms
T15.1 526
©2001 Silicon Storage Technology, Inc.
S71175-02-000 5/01
526
22
2 Megabit LPC Flash SST49LF020
Advance Information
RST#
TRST TRC Row Address TAS TAH Column Address TAS TAH Row Address Column Address
Addresses
R/C# WE# OE#
TOE TOLZ VIH TAA TOH TOHZ Data Valid High-Z 526 ILL F28.0
DQ7-0
High-Z
FIGURE 15: READ CYCLE TIMING DIAGRAM (PP MODE)
TRST
RST# Addresses
Row Address TAS TAH Column Address TAS TAH
R/C#
TCWH TOEH
OE# WE#
TOES TWP TWPH TDH
TDS
DQ7-0
Data Valid 526 ILL F29.0
FIGURE 16: WRITE CYCLE TIMING DIAGRAM (PP MODE)
©2001 Silicon Storage Technology, Inc.
S71175-02-000 5/01
526
23
2 Megabit LPC Flash SST49LF020
Advance Information
Addresses
Row
Column
R/C#
WE#
OE#
TOEP
DQ7
D
D#
D#
D
526 ILL F54.2
FIGURE 17: DATA# POLLING TIMING DIAGRAM (PP MODE)
Addresses
Row
Column
R/C#
WE#
OE#
TOET
DQ6
D
D
526 ILL F55.0
FIGURE 18: TOGGLE BIT TIMING DIAGRAM (PP MODE)
©2001 Silicon Storage Technology, Inc.
S71175-02-000 5/01
526
24
2 Megabit LPC Flash SST49LF020
Advance Information
Four-Byte Code for Byte-Program Addresses 5555 R/C# 2AAA 5555 BA
OE#
TWP
TBP
TWPH
WE# SB0
SB1
SB2
SB3
Internal Program Starts
DQ7-0
AA
55
A0
Data
BA = Byte-Program Address
526 ILL F51.0
FIGURE 19: BYTE-PROGRAM TIMING DIAGRAM (PP MODE)
Six-Byte code for Sector-Erase
Addresses 5555 R/C# 2AAA 5555 5555 2AAA SAx
OE#
TWP TSE TWPH
WE# SB0 DQ7-0 AA
SB1 55
SB2 80
SB3 AA
SB4 55
SB5 30
Internal Erase Starts
SAx = Sector Address
526 ILL F32.0
FIGURE 20: SECTOR-ERASE TIMING DIAGRAM (PP MODE)
©2001 Silicon Storage Technology, Inc.
S71175-02-000 5/01
526
25
2 Megabit LPC Flash SST49LF020
Advance Information
Six-Byte code for Block-Erase
Addresses 5555 R/C# 2AAA 5555 5555 2AAA BAx
OE#
TWP TBE TWPH
WE# SB0 DQ7-0 AA
SB1 55
SB2 80
SB3 AA
SB4 55
SB5 50
Internal Erase Starts
BAx = Block Address
526 ILL F48.0
FIGURE 21: BLOCK-ERASE TIMING DIAGRAM (PP MODE)
Six-Byte code for Chip-Erase
Addresses 5555 R/C# 2AAA 5555 5555 2AAA 5555
OE#
TWP TSCE TWPH
WE# SB0 DQ7-0 AA
SB1 55
SB2 80
SB3 AA
SB4 55
SB5 10
Internal Erase Starts
526 ILL F33.0
FIGURE 22: CHIP-ERASE TIMING DIAGRAM (PP MODE)
©2001 Silicon Storage Technology, Inc.
S71175-02-000 5/01
526
26
2 Megabit LPC Flash SST49LF020
Advance Information
Three-byte sequence for Software ID Entry Addresses 5555 2AAA 5555 0000 0001
R/C#
OE# TWP WE# TWPH DQ7-0 AA SW0 55 SW1 90 SW2 BFH 61H
526 ILL F34.3
TIDA TAA
FIGURE 23: SOFTWARE ID ENTRY
AND
READ (PP MODE)
Three-Byte Sequence for Software ID Exit and Reset
Addresses 5555 R/C# 2AAA 5555 TIDA
OE# TWP WE# T WHP SW0 DQ7-0 AA SW1 55 SW2 F0
526 ILL F35.1
FIGURE 24: SOFTWARE ID EXIT AND RESET (PP MODE)
©2001 Silicon Storage Technology, Inc.
S71175-02-000 5/01
526
27
2 Megabit LPC Flash SST49LF020
Advance Information
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
526 ILL F06.1
AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.4 VDD) and VOT (0.4 VDD). Input rise and fall times (10% 90%) are <3 ns.
Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test
FIGURE 25: AC INPUT/OUTPUT REFERENCE WAVEFORMS (PP MODE)
TO TESTER
TO DUT CL
526 ILL F07.0
FIGURE 26: A TEST LOAD EXAMPLE
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2 Megabit LPC Flash SST49LF020
Advance Information
Address: 5555H Write Data: AAH Cycle: 1
Read Command Sequence Address: AIN Read Data: DOUT Cycle: 1
Address: 2AAAH Write Data: 55H Cycle: 2
Address: 5555H Write Data: A0H Cycle: 3
Available for Next Command
526 ILL F40.0
Address: AIN Write Data: DIN Cycle: 4
Wait TBP
Available for Next Byte
526 ILL F41.1
FIGURE 27: READ COMMAND SEQUENCE (LPC MODE)
FIGURE 28: BYTE-PROGRAM ALGORITHM (LPC MODE)
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2 Megabit LPC Flash SST49LF020
Advance Information
Block-Erase Command Sequence Address: 5555H Write Data: AAH Cycle: 1
Sector-Erase Command Sequence Address: 5555H Write Data: AAH Cycle: 1
Address: 2AAAH Write Data: 55H Cycle: 2
Address: 2AAAH Write Data: 55H Cycle: 2
Address: 5555H Write Data: 80H Cycle: 3
Address: 5555H Write Data: 80H Cycle: 3
Address: 5555H Write Data: AAH Cycle: 4
Address: 5555H Write Data: AAH Cycle: 4
Address: 2AAAH Write Data: 55H Cycle: 5
Address: 2AAAH Write Data: 55H Cycle: 5
Address: BAX Write Data: 50H Cycle: 6
Address: SAX Write Data: 30H Cycle: 6
Wait TBE
Wait TSE
Block erased to FFH
Sector erased to FFH
Available for Next Command
Available for Next Command
526 ILL F43.1
FIGURE 29: ERASE COMMAND SEQUENCES (LPC MODE)
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2 Megabit LPC Flash SST49LF020
Advance Information
Software Product ID Entry Command Sequence Address: 5555H Write Data: AAH Cycle: 1
Software Product ID Exit & Reset Command Sequence Address: 5555H Write Data: AAH Cycle: 1 Address: XXXXH Write Data: F0H Cycle: 1
Address: 2AAAH Write Data: 55H Cycle: 2
Address: 2AAAH Write Data: 55H Cycle: 2
Wait TIDA
Address: 5555H Write Data: 90H Cycle: 3
Address: 5555H Write Data: F0H Cycle: 3
Available for Next Command
Wait TIDA
Wait TIDA
Address: 0001H Read Data: BFH Cycle: 4
Available for Next Command
526 ILL F44.1
Address: 0002H Read Data: Cycle: 5
Available for Next Command
FIGURE 30: SOFTWARE PRODUCT COMMAND FLOWCHARTS (LPC MODE)
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2 Megabit LPC Flash SST49LF020
Advance Information
Start
Write data: AAH Address: 5555H
Write data: 55H Address: 2AAAH
Write data: A0H Address: 5555H
Load Byte Address/Byte Data
Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed
526 ILL F36.1
FIGURE 31: BYTE-PROGRAM ALGORITHM (PP MODE)
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2 Megabit LPC Flash SST49LF020
Advance Information
Internal Timer ByteProgram/Erase Initiated
Toggle Bit ByteProgram/Erase Initiated
Data# Polling ByteProgram/Erase Initiated
Wait TBP, TSCE, TBE, or TSE
Read byte
Read DQ7
Program/Erase Completed
Read same byte
No
Is DQ7 = true data? Yes
No
Does DQ6 match? Yes
Program/Erase Completed
Program/Erase Completed
526 ILL F37.0
FIGURE 32: WAIT OPTIONS (PP MODE)
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2 Megabit LPC Flash SST49LF020
Advance Information
Software Product ID Entry Command Sequence
Software Product ID Exit & Reset Command Sequence
Write data: AAH Address: 5555H
Write data: AAH Address: 5555H
Write data: F0H Address: XXH
Write data: 55H Address: 2AAAH
Write data: 55H Address: 2AAAH
Wait TIDA
Write data: 90H Address: 5555H
Write data: F0H Address: 5555H
Return to normal operation
Wait TIDA
Wait TIDA
Read Software ID
Return to normal operation
526 ILL F38.1
FIGURE 33: SOFTWARE PRODUCT COMMAND FLOWCHARTS (PP MODE)
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2 Megabit LPC Flash SST49LF020
Advance Information
Chip-Erase Command Sequence Write data: AAH Address: 5555H
Block-Erase Command Sequence Write data: AAH Address: 5555H
Sector-Erase Command Sequence Write data: AAH Address: 5555H
Write data: 55H Address: 2AAAH
Write data: 55H Address: 2AAAH
Write data: 55H Address: 2AAAH
Write data: 80H Address: 5555H
Write data: 80H Address: 5555H
Write data: 80H Address: 5555H
Write data: AAH Address: 5555H
Write data: AAH Address: 5555H
Write data: AAH Address: 5555H
Write data: 55H Address: 2AAAH
Write data: 55H Address: 2AAAH
Write data: 55H Address: 2AAAH
Write data: 10H Address: 5555H
Write data: 50H Address: BAX
Write data: 30H Address: SAX
Wait TSCE
Wait TBE
Wait TSE
Chip erased to FFH
Block erased to FFH
Sector erased to FFH
526 ILL F39.1
FIGURE 34: ERASE COMMAND SEQUENCE (PP MODE)
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2 Megabit LPC Flash SST49LF020
Advance Information
PRODUCT ORDERING INFORMATION
Device SST49LF0x0 Speed - XXX Suffix1 XX Suffix2 XX Package Modifier H = 32 pins Package Type N = PLCC W = TSOP (die up) (8mm x 14mm) Operating Temperature C = Commercial = 0°C to +85°C Minimum Endurance 4 = 10,000 cycles Serial Access Clock Frequency 33 = 33 MHz Device Density 020 = 2 Mbit Voltage Range L = 3.0-3.6V Device Family
SST49LF020 Valid combinations SST49LF020-33-4C-WH
Example:
SST49LF020-33-4C-NH
Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
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2 Megabit LPC Flash SST49LF020
Advance Information
PACKAGING DIAGRAMS
TOP VIEW
.485 .495 .447 .453 .042 .048
2 1 32
SIDE VIEW
.106 .112 .020 R. MAX. .023 x 30° .029 .030 R. .040
BOTTOM VIEW
Optional Pin #1 Identifier
.042 .048 .585 .595 .547 .553 .026 .032
.013 .021 .400 BSC
.490 .530
.050 BSC. .015 Min. .050 BSC. .125 .140 .075 .095 .026 .032
Note:
1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 32.PLCC.NH-ILL.2 4. Coplanarity: 4 mils.
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH
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2 Megabit LPC Flash SST49LF020
Advance Information
Pin # 1 Identifier
1.05 0.95 .50 BSC
8.10 7.90
.270 .170
12.50 12.30
0.15 0.05
0.70 0.50
14.20 13.80
32.TSOP-WH-ILL.4
Note:
1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM SST PACKAGE CODE: WH
X
14MM
Silicon Storage Technology, Inc. · 1171 Sonora Court · Sunnyvale, CA 94086 · Telephone 408-735-9110 · Fax 408-735-9036 www.SuperFlash.com or www.ssti.com
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