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INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:
· The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC · The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

HEF4516B MSI Binary up/down counter
Product specification File under Integrated Circuits, IC04 January 1995

Philips Semiconductors

Product specification

Binary up/down counter
DESCRIPTION The HEF4516B is an edge-triggered synchronous up/down 4-bit binary counter with a clock input (CP), an up/down count control input (UP/DN), an active LOW count enable input (CE), an asynchronous active HIGH parallel load input (PL), four parallel inputs (P0 to P3), four parallel outputs (O0 to O3), an active LOW terminal count output (TC), and an overriding asynchronous master reset input (MR).

HEF4516B MSI
Information on P0 to P3 is loaded into the counter while PL is HIGH, independent of all other input conditions except MR which must be LOW. When PL and CE are LOW, the counter changes on the LOW to HIGH transition of CP. Input UP/DN determines the direction of the count, HIGH for counting up, LOW for counting down. When counting up, TC is LOW when O0 and O3 are HIGH and CE is LOW. When counting down, TC is LOW when O0 to O3 and CE are LOW. A HIGH on MR resets the counter (O0 to O3 = LOW) independent of all other input conditions.

Fig.2 Pinning diagram.

HEF4516BP(N): HEF4516BD(F): HEF4516BT(D):

16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1)

( ): Package Designator North America Fig.1 Functional diagram.

PINNING PL P0 to P3 CE CP UP/DN MR TC O0 to O3 parallel load input (active HIGH) parallel inputs count enable input (active LOW) clock pulse input (LOW to HIGH, edge triggered) up/down count control input master reset input terminal count output (active LOW) parallel outputs

FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 2

Philips Semiconductors

Product specification

Binary up/down counter

HEF4516B MSI

Fig.3 Logic diagram (continued in Fig.4).

January 1995

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Philips Semiconductors

Product specification

Binary up/down counter

HEF4516B MSI

Fig.4 Logic diagram (continued from Fig.3).

January 1995

4

Philips Semiconductors

Product specification

Binary up/down counter
FUNCTION TABLE MR L L L L H Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition PL H L L L X UP/DN X X L H X CE X H L L X X CP X X MODE parallel load no change count down count up reset

HEF4516B MSI

Fig.5 State diagram.

Logic equation for terminal count: TC = CE { ( UP/DN ) O 0 O 1 O 2 O 3 + UP/DN O 0 O 1 O 2 O 3 }

AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; input transition times 20 ns VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (µW) 1000 fi + (foCL) × VDD2 4500 fi + (foCL) × VDD2 11 200 fi + (foCL) × VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V)

January 1995

5

Philips Semiconductors

Product specification

Binary up/down counter
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays CP On HIGH to LOW 5 10 15 5 LOW to HIGH CP TC HIGH to LOW 10 15 5 10 15 5 LOW to HIGH PL On HIGH to LOW 10 15 5 10 15 5 LOW to HIGH PL TC HIGH to LOW 10 15 5 10 15 5 LOW to HIGH CE TC HIGH to LOW 10 15 5 10 15 5 LOW to HIGH MR On, TC HIGH to LOW MR TC LOW to HIGH 10 15 5 10 15 5 10 15 tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL 145 60 45 155 65 45 260 105 75 180 75 55 125 55 40 170 70 50 250 110 80 250 110 80 165 65 50 145 60 45 205 65 45 225 75 50 290 ns 120 ns 90 ns 310 ns 130 ns 90 ns 525 ns 210 ns 150 ns 360 ns 150 ns 115 ns 255 ns 110 ns 85 ns 340 ns 140 ns 105 ns 500 ns 220 ns 160 ns 500 ns 220 ns 160 ns 330 ns 135 ns 100 ns 290 ns 125 ns 95 ns 405 ns 130 ns 85 ns 450 ns 150 ns 100 ns SYMBOL MIN. TYP. MAX.

HEF4516B MSI

TYPICAL EXTRAPOLATION FORMULA 118 ns + (0,55 ns/pF) CL 49 ns + (0,23 ns/pF) CL 37 ns + (0,16 ns/pF) CL 128 ns + (0,55 ns/pF) CL 54 ns + (0,23 ns/pF) CL 37 ns + (0,16 ns/pF) CL 233 ns + (0,55 ns/pF) CL 94 ns + (0,23 ns/pF) CL 67 ns + (0,16 ns/pF) CL 153 ns + (0,55 ns/pF) CL 64 ns + (0,23 ns/pF) CL 47 ns + (0,16 ns/pF) CL 98 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 143 ns + (0,55 ns/pF) CL 59 ns + (0,23 ns/pF) CL 42 ns + (0,16 ns/pF) CL 223 ns + (0,55 ns/pF) CL 99 ns + (0,23 ns/pF) CL 72 ns + (0,16 ns/pF) CL 223 ns + (0,55 ns/pF) CL 99 ns + (0,23 ns/pF) CL 72 ns + (0,16 ns/pF) CL 138 ns + (0,55 ns/pF) CL 54 ns + (0,23 ns/pF) CL 42 ns + (0,16 ns/pF) CL 118 ns + (0,55 ns/pF) CL 49 ns + (0,23 ns/pF) CL 37 ns + (0,16 ns/pF) CL 178 ns + (0,55 ns/pF) CL 54 ns + (0,23 ns/pF) CL 37 ns + (0,16 ns/pF) CL 198 ns + (0,55 ns/pF) CL 64 ns + (0,23 ns/pF) CL 42 ns + (0,16 ns/pF) CL

January 1995

6

Philips Semiconductors

Product specification

Binary up/down counter
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns VDD V Output transition times HIGH to LOW 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL SYMBOL MIN. TYP. 60 30 20 60 30 20 MAX. 120 ns 60 ns 40 ns 120 ns 60 ns 40 ns

HEF4516B MSI

TYPICAL EXTRAPOLATION FORMULA 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL

January 1995

7

Philips Semiconductors

Product specification

Binary up/down counter

HEF4516B MSI
TYPICAL EXTRAPOLATION FORMULA ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz see also waveforms Figs 6 and 7

VDD V Minimum clock pulse width; LOW Minimum PL pulse width; HIGH Minimum MR pulse width; HIGH Recovery time for MR Recovery time for PL Set-up times Pn PL 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 UP/DN CP 10 15 5 CE CP Hold times Pn PL 10 15 5 10 15 5 UP/DN CP 10 15 5 CE CP Maximum clock pulse frequency 10 15 5 10 15

SYMBOL

MIN. 95

TYP. 45 20 15 55 25 15 60 25 20 65 20 15 75 25 15 50 25 20 125 50 35 60 20 10 -40 -20 -20 -90 -35 -25 -40 -15 -10 6 14 18

MAX.

tWCPL

35 25 105

tWPLH

45 35 120

tWMRH

50 40 130

tRMR

45 30 150

tRPL

50 30 100

tsu

50 40 250

tsu

100 75 120

tsu

40 25 10

thold

5 0 35

thold

15 15 20

thold

5 5 3

fmax

7 9

January 1995

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Philips Semiconductors

Product specification

Binary up/down counter

HEF4516B MSI

Fig.6

Waveforms showing minimum pulse width for CP, set-up and hold times for CE to CP and UP/DN to CP.

Fig.7

Waveforms showing minimum pulse width for PL and MR, recovery time for PL and MR and set-up and hold times for Pn to PL.

January 1995

9

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Binary up/down counter HEF4516B MSI