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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: · The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC · The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4516B MSI Binary up/down counter Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Binary up/down counter DESCRIPTION The HEF4516B is an edge-triggered synchronous up/down 4-bit binary counter with a clock input (CP), an up/down count control input (UP/DN), an active LOW count enable input (CE), an asynchronous active HIGH parallel load input (PL), four parallel inputs (P0 to P3), four parallel outputs (O0 to O3), an active LOW terminal count output (TC), and an overriding asynchronous master reset input (MR). HEF4516B MSI Information on P0 to P3 is loaded into the counter while PL is HIGH, independent of all other input conditions except MR which must be LOW. When PL and CE are LOW, the counter changes on the LOW to HIGH transition of CP. Input UP/DN determines the direction of the count, HIGH for counting up, LOW for counting down. When counting up, TC is LOW when O0 and O3 are HIGH and CE is LOW. When counting down, TC is LOW when O0 to O3 and CE are LOW. A HIGH on MR resets the counter (O0 to O3 = LOW) independent of all other input conditions. Fig.2 Pinning diagram. HEF4516BP(N): HEF4516BD(F): HEF4516BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America Fig.1 Functional diagram. PINNING PL P0 to P3 CE CP UP/DN MR TC O0 to O3 parallel load input (active HIGH) parallel inputs count enable input (active LOW) clock pulse input (LOW to HIGH, edge triggered) up/down count control input master reset input terminal count output (active LOW) parallel outputs FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 2 Philips Semiconductors Product specification Binary up/down counter HEF4516B MSI Fig.3 Logic diagram (continued in Fig.4). January 1995 3 Philips Semiconductors Product specification Binary up/down counter HEF4516B MSI Fig.4 Logic diagram (continued from Fig.3). January 1995 4 Philips Semiconductors Product specification Binary up/down counter FUNCTION TABLE MR L L L L H Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition PL H L L L X UP/DN X X L H X CE X H L L X X CP X X MODE parallel load no change count down count up reset HEF4516B MSI Fig.5 State diagram. Logic equation for terminal count: TC = CE { ( UP/DN ) O 0 O 1 O 2 O 3 + UP/DN O 0 O 1 O 2 O 3 } AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; input transition times 20 ns VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (µW) 1000 fi + (foCL) Ч VDD2 4500 fi + (foCL) Ч VDD2 11 200 fi + (foCL) Ч VDD2 where fi = input freq. (MHz) fo