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CD4518BMS, CD4520BMS
December 1992
CMOS Dual Up Counters
Pinout
CD4518BMS, CD4520BMS TOP VIEW
Features
· High Voltage Types (20V Rating) · CD4518BMS Dual BCD Up Counter · CD4520BMS Dual Binary Up Counter · Medium Speed Operation - 6MHz Typical Clock Frequency at 10V · Positive or Negative Edge Triggering · Synchronous Internal Carry Propagation · 100% Tested for Quiescent Current at 20V · 5V, 10V and 15V Parametric Ratings · Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC · Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V · Standardized Symmetrical Output Characteristics · Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices"
CLOCK A ENABLE A Q1A Q2A Q3A Q4A RESET A VSS
1 2 3 4 5 6 7 8
16 VDD 15 RESET B 14 Q4B 13 Q3B 12 Q2B 11 Q1B 10 ENABLE B 9 CLOCK B
Functional Diagram
Applications
3
· Multistage Synchronous Counting · Multistage Ripple Counting · Frequency Dividers
CLOCK A 1 ENABLE A 2 C
÷10/÷16
Q1A Q2A Q3A Q4A
4 5 6
Description
CD4518BMS Dual BCD Up Counter and CD4520BMS Dual Binary Up Counter each consist of two identical, internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or negative-going transition. For single unit operation the ENABLE input is maintained high and the counter advances on each positive-going transition of the CLOCK. The counters are cleared by high levels on their RESET lines. The counter can be cascaded in the ripple mode by connecting Q4 to the enable input of the subsequent counter while the CLOCK input of the latter is held low. The CD4518BMS and CD4520BMS are supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack *CD4518B Only H4S H1F *H6P H6W CD4520B Only
RESET A 7
R
11 CLOCK B 9 ENABLE B 10 C
÷10/÷16
Q1B 12 13 14 Q2B Q3B Q4B
R RESET B 15
VSS = 8 VDD = 16
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3342
7-1206
Specifications CD4518BMS, CD4520BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 +25oC, +25oC, LIMITS TEMPERATURE +25oC +125oC -55oC +25oC +125oC -55oC +25oC +125oC -55oC +125oC, +125oC, +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC 3.5 11 1.5 4 V V V V -55oC -55oC MIN -100 -1000 -100 14.95 0.53 1.4 3.5 -2.8 0.7 MAX 10 1000 10 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8 UNITS µA µA µA nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V
PARAMETER Supply Current
SYMBOL IDD
CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND
VOH > VOL < VDD/2 VDD/2
NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.
7-1207
Specifications CD4518BMS, CD4520BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 TTHL TTLH FCL VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25 C +125oC, -55oC
o
LIMITS MIN 1.5 1.11 MAX 560 756 650 878 200 270 UNITS ns ns ns ns ns ns MHz MHz
PARAMETER Propagation Delay Clock to Output Propagation Delay Reset to Ouput Transition Time (Note 2) Maximum Clock Input Frequency NOTES:
SYMBOL TPHL1 TPLH1 TPHL2
CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) Input Voltage Low Input Voltage High VOL VOL VOH VOH IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VIL VIH VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD =15V, VOUT = 13.5V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V NOTES 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 TEMPERATURE -55oC, +25oC +125 C -55oC, +25oC +125oC -55 C, +25 C +125oC +25 C, +125 C, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC
o o o o o
MIN 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 +7
MAX 5 150 10 300 10 600 50 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 -4.2 3 -
UNITS µA µA µA µA µA µA mV mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V
7-1208
Specifications CD4518BMS, CD4520BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Propagation Delay Clock to Output Propagation Delay Reset to Output Transition Time Maximum Clock Input Frequency Maximum Clock Rise and Fall Time SYMBOL TPHL1 TPLH1 TPHL2 TTHL TTLH FCL TRCL TFCL CONDITIONS VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V Minimum Enable Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Minimum Reset Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Minimum Clock Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH VTN VTP VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10µA VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC +25
oC
NOTES 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2
TEMPERATURE +25oC +25 C +25oC +25 C +25oC +25oC +25 C +25oC +25oC +25 C +25oC +25 C +25oC +25oC +25 C +25oC +25oC +25 C +25oC +25 C +25oC
o o o o o o o o
MIN 3 4 -
MAX 230 160 225 170 100 80 15 5 5 400 200 140 250 110 80 200 100 70 7.5
UNITS ns ns ns ns ns ns MHz MHz µs µs µs ns ns ns ns ns ns ns ns ns pF
CIN
Any Input
MIN -2.8 0.2 VOH > VDD/2 -
MAX 25 -0.2 ±1 2.8 ±1 VOL < VDD/2 1.35 x +25oC Limit
UNITS µA V V V V V
+25oC
ns
NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25oC limit. 4. Read and Record
7-1209
Specifications CD4518BMS, CD4520BMS
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A ± 1.0µA ± 20% x Pre-Test Reading ± 20% x Pre-Test Reading DELTA LIMIT
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4
CONFORMANCE GROUPS Group E Subgroup 2
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V OPEN 3-6, 11-14 3-6, 11-14 3-6, 11-14 GROUND 1, 2, 7-10, 15 8 7, 8, 15 8 VDD 16 1, 2, 7, 9, 10, 15, 16 2, 10, 16 1, 2, 7, 9, 10, 15, 16 3-6, 11-14 1, 9 9V ± -0.5V 50kHz 25kHz
7-1210
CD4518BMS, CD4520BMS Logic Diagrams
VDD Q1 3/11 Q2 4/12 Q3 5/13 Q4 6/14
VSS
*
ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK RESET 7/15
D Q C Q R
D Q C Q R
D Q C Q R
D Q C Q R
*
ENABLE 2/10 CLOCK 1/9
* *
FIGURE 1. DECADE COUNTER (CD4518BMS) LOGIC DIAGRAM FOR ONE OF TWO IDENTICAL COUNTERS
VDD Q1 3/11 Q2 4/12 Q3 5/13 Q4 6/14
VSS
*
ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK RESET 7/15
D Q C Q R
D Q C Q R
D Q C Q R
D Q C Q R
*
ENABLE 2/10 CLOCK 1/9
*
*
FIGURE 2. BINARY COUNTER (CD4520BMS) LOGIC DIAGRAM FOR ONE OF TWO IDENTICAL COUNTERS
TRUTH TABLE CLOCK ENABLE 1 0 X X 0 1 X X = Don't Care X 1 High State RESET 0 0 0 0 0 0 1 0 Low State ACTION Increment Counter Increment Counter No Change No Change No Change No Change Q1 thru Q4 = 0
7-1211
CD4518BMS, CD4520BMS Typical Performance Curves
OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC
30 25 20 15 10 5
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V
10V
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
5V 0 5 10 15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0
FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 0
0 -5 -10 -15
0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
-10V
-20 -25
-10V
-10
-15V
-30
-15V
-15
FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
PROPAGATION DELAY TIME (tPLH, tPHL) (ns) 350 AMBIENT TEMPERATURE (TA) = +25oC 300 250 200 150 100 15V 50 0 10 20 30 40 50 60 70 80 LOAD CAPACITANCE (CL) (pF) 90 100 SUPPLY VOLTAGE (VDD) = 5V
FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
PROPAGATION DELAY TIME (tPHL, tPLH) (ns) 350 300 SUPPLY VOLTAGE (VDD) = 5V 250 200 150 100 15V 50 0 10 AMBIENT TEMPERATURE (TA) = +25oC
10V
10V
20
30
40 50 60 70 80 90 LOAD CAPACITANCE (CL) (pF)
100
110
FIGURE 7. TYPICAL PROPAGATION DELAY vs LOAD CAPACITANCE, CLOCK OR ENABLE TO OUTPUT
FIGURE 8. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE, RESET TO OUTPUT
7-1212
CD4518BMS, CD4520BMS Typical Performance Curves
AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns) MAXIMUM CLOCK FREQUENCY (fCL MAX) (MHz) AMBIENT TEMPERATURE (TA) = +25oC LOAD CAPACITANCE (CL) = 50PF
15
200 SUPPLY VOLTAGE (VDD) = 5V
10
150
100 10V 50 15V
5
0 0
20
40 60 80 100 LOAD CAPACITANCE (CL) (pF)
0
5
10 15 SUPPLY VOLTAGE (VDD) (V)
20
FIGURE 9. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE
POWER DISSIPATION /CONVERTER (PD) (µW)
FIGURE 10. TYPICAL MAXIMUM CLOCK FREQUENCY vs SUPPLY VOLTAGE
104 8
6 4 SUPPLY VOLTAGE (VDD) = 15V 2
103 8
6 4 2
102 8
6 4 2
10V 10V 5V CL = 50pF
10 8
6 4 2
CL = 15pF AMBIENT TEMPERATURE (TA) = +25oC
2 4 68 2 4 68 2 4 68 2 4 68 2 4 68
1 0.1 1
10
102
103
104
FREQUENCY (f) (kHz)
FIGURE 11. TYPICAL POWER DISSIPATION CHARACTERISTICS
Timing Diagrams
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
CLOCK ENABLE RESET
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0
Q1 CD4518BMS Q2 Q3 Q4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
Q1 CD4520BMS Q2 Q3 Q4 FIGURE 12. TIMING DIAGRAMS FOR CD4518BMS AND CD4520BMS
7-1213
CD4518BMS, CD4520BMS
CLOCK INPUT VDD 1 2 7 9 10 15 1 2 7 9 10 15
CLOCK ENABLE RESET A A A Q1A Q2A Q3A Q4A 3 4 5 6
CLOCK ENABLE RESET B B B Q1B Q2B Q3B Q4B 11 12 13 14
CLOCK ENABLE RESET A A A Q1A Q2A Q3A Q4A 3 4 5 6
CLOCK ENABLE RESET B B B Q1B Q2B Q3B Q4B 11 12 13 14
CD4518BMS/20BMS
CD4518BMS/20BMS
FIGURE 13. RIPPLE CASCADING OF FOUR COUNTERS WITH POSITIVE EDGE TRIGGERING
CLOCK* INPUT
CD4071
CD4071
1
2
3
9
10
15
1
2
3
9
10
15
CLOCK ENABLE RESET A A A Q1A Q2A Q3A Q4A 3 4 5 6 CD4520BMS CD4012A
CLOCK ENABLE RESET B B B Q1B Q2B Q3B Q4B 11 12 13 14
CLOCK ENABLE RESET A A A Q1A Q2A Q3A Q4A 3 4 5 6 CD4520BMS
CLOCK ENABLE RESET B B B Q1B Q2B Q3B Q4B 11 12 13 14
CD4012A
CD4012A CD4520BMS
* For synchronous cascading, the clock transition time should be made less than or equal to the sum of the fixed propagation delay at 15pF and the transition time of the output driver stage for the estimated capacitive load. FIGURE 14. SYNCHRONOUS CASCADING OF FOUR BINARY COUNTERS WITH NEGATIVE EDGE TRIGGERING
7-1214
CD4518BMS, CD4520BMS Chip Dimensions and Pad Layouts
CD4518BMS
Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch).
CD4520BMS
METALLIZATION: PASSIVATION:
Thickness: 11kÅ - 14kÅ,
AL.
10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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