Intersil 4518 free download

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CD4518BMS, CD4520BMS December 1992 CMOS Dual Up Counters Pinout CD4518BMS, CD4520BMS TOP VIEW Features · High Voltage Types (20V Rating) · CD4518BMS Dual BCD Up Counter · CD4520BMS Dual Binary Up Counter · Medium Speed Operation - 6MHz Typical Clock Frequency at 10V · Positive or Negative Edge Triggering · Synchronous Internal Carry Propagation · 100% Tested for Quiescent Current at 20V · 5V, 10V and 15V Parametric Ratings · Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC · Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V · Standardized Symmetrical Output Characteristics · Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices" CLOCK A ENABLE A Q1A Q2A Q3A Q4A RESET A VSS 1 2 3 4 5 6 7 8 16 VDD 15 RESET B 14 Q4B 13 Q3B 12 Q2B 11 Q1B 10 ENABLE B 9 CLOCK B Functional Diagram Applications 3 · Multistage Synchronous Counting · Multistage Ripple Counting · Frequency Dividers CLOCK A 1 ENABLE A 2 C ч10/ч16 Q1A Q2A Q3A Q4A 4 5 6 Description CD4518BMS Dual BCD Up Counter and CD4520BMS Dual Binary Up Counter each consist of two identical, internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or negative-going transition. For single unit operation the ENABLE input is maintained high and the counter advances on each positive-going transition of the CLOCK. The counters are cleared by high levels on their RESET lines. The counter can be cascaded in the ripple mode by connecting Q4 to the enable input of the subsequent counter while the CLOCK input of the latter is held low. The CD4518BMS and CD4520BMS are supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack *CD4518B Only H4S H1F *H6P H6W CD4520B Only RESET A 7 R 11 CLOCK B 9 ENABLE B 10 C ч10/ч16 Q1B 12 13 14 Q2B Q3B Q4B R RESET B 15 VSS = 8 VDD = 16 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 File Number 3342 7-1206 Specifications CD4518BMS, CD4520BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance . . . . . . . . . . . . .