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CD4076BMS December 1992 CMOS 4 -Bit D-Type Registers Pinout CD4076BMS TOP VIEW M N Q1 Q2 Q3 Q4 CLOCK VSS 1 2 3 4 5 6 7 8 16 VDD 15 RESET 14 DATA 1 13 DATA 2 12 DATA 3 11 DATA 4 10 G2 9 G1 DATA INPUT DISABLE Features · High Voltage Type (20V Rating) · Three State Outputs · Input Disabled Without Gating the Clock · Gated Output Control Lines for Enabling or Disabling the Outputs · Standardized Symmetrical Output Characteristics · 100% Tested for Quiescent Current at 20V · Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC · Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V · 5V, 10V and 15V Parametric Ratings · Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices" OUTPUT DISABLE Functional Diagram DATA INPUT DISABLE G1 9 14 D1 13 D2 12 4D - TYPE FLIP-FLOPS WITH AND-OR LOGIC 4 Q2 5 10 G2 CLOCK 7 1 OUTPUT DISABLE M 2 3 Q1 N Description CD4076BMS types are four-bit registers consisting of D-type flip-flops that feature three-state outputs. Data Disable inputs are provided to control the entry of data into the flip-flops. When both Data Disable inputs are low, data at the D inputs are loaded into their respective flip-flops on the next positive transition of the clock input. Output Disable inputs are also provided. When the Output Disable inputs are both low, the normal logic states of the four outputs are available to the load. The outputs are disabled independently of the clock by a high logic level at either Output Disable input, and present a high impedance. The CD4076BMS is supplied in these 16 lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4T H1E H6W D3 Q3 11 D4 15 RESET 6 Q4 VSS = 8 VDD = 16 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 File Number 3325 7-1029 Specifications CD4076BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA