Intersil 40182 free download

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CD40182BMS December 1992 CMOS Look-Ahead Carry Generator Description The CD40182BMS is a high-speed look-ahead carry generator capable of anticipating a carry across four binary adders or groups of adders. The CD40182BMS is cascadable to perform full look-ahead across n-bit adders. Carry, propagate-carry, and generate-carry functions are provided as enumerated in the terminal designation below. The CD40182BMS, when used in conjuction with the CD40181BMS arithmetic logic unit (ALU), provides full highspeed look-ahead carry capability for up to n-bit words. Each CD40182BMS generates the look-ahead (anticipated carry) across a group of four ALU's. In addition, other CD40182BMS's may be employed to anticipate the carry across sections of four look-ahead blocks up to n-bits. Carry inputs and outputs of the CD40181BMS are active-high logic, and carry-generate (G) and carry-propagate (P) outputs are active-low. Therefore the inputs and outputs of the CD40182BMS are compatible. The CD40182BMS is supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4V H1E H6P Features · High Voltage Type (20V Rating) · Generates High-Speed Carry Across Four Adders or Adder Groups · High-Speed Operation - tPHL, tPLH =100 ns (typ) at VDD = 10V · Cascadable for Fast Carries Over N Bits · Designed for Use with CD40181BMS ALU · 100% Tested for Quiescent Current at 20V · 5V, 10V and 15V Parametric Ratings · Standardized Symmetrical Output Characteristics · Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC · Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V · Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices" The CD40182BMS is similar to industry type MC14582. Applications · High-Speed Parallel Arithmetric Units · Multi-Level Look-Ahead Carry Generation for Long Word Lengths Pinout CD40182BMS TOP VIEW Functional Diagram G1 1 P1 2 G0 3 P0 4 G3 5 P3 6 P 7 VSS 8 16 VDD 15 P2 14 G2 13 Cn 12 Cn + x 11 Cn + y 10 G 9 Cn + z VDD = 16 VSS = 8 G 3 G0 1 G1 14 G2 5 G3 4 P0 2 P1 15 P2 6 P3 Cn 13 12 11 9 Cn + x Cn + y Cn + z P 7 P 10 G CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 File Number 3362 7-1410 Specifications CD40182BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . .