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CD4555BMS CD4556BMS December 1992 CMOS Dual Binary to 1 of 4 Decoder/Demultiplexers Pinouts E A B 1 2 3 4 5 6 7 8 Features · High Voltage Type (20V Rating) · CD4555BMS: Outputs High on Select · CD4556BMS: Outputs Low on Select · Expandable with Multiple Packages CD4556BMS TOP VIEW 16 VDD 15 E 14 A 13 B 12 Q0 11 Q1 10 Q2 9 Q3 1/2 OF DUAL 1/2 OF DUAL Q0 Q1 Q2 Q3 VSS · 100% Tested for Quiescent Current at 20V · Standardized, Symmetrical Output Characteristics · Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC · Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V · 5V, 10V and 15V Parametric Ratings · Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices" 1/2 OF DUAL CD4555BMS TOP VIEW E A B Q0 Q1 Q2 Q3 VSS 1 2 3 4 5 6 7 8 16 VDD 15 E 14 A 13 B 12 Q0 11 Q1 10 Q2 9 Q3 1/2 OF DUAL Applications · Decoding · Code Conversion · Demultiplexing (Using Enable Input as a Data Input · Memory Chip-Enable Selection · Function Selection Functional Diagrams VDD A B E 2 3 1 16 4 5 6 7 12 11 10 9 VSS 8 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Description CD4555BMS and CD4556BMS are dual one-of-four decoders/demultiplexers. Each decoder has two select inputs (A and B), an Enable input (E), and four mutually exclusive outputs. On the CD4555BMS the outputs are high on select; on the CD4556BMS the outputs are low on select. When the Enable input is high, the outputs of the CD4555BMS remain low and the outputs of the CD4556BMS remain high regardless of the state of the select inputs A and B. The CD4555BMS and CD4556BMS are similar to types MC14555 and MC14556, respectively. The CD4555BMS and CD4556BMS are supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack *CD4555B Only *H46 H4T H1E H6W CD4556B Only A B E 14 13 15 CD4555BMS VDD A B E 2 3 1 16 4 5 6 7 12 11 10 9 VSS 8 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 A B E 14 13 15 CD4556BMS CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 File Number 3346 7-1249 Specifications CD4555BMS, CD4556BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Packa