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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MC14531B 12-Bit Parity Tree
The MC14531B 12ґbit parity tree is constructed with MOS Pґchannel and Nґchannel enhancement mode devices in a single monolithic structure. The circuit consists of 12 dataґbit inputs (D0 thru D11), and even or odd parity selection input (W) and an output (Q). The parity selection input can be considered as an additional bit. Words of less than 13 bits can generate an even or odd parity output if the remaining inputs are selected to contain an even or odd number of ones, respectively. Words of greater than 12ґbits can be accommodated by cascading other MC14531B devices by using the W input. Applications include checking or including a redundant (parity) bit to a word for error detection/correction systems, controller for remote digital sensors or switches (digital event detection/correction), or as a multiple input summer without carries. Ї Supply Voltage Range = 3.0 Vdc to 18 Vdc Ї All Outputs Buffered Ї Capable of Driving Two LowґPower TTL Loads or One LowґPower Schottky TTL Load Over the Rated Temperature Range Ї Variable Word Length Ї Diode Protection on All Inputs MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter VDD Vin, Vout Iin, Iout PD Tstg TL DC Supply Voltage L SUFFIX CERAMIC CASE 620

P SUFFIX PLASTIC CASE 648

D SUFFIX SOIC CASE 751B

ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC

ннннннннннннннннннннн н н н ннн н н н ннннннннннннннннннннн н н н ннннннннннннннннннннн н н н ннн н н н ннннннннннннннннннннн н н н ннннннннннннннннннннн н н н ннннннннннннннннннннн н н н ннннннннннннннннннннн н н н ннннннннннннннннннннн н н н ннннннннннннннннннннн ннннннннннннннннннн н н ннннннннннннннннннннн н н н ннннннннннннннннннннн н н н ннннннннннннннннннннн н н н ннннннннннннннннннннн н н н ннннннннннннннннннннн н н н ннннннннннннннннннннн н н н нннннннн н н н ннннннннннннннннннннн н н н ннннннннннннннннннннн н н н ннннннннннннннннннннн н н н ннннннннннннннннннннн ннннннннннннннннннннн н н н н н ннн н н н ннннннннннннннннннннн ннннннннннннннннннн нннннннннннннн н ннннннннннннннннннннн ннннннннннннннннннннн ннннннннннннннннннн н н н ннн н н ннннннннннннннннннннн ннннннннннннннннннннн ннннннннннннннннннн н ннннннннннннннннннннн н н ннннннннннннннннннннн
Value Unit V V ґ 0.5 to + 18.0 ╠ 10 500 Input or Output Voltage (DC or Transient) ґ 0.5 to VDD + 0.5 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature mA mW ґ 65 to + 150 260

TA = ґ 55╟ to 125╟C for all packages.

_C _C

Lead Temperature (8ґSecond Soldering)

* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: ґ 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: ґ 12 mW/_C From 100_C To 125_C

TRUTH TABLE
Inputs Decimal (Octal) Equivalent 0 1 2 3 4 5 6 7 * * * 8184 (17770) 8185 (17771) 8186 (17772) 8187 (17773) 8188 (17774) 8189 (17775) 8190 (17776) 8191 (17777) (0) (1) (2) (3) (4) (5) (6) (7) Output

W 0 0 0 0 0 0 0 0 * * *

D11 0 0 0 0 0 0 0 0 * * * 1 1 1 1 1 1 1 1

D10 0 0 0 0 0 0 0 0 * * * 1. 1 1 1 1 1 1 1

... ... ... ... ... ... ... ... ... * ... * ... ... ... ... ... ... ... ...

D2 0 0 0 0 1 1 1 1 * * * 0 0 0 0 1 1 1 1

D1 0 0 1 1 0 0 1 1 * * * 0 0 1 1 0 0 1 1

D0 0 1 0 1 0 1 0 1 * * * 0 1 0 1 0 1 0 1

Q* 0 1 1 0 1 0 0 1 * * * 0 1 1 0 1 0 0 1

LOGIC DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 ODD/EVEN W 7 6 5 4 3 2 1 15 14 13 12 11 10 Q = D0 VDD = PIN 16 VSS = PIN 8 9 Q

1 1 1 1 1 1 1 1

D1 D2 @@@@ D11 W

*0 = Even Parity 1 = Odd Parity NOTE: May redefine to suit application by manipulating W and/or other available D's.

REV 3 1/94

╘MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995

MC14531B 1

нннннннннннннннннннннннннннннннннн нннннннннннннннннннннннннннннннннн нннннннннннннннннннннннннннннннннн нннннннннннннннннннннннннннннннннн
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 ґ 3.0 ґ 0.64 ґ 1.6 ґ 4.2 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- ╠ 0.1 -- 5.0 10 20 ґ 2.4 ґ 0.51 ґ 1.3 ґ 3.4 0.51 1.3 3.4 -- -- -- -- -- ґ 4.2 ґ 0.88 ґ 2.25 ґ 8.8 0.88 2.25 8.8 ╠ 0.00001 5.0 0.005 0.010 0.015 -- -- -- -- -- -- -- ╠ 0.1 7.5 5.0 10 20 ґ 1.7 ґ 0.36 ґ 0.9 ґ 2.4 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- ╠ 1.0 -- 150 300 600 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc Min -- -- -- ґ 55_C 25_C 125_C Max Min -- -- -- Typ # 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Iin Cin IDD ╣Adc pF ╣Adc IT IT = (0.25 ╣A/kHz) f + IDD IT = (0.50 ╣A/kHz) f + IDD IT = (0.75 ╣A/kHz) f + IDD ╣Adc #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL ґ 50) Vfk where: IT is in ╣A (per package), CL in pF, V = (VDD ґ VSS) in volts, f in kHz is input frequency, and k = 0.001. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

PIN ASSIGNMENT
D6 D5 D4 D3 D2 D1 D0 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD D7 D8 D9 D10 D11 W Q

MC14531B 2

MOTOROLA CMOS LOGIC DATA

нннннннннннннннннннннннннннннннннн нннннннннннннннннннннннннннннннннн нннннннннннннннннннннннннннннннннн нннннннннннннннннннннннннннннннннн
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Output Rise and Fall Time tTLH, tTHL = (1.6 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Symbol tTLH, tTHL VDD 5.0 10 15 Min -- -- -- Typ # 100 50 40 Max 200 100 80 Unit ns Propagation Delay Time Data to Q tPLH, tPHL = (1.7 ns/pF) CL + 355 ns tPLH, tPHL = (0.66 ns/pF) CL + 142 ns tPLH, tPHL = (0.5 ns/pF) CL + 95 ns Odd/Even to Q tPLH, tPHL = (1.7 ns/pF) CL + 165 ns tPLH, tPHL = (0.66 ns/pF) CL + 67 ns tPLH, tPHL = (0.5 ns/pF) CL + 45 ns tPLH, tPHL 5.0 10 15 5.0 10 15 -- -- -- -- -- -- 440 175 120 250 100 70 1320 525 360 750 300 210 ns * The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 20 ns 90% SIGNAL INPUT 10% 50% VSS 20 ns VDD INPUT (D OR W) tPLH 90% OUTPUT 10% tTLH 20 ns 90% 50% 20 ns 10% VDD 1 DATA RATE (f) f IN RESPECT TO SYSTEM CLOCK VSS tPHL VOH 50% VOL tTHL

Figure 1. Dynamic Power Dissipation Signal Waveform

Figure 2. Dynamic Signal Waveforms

MOTOROLA CMOS LOGIC DATA

MC14531B 3

OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 620ґ10 ISSUE V
ґAґ
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 ґґґ 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ґґґ 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01

ґBґ
1 8

C

L

ґTґ
SEATING PLANE

N E F D G
16 PL

K M J
16 PL

0.25 (0.010)
M

M

T B

S

0.25 (0.010)

T A

S

P SUFFIX PLASTIC DIP PACKAGE CASE 648ґ08 ISSUE R
ґAґ
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01

B
1 8

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L

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SEATING PLANE

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0.25 (0.010)

M

MC14531B 4

MOTOROLA CMOS LOGIC DATA

OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751Bґ05 ISSUE J
ґAґ
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019

16

9

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1 8

P

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0.25 (0.010)

M

B

S

G F

K C ґTґ
SEATING PLANE

R

X 45 _

M D
16 PL M

J

0.25 (0.010)

T B

S

A

S

DIM A B C D F G J K M P R

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MOTOROLA CMOS LOGIC DATA

*MC14531B/D*

MC14531B MC14531B/D 5