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CD4555BMS CD4556BMS
December 1992

CMOS Dual Binary to 1 of 4 Decoder/Demultiplexers
Pinouts
E A B 1 2 3 4 5 6 7 8

Features
· High Voltage Type (20V Rating) · CD4555BMS: Outputs High on Select · CD4556BMS: Outputs Low on Select · Expandable with Multiple Packages

CD4556BMS TOP VIEW
16 VDD 15 E 14 A 13 B 12 Q0 11 Q1 10 Q2 9 Q3 1/2 OF DUAL

1/2 OF DUAL

Q0 Q1 Q2 Q3 VSS

· 100% Tested for Quiescent Current at 20V · Standardized, Symmetrical Output Characteristics · Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC · Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V · 5V, 10V and 15V Parametric Ratings · Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices"
1/2 OF DUAL

CD4555BMS TOP VIEW
E A B Q0 Q1 Q2 Q3 VSS 1 2 3 4 5 6 7 8 16 VDD 15 E 14 A 13 B 12 Q0 11 Q1 10 Q2 9 Q3 1/2 OF DUAL

Applications
· Decoding · Code Conversion · Demultiplexing (Using Enable Input as a Data Input · Memory Chip-Enable Selection · Function Selection

Functional Diagrams
VDD A B E 2 3 1 16 4 5 6 7 12 11 10 9 VSS 8 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3

Description
CD4555BMS and CD4556BMS are dual one-of-four decoders/demultiplexers. Each decoder has two select inputs (A and B), an Enable input (E), and four mutually exclusive outputs. On the CD4555BMS the outputs are high on select; on the CD4556BMS the outputs are low on select. When the Enable input is high, the outputs of the CD4555BMS remain low and the outputs of the CD4556BMS remain high regardless of the state of the select inputs A and B. The CD4555BMS and CD4556BMS are similar to types MC14555 and MC14556, respectively. The CD4555BMS and CD4556BMS are supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack *CD4555B Only *H46 H4T H1E H6W CD4556B Only

A B E

14 13 15

CD4555BMS
VDD A B E 2 3 1 16 4 5 6 7 12 11 10 9 VSS 8 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3

A B E

14 13 15

CD4556BMS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

File Number

3346

7-1249

Specifications CD4555BMS, CD4556BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum

Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 +25oC, +25oC, LIMITS TEMPERATURE +25oC +125oC -55oC +25oC +125oC -55oC +25oC +125oC -55oC +125oC, +125oC, +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC 3.5 11 1.5 4 V V V V -55oC -55oC MIN -100 -1000 -100 14.95 0.53 1.4 3.5 -2.8 0.7 MAX 10 1000 10 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8 UNITS µA µA µA nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V

PARAMETER Supply Current

SYMBOL IDD

CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND

VOH > VOL < VDD/2 VDD/2

NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs.

3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.

7-1250

Specifications CD4555BMS, CD4556BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC LIMITS MIN MAX 440 594 400 540 200 270 UNITS ns ns ns ns ns ns

PARAMETER Propagation Delay A or B Input to any Output Propagation Delay E to any Output Transition Time

SYMBOL TPHL1 TPLH1 TPHL2 TPLH2 TTHL TTLH

CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND

+25oC +125oC, -55oC

+25oC +125oC, -55oC

NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, +25oC +125oC VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC -55oC Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC -55oC Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC -55oC Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC -55oC Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC -55oC Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC -55oC Input Voltage Low Input Voltage High VIL VIH VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V 1, 2 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC 7 V 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 -4.2 3 mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA V MIN MAX 5 150 10 300 10 600 50 UNITS µA µA µA µA µA µA mV

7-1251

Specifications CD4555BMS, CD4556BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Propagation Delay A or B Input to any Output Propagation Delay E to any Output Transition Time SYMBOL TPHL1 TPLH1 TPHL2 TPLH2 TTHL TTLH CIN CONDITIONS VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V Any Input NOTES 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 TEMPERATURE +25oC +25 C +25oC +25
oC o

MIN -

MAX 190 140 170 130 100 80 7.5

UNITS ns ns ns ns ns ns pF

+25oC +25oC +25
oC

Input Capacitance NOTES:

1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH VTN VTP VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10µA VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25o
o

MIN -2.8 0.2 VOH > VDD/2 -

MAX 25 -0.2 ±1 2.8 ±1 VOL < VDD/2 1.35 x +25oC Limit

UNITS µA V V V V V

C

+25 C +25oC +25oC +25oC +25oC

ns

NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

3. See Table 2 for +25oC limit. 4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A ± 1.0µA ± 20% x Pre-Test Reading ± 20% x Pre-Test Reading DELTA LIMIT

TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A

7-1252

Specifications CD4555BMS, CD4556BMS
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Final Test Group A Group B Group D Subgroup B-5 Subgroup B-6 MIL-STD-883 METHOD 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 READ AND RECORD

NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4

CONFORMANCE GROUPS Group E Subgroup 2

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V OPEN 4 - 7, 9 - 12 4 - 7, 9 - 12 GROUND 1 - 3, 8, 13 - 15 8 1, 8, 15 VDD 16 1 - 3, 13 - 16 16 4 - 7, 9 - 12 2, 14 3, 13 9V ± -0.5V 50kHz 25kHz PART NUMBER CD4555BMS & CD4556BMS

Logic Diagrams
4(12) 2(14) A Q0 A 5(11) Q1 6(10) B Q2 7(9) Q3 VDD E 2(14) 4(12) Q0 5(11) Q1 6(10)

*
3(13) B

*
3(13)

*
1(15) E

*
1(15) 7(9)

Q2

* *ALL INPUTS PROTECTED BY CMOS
PROTECTION NETWORK

* *ALL INPUTS PROTECTED BY CMOS
PROTECTION NETWORK

Q3 VDD

VSS

VSS

FIGURE 1. CD455RBMS LOGIC DIAGRAM (1 OF 2 IDENTICAL CIRCUITS)

FIGURE 2. CD4556BMS LOGIC DIAGRAM (1 OF 2 IDENTICAL CIRCUITS)

7-1253

CD4555BMS, CD4556BMS
TRUTH TABLE INPUTS ENABLE SELECT E 0 0 0 0 1 X = Don't Care B 0 0 1 1 X A 0 1 0 1 X Q3 0 0 0 1 0 OUTPUTS CD4555BMS Q2 0 0 1 0 0 Logic 1 High Logic 0 Low Q1 0 1 0 0 0 Q0 1 0 0 0 0 Q3 1 1 1 0 1 OUTPUTS CD4556BMS Q2 1 1 0 1 1 Q1 1 0 1 1 1 Q0 0 1 1 1 1

Typical Performance Characteristics
OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

30 25 20 15 10 5

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V

10V

5V 0 5 10 15

5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0

FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 0

0 -5 -10 -15

0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

-10V

-20 -25

-10V

-10

-15V

-30

-15V

-15

FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS

FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS

7-1254

CD4555BMS, CD4556BMS Typical Performance Characteristics
PROPAGATION DELAY TIME (tPLH, tPHL) (ns) AMBIENT TEMPERATURE (TA) = +25oC 250

(Continued)

PROPAGATION DELAY TIME (tPLH, tPHL) (ns)

AMBIENT TEMPERATURE (TA) = +25oC 250

200

SUPPLY VOLTAGE (VDD) = 5V

200 SUPPLY VOLTAGE (VDD) = 5V 150

150 10V 100 15V 50

100

10V 15V

50

0

20

40 60 80 100 LOAD CAPACITANCE (CL) (pF)

0

20

40

60

80

100

LOAD CAPACITANCE (CL) (pF)

FIGURE 7. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE (A OR B INPUT TO ANY OUTPUT)
PROPAGATION DELAY TIME (tPLH, tPHL) (ns) AMBIENT TEMPERATURE (TA) = +25oC 300 250 200 ANY INPUT 150 100 50 E INPUT

FIGURE 8. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE (E INPUTS TO ANY OUTPUT)
AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns)

200 SUPPLY VOLTAGE (VDD) = 5V

150

100 10V 50 15V

0

5

10

15

20

SUPPLY VOLTAGE (VDD) = 5V

0 0

20

40 60 80 100 LOAD CAPACITANCE (CL) (pF)

FIGURE 9. TYPICAL PROPAGATION DELAY TIME vs SUPPLY VOLTAGE
106 DYNAMIC POWER DISSIPATION (PD) (µW)

FIGURE 10. TYPICAL TRANSITION TIME vs LOAD CPACITANCE

AMBIENT TEMPERATURE (TA) = +25oC 10
5

104 103

SUPPLY VOLTAGE (VDD) = 15V LOAD CAPACITANCE (CL) = 50pF

102

VDD = 10V CL = 50pF VDD = 10V CL = 15pF

10 VDD = 5V CL = 50pF 1 10-1
2 4 68 2 4 68 2 4 68

1

10

102

2 4 68

103

2 4 68

104

INPUT FREQUENCY (f) (kHz)

FIGURE 11. TYPICAL DYNAMIC POWER DISSIPATION vs FREQUENCY

7-1255

CD4555BMS, CD4556BMS
20ns 90% 50% 10% tPLH 90% 50% 10% tPHL VDD OUTPUT Q3 VSS 90% 50% 10% tTHL tTLH tTLH tTHL fI = 1MHz, 50% DUTY CYCLE VDD OUTPUT Q3 VSS 20ns VDD INPUT B VSS 90% 50% 10% tPHL tPLH 20ns 20ns VDD INPUT B VSS

fI = 1MHz, 50% DUTY CYCLE

FIGURE 12. CD4555BMS B INPUT TO Q3 OUTPUT DYNAMIC SIGNAL WAVEFORMS

FIGURE 13. CD4556BMS B INPUT TO Q3 OUTPUT DYNAMIC SIGNAL WAVEFORMS

20ns 90% 50% 10% tPHL

20ns 20ns VDD 90% INPUT E VSS tPLH VDD OUTPUT Q3 VSS tTHL tTLH 90% 50% 10% tTLH tTHL 50% 10% tPLH tPHL VDD OUTPUT Q3 VSS 20ns VDD INPUT E VSS

90% 50% 10%

fI = 1MHz, 50% DUTY CYCLE

fI = 1MHz, 50% DUTY CYCLE

FIGURE 14. CD4555BMS E INPUT TO Q3 OUTPUT DYNAMIC SIGNAL WAVEFORMS

FIGURE 15. CD4556BMS E INPUT TO Q3 OUTPUT DYNAMIC SIGNAL WAVEFORMS

Applications
TRUTH TABLE
1/6 CD4555BMS

SELECT INPUTS
SELECT A A Q0 Q1 B B Q2 E Q3 Q0 Q1 OUTPUTS Q2 Q3

OUTPUTS Q0 DATA 0 0 0 Q1 0 DATA 0 0 Q2 0 0 DATA 0 Q3 0 0 0 DATA

B 0 0 1 1

A 0 1 0 1

INPUTS

DATA

1/6 CD4069BMS

FIGURE 16. 1 OF 4 LINE DATA DEMULTIPLEXER USING CD4555BMS

7-1256

CD4555BMS, CD4556BMS Applications (Continued)
CD4555BMS

TRUTH TABLE
A A Q0 Q1 B DECODER INPUTS B Q2 E Q3 Q0 Q1 Q2 Q3 OUTPUTS A Q0 Q1 B Q2 C E Q3 Q4 Q5 Q6 Q7

INPUTS C 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 2 0 0 1 0 0 0 0 0

Q OUTPUTS 3 0 0 0 1 0 0 0 0 4 0 0 0 0 1 0 0 0 5 0 0 0 0 0 1 0 0 6 0 0 0 0 0 0 1 0 7 0 0 0 0 0 0 0 1

1/6 CD4069BMS OR EQUIV

FIGURE 17. 1 OF 8 DECODER USING CD4555BMS

CD4555BMS A Q0 Q1 B B Q2 E Q3

A

Q0 Q1 Q2 Q3

DECODER INPUTS

A

Q0 Q1

Q4 Q5 Q6 Q7

B Q2 E A Q0 Q1 D B Q2 E Q3 B Q2 1/2 CD4556BMS E Q3 A Q0 Q1 Q3

C

OUTPUTS

Q8 Q9 Q10 Q11

E

A

Q0 Q1

Q12 Q13 Q14 Q15

B Q2 E Q3

FIGURE 18. 1 OF 16 DECODER USING CD4555BMS AND CD4556BMS

7-1257

CD4555BMS, CD4556BMS
TRUTH TABLE INPUTS E 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Q OUTPUTS 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

X = Don't Care

Chip Dimensions and Pad Layouts

CD4555BMSH
Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch).

CD4556BMSH

METALLIZATION: PASSIVATION:

Thickness: 11kÅ - 14kÅ,

AL.

10.4kÅ - 15.6kÅ, Silane

BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches

7-1258

CD4555BMS, CD4556BMS

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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