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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Phase Comparator and Programmable Counters
The MC14568B consists of a phase comparator, a divide­by­4, 16, 64 or 100 counter and a programmable divide­by­N 4­bit binary counter (all positive­edge triggered) constructed with MOS P­channel and N­channel enhancement mode devices (complementary MOS) in a monolithic structure. The MC14568B has been designed for use in conjunction with a programmable divide­by­N counter for frequency synthesizers and phase­ locked loop applications requiring low power dissipation and/or high noise immunity. This device can be used with both counters cascaded and the output of the second counter connected to the phase comparator (CTL high), or used independently of the programmable divide­by­N counter, for example cascaded with a MC14569B, MC14522B or MC14526B (CTL low). · Supply Voltage Range = 3.0 to 18 V · Capable of Driving Two Low­Power TTL Loads, One Low­Power Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range. · Chip Complexity: 549 FETs or 137 Equivalent Gates MAXIMUM RATINGS* (Voltages referenced to VSS)
Rating Symbol VDD Vin Iin PD TA Tstg DC Supply Voltage Value

MC14568B
L SUFFIX CERAMIC CASE 620

P SUFFIX PLASTIC CASE 648

D SUFFIX SOIC CASE 751B

ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Unit Vdc Vdc ­ 0.5 to + 18 ± 10 500 ­ 55 to + 125 ­ 65 to + 150 Input Voltage, All Inputs ­ 0.5 to VDD + 0.5 DC Input Current, per Pin Power Dissipation, per Package Operating Temperature Range Storage Temperature Range mAdc mW

TA = ­ 55° to 125°C for all packages.

TRUTH TABLE
F Pin 10 0 0 1 1 G Pin 11 0 1 0 1 Division Ratio of Counter D1 4 16 64 100

_C _C

* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: ­ 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: ­ 12 mW/_C From 100_C To 125_C

The divide by zero state on the programmable divide­by­N 4­bit binary counter, D2, is illegal.

BLOCK DIAGRAM
PCin 14 (REF.) B TG TG C1 9 COUNTER D1 10 F CTL 15 TG "0" 3 PE 2 DP3 4­BIT PROGRAMMABLE COUNTER D2 DP0 1 Q1/C2 D2 "0" VDD = PIN 16 VSS = PIN 8
REV 3 1/94

A

PHASE COMPARATOR

13 PCout 12 LD

CTL HIGH
11 G PCin P/C C1 D1 C1 PCout LD PCin

CTL LOW
PCout P/C LD D1

"0" Q1/C2

D2 Q1/C2

4

5 6 DP2 DP1

7

©MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995

MC14568B 1

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 ­ 1.2 ­ 0.25 ­ 0.62 ­ 1.8 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- ± 0.1 -- 5.0 10 20 ­ 1.0 ­ 0.2 ­ 0.5 ­ 1.5 0.51 1.3 3.4 -- -- -- -- -- ­ 1.7 ­ 0.36 ­ 0.9 ­ 3.5 0.88 2.25 8.8 ± 0.00001 5.0 0.005 0.010 0.015 -- -- -- -- -- -- -- ± 0.1 7.5 5.0 10 20 ­ 0.7 ­ 0.14 ­ 0.35 ­ 1.1 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- ± 1.0 -- 150 300 600 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc Min -- -- -- ­ 55_C 25_C 125_C Max Min -- -- -- Typ # 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage# "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance Quiescent Current (Per Package) Vin = 0 or VDD, Iout = 0 µA Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) Three­State Leakage Current Pins 1, 13 VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Iin Cin IDD µAdc pF µAdc IT IT = (0.2 µA/kHz) f + IDD IT = (0.4 µA/kHz) f + IDD IT = (0.9 µA/kHz) f + IDD µAdc ITL 15 -- ± 0.1 -- ± 0.0001 ± 0.1 -- ± 3.0 µAdc #Noise immunity for worst input combination. Noise Margin for both "1" and "0" level = 1.0 V min @ VDD = 5.0 V = 2.0 V min @ VDD = 10 V = 2.5 V min @ VDD = 15 V To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + 1 x 10­3 (CL ­ 50) VDDf where: IT is in µA (per package), CL in pF, VDD in V, and f in kHz is input frequency. ** The formulas given are for the typical characteristics only at 25_C. Pin 15 is connected to VSS or VDD for input voltage test.

PIN ASSIGNMENT
Q1/C2 PE "0" DP3 DP2 DP1 DP0 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD CTL PCin PCout LD G F C1

MC14568B 2

MOTOROLA CMOS LOGIC DATA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)
Characteristic Symbol tTLH VDD V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Min -- -- -- -- -- -- -- -- -- 15 15 15 Typ 180 90 65 100 50 40 125 60 45 -- -- -- Max 360 180 130 200 100 80 250 120 90 -- -- -- Unit ns Output Rise Time Output Fall Time tTHL ns Minimum Pulse Width, C1, Q1/C2, or PCin Input tWH ns Maximum Clock Rise and Fall Time, C1, Q1/C2, or PCin Input PHASE COMPARATOR Input Resistance Input Sensitivity, dc Coupled Turn­Off Delay Time, PCout and LD Outputs Turn­On Delay Time. PCout and LD Outputs DIVIDE­BY­4, 16, 64 OR 100 COUNTER (D1) Maximum Clock Pulse Frequency Division Ratio = 4, 64 or 100 fcl 5.0 10 15 5.0 10 15 tPLH, tPHL 5.0 10 15 5.0 10 15 3.0 8.0 10 1.0 3.0 50 -- -- -- -- -- -- 6.0 16 22 2.5 6.3 9.7 450 190 130 720 300 200 -- -- -- -- -- -- ns 900 380 260 1440 600 400 MHz Rin -- tPHL 5.0 to 15 5.0 to 15 5.0 10 15 5.0 10 15 -- -- -- -- -- -- -- 106 -- M tTLH, tTHL µs See Input Voltage 550 195 120 675 300 190 1100 390 240 1350 600 380 ns tPLH ns Division Ratio = 16 Propagation Delay Time, Q1/C2 Output Division Ratio = 4, 64 or 100 Division Ratio = 16 PROGRAMMABLE DIVIDE­BY­N 4­BIT COUNTER (D2) Maximum Clock Pulse Frequency (Figure 3a) Turn­On Delay Time, "0" Output (Figure 3a) Turn­Off Delay Time, "0" Output (Figure 3a) Minimum Preset Enable Pulse Width fcl 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 1.2 3.0 4.0 -- -- -- -- -- -- -- -- -- 1.8 8.5 12 450 190 130 225 85 60 75 40 30 -- -- -- 900 380 260 450 170 150 250 100 75 MHz tPLH ns tPHL ns tWH(PE) ns

MOTOROLA CMOS LOGIC DATA

MC14568B 3

SWITCHING TIME TEST CIRCUITS AND WAVEFORMS
VDD 10 k CTL DP0 DP1 DP2 DP3 PCin F G C1 PE PCout LD CL CL VDD 2 A LAGS B, PCout IS LOW. "0"out REF B 50% 20 ns 20 ns PCin PG1 A tPLH Q1/C2 "0" LD tPHL THREE­STATE tPHL tTLH THREE­STATE 25% tTHL 90% 10% tPHL 75% tPLH 90% 50% 10% tPLH tPLH tW(PCin) A LEADS B, PCout IS HIGH.

PULSE GENERATOR 1 PULSE GENERATOR 2

VOH VOL

VSS

PCout

Figure 1. Phase Comparator
VDD CTL DP0 DP1 DP2 DP3 PCin F G C1 PE

20 ns PCout LD 20 ns C1 10% 90% 50% tPHL Q1/C2 CL "0" Q1/C2 10% 90% 50% tTLH VSS tTHL

tW(C1) fin fmax

PULSE GENERATOR

Figure 2. Counter D1
VDD DP0 DP1 PCout DP2 LD DP3 Q1/C2 PCin F G "0" C1 CTL PE VSS N PULSES*

PULSE GENERATOR

VDD DP0 DP1 PCout DP2 LD DP3 Q1/C2 PCin F G "0" C1 CTL PE VSS CL

PULSE GENERATOR 1

CL

PULSE GENERATOR 2

20 ns Q1/C2 10% tPLH "0" 10% tTLH 90% 50% 90% 50%

20 ns

tW(Q1/C2)

Q1/C2 = PG 1 20 ns

50% 20 ns

tPHL

fin fmax

PE = PG2

90% 50% 10% tW(PE)

tTHL

"0" * N is the value programmed on the DP Inputs.

a.

Figure 3. Counter D2

b.

MC14568B 4

MOTOROLA CMOS LOGIC DATA

LOGIC DIAGRAM
14 A 13 PCout

PCin

B (REF.)

LD

D Q C C

D

Q Q C

9 C1

COUNTER D1

10 F 11 G 1

Q1/C2

15 CTL

3 "0" PE 2 PE

COUNTER D2

C Q D

VDD = PIN 16 VSS = PIN 8

4 DP3

5 DP2

6 DP1

7 DP0

MOTOROLA CMOS LOGIC DATA

MC14568B 5

Typical Maximum Frequency Divider D1 Division ratios: 4, 64 or 100 (CL = 50 pF)
28 26 f, FREQUENCY (MHz) 24 22 20 VDD = 15 V 18 f, FREQUENCY (MHz) 16 14 12 10 6 8 5 6 f, FREQUENCY (MHz) VDD = 5 V 4 2 0 ­ 40 4 VDD = 10 V 12 10 8 6

Typical Maximum Frequency Divider D1 Division ratio: 16 (CL = 50 pF)

VDD = 15 V

VDD = 10 V 4 2 0 ­ 40 VDD = 5 V

­ 20

0

+ 20 + 40 + 60 T, TEMPERATURE (°C)

+ 80

+ 100

Typical Maximum Frequency Divider D2 Division ratio: 2 (CL = 50 pF)

VDD = 15 V 3 VDD = 10 V 2 1 0 ­ 40 VDD = 5 V

­ 20

0

+ 20 + 40 + 60 T, TEMPERATURE (°C)

+ 80

+ 100

­ 20

0

+ 20 + 40 + 60 T, TEMPERATURE (°C)

+ 80

+ 100

MC14568B 6

MOTOROLA CMOS LOGIC DATA

OPERATING CHARACTERISTICS
The MC14568B contains a phase comparator, a fixed divider (÷ 4, ÷ 16, ÷ 64, ÷ 100) and a programmable divide­ by­N 4­bit counter. PHASE COMPARATOR The phase comparator is a positive edge controlled logic circuit. It essentially consists of four flip­flops and an output pair of MOS transistors. Only one of its inputs (PCin, pin 14) is accessible externally. The second is connected to the output of one of the two counters D1 or D2 (see block diagram). Duty cycles of both input signals (at A and B) need not be taken into consideration since the comparator responds to leading edges only. If both input signals have identical frequencies but different phases, with signal A (pin 14) leading signal B (Ref.), the comparator output will be high for the time equal to the phased difference. If signal A lags signal B, the output will be low for the same time. In between, the output will be in a three­state condition and the voltage on the capacitor of an RC filter normally connected at this point will have some intermediate value (see Figure 4). When used in a phase locked loop, this value will adjust the Voltage Controlled Oscillator frequency by reducing the phase difference between the reference signal and the divided VCO frequency to zero.
VDD A (PCin) 1/f VOH B (REF.) LD VOL VOH VOL VOL VOH VSS

If the input signals have different frequencies, the output signal will be high when signal B has a lower frequency than signal A, and low otherwise. Under the same conditions of frequency difference, the output will vary between VOH (or VOL) and some intermediate value until the frequencies of both signals are equal and their phase difference equal to zero, i.e. until locked condition is obtained. Capture and lock range will be determined by the VCO frequency range. The comparator is provided with a lock indicator output, which will stay at logic 1 in locked conditions. The state diagram (Figure 5) depicts the internal state transitions. It assumes that only one transition on either signal occurs at any time. It shows that a change of the output state is always associated with a positive transition of either signal. For a negative transition, the output does not change state. A positive transition may not cause the output to change, this happens when the signals have different frequencies.

DIVIDE BY 4, 16, 64 OR 100 COUNTER (D1) This counter is able to work at an input frequency of 5 MHz for a VDD value of 10 volts over the standard temperature range when dividing by 4, 64 and 100. Programming is accomplished by use of inputs F and G (pins 10 and 11) according to the truth table shown. Connecting the Control input (CTL, pin 15), to VDD allows cascading this counter with the programmable divide­by­N counter provided in the same package. Independent operation is obtained when the Control input is connected to VSS. The different division ratios have been chosen to generate the reference frequencies corresponding to the channel spacings normally required in frequency synthesizer applications. For example. with the division ratio 100 and a 5 MHz crystal stabilized source a reference frequency of 50 kHz is supplied to the comparator. The lower division ratios permit operation with low frequency crystals.

PCout

Figure 4. Phase Comparator Waveforms

INPUT STATE

00 X X 01 11 A B 10 10

00 01 11 01

00 10 11

PCout LD (LOCK DETECT)

0 0

3­STATE OUTPUT DISCONNECTED 1

1 0

Figure 5. Phase Comparator State Diagram

MOTOROLA CMOS LOGIC DATA

MC14568B 7

If used in cascade with the programmable divide­by­N counter, practically all usual reference frequencies, or channel spacings of 25, 20, 12.5, 10, 6.25 kHz, etc. are easily achievable. PROGRAMMABLE DIVIDE­BY­N 4­BIT COUNTER (D2) This counter is programmable by using inputs DP0 ... DP3

(pins 7 ... 4). The Preset Enable input enables the parallel preset inputs DP0... D P3. The "0" output must be externally connected to the PE input for single stage applications. Since there is not a cascade feedback input, this counter, when cascaded, must be used as the most significant digit. Because of this, it can be cascaded with binary counters as well as with BCD counters (MC14569B, MC14522B, MC14526B).

TYPICAL APPLICATIONS

fin

C

CF MC14569B ZERO DETECT

C PE

CF MC14522B OR MC14526B

Q4 "0"

C PE

CF MC14522B OR MC14526B

Q4 "0"

Q1/C2 MC14568B PE "0"

DP0 ­ ­ ­ ­ ­ ­ DP3 LSD

DP0 ­ ­ ­ ­ ­ ­ DP3

DP0 ­ ­ ­ ­ ­ ­ DP3 MSD fout

Figure 6. Cascading MC14568B and MC14522B or MC14526B with MC14569B

(40 kHz)

PCin C1 CTI "0" PE

MC14568B

PCout G F

VCO VSS VSS

fout (144 ­ 146 MHz)

VSS

Q1/C2 VDD DP0 ­ ­ ­ ­ DP3 CF C MIXER 2k 2M MC14011 Q

MC14569B ZERO DETECT

Frequencies shown in parenthesis are given as an example.

CRYSTAL OSCILLATOR (143.5 MHz)

Figure 7. Frequency Synthesizer with MC14568B and MC14569B Using a Mixer (Channel Spacing 10 kHz)

MC14568B 8

MOTOROLA CMOS LOGIC DATA

(5 MHz) (VDD)

PCin C1 CTL "0"

MC14568B

PCout G F PE

VCO VDD VDD

fout

VSS

VDD DP0 ­ ­ ­ ­ ­ DP3 "0" MC14522B

C

Q

CF MC14569B

C

ZERO DETECT PE (BCD) BINARY

DP0 ­ ­ ­ ­ ­ DP3

N1 (0 ­ 5) (625 kHz STEPS) Divide ratio = 160N1 + 16N2 + N3 Example: fout = N1 (MHz) + N2 (x 100 kHz) + N3 (x25 kHz) Frequency range = 5 MHz Channel spacing = 25 kHz Reference frequency = 6.25 kHz

N2 (0 ­ 9) (62.5 kHz STEPS)

N3 (0, 4, 8, 12) (6.25 kHz STEPS)

Figures shown in parenthesis refer to example. Recommended reading: (1) AN535: "Phase­Lock Techniques" (2) AR254: "Phase­Locked Loop Design Articles"

Figure 8. Frequency Synthesizer Using MC14568B, MC14569B and MC14522B (Without Mixer)

MOTOROLA CMOS LOGIC DATA

MC14568B 9

MC14568B 10
26.965­27.255 (28.605) MHz RECEIVER SECOND MIXER TO 455 kHz IF 10.695 MHz RF AMP 16.270­16.560 (17.910) MHz LOCK DETECTOR MC14568B REFERENCE OSCILLATOR ÷2 ÷64 D ÷8 LOOP LOW PASS FILTER VCO RECEIVER FIRST MIXER ÷N 10.24 MHz X3 .91­1.20 (2.55) MHz N = 91­120 (255) MHz ÷N MC14526B NOTE: 1. 10 kHz Channel Spacing 2. Expandable to 165 Channels (Expanded frequency range shown in parenthesis) VDD RCV 10.695 MHz DOWN MIXER 10 kHz

Figure 9. Typical 23­Channel CB Frequency Synthesizer for Double Conversion Transceivers
TRX OSCILLATOR (TRASMIT ONLY)

MOTOROLA CMOS LOGIC DATA

MIXER

TO TRANSMITTER 26.965­27.255 (28.605) MHz

OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 620­10 ISSUE V
­A­
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 ­­­ 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ­­­ 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01

­B­
1 8

C

L

­T­
SEATING PLANE

N E F D G
16 PL

K M J
16 PL

0.25 (0.010)
M

M

T B

S

0.25 (0.010)

T A

S

P SUFFIX PLASTIC DIP PACKAGE CASE 648­08 ISSUE R
­A­
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01

B
1 8

F S

C

L

­T­ H G D
16 PL

SEATING PLANE

K

J T A
M

M

0.25 (0.010)

M

MOTOROLA CMOS LOGIC DATA

MC14568B 11

OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B­05 ISSUE J
­A­
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019

16

9

­B­
1 8

P

8 PL

0.25 (0.010)

M

B

S

G F

K C ­T­
SEATING PLANE

R

X 45 _

M D
16 PL M

J

0.25 (0.010)

T B

S

A

S

DIM A B C D F G J K M P R

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MC14568B 12



*MC14568B/D*

MOTOROLA CMOS LOGIC DATA MC14568B/D