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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14599 See Page 6-174
8-Bit Bus-Compatible Latches
The MC14597B and MC14598B are 8bit latches, one addressed with an internal counter and the other addressed with an external binary address. The 8 latchoutputs are high drive, threestate and bus line compatible. The drive capability allows direct applications with MPU systems such as the Motorola 6800 family. With MC14597B, a 3bit address counter (clocked on the falling edge of Increment) selects the appropriate latch. The latches of the MC14598B are accessed via the Address pins, A0, A1, and A2. A Full Flag is provided on the MC14597B to indicate the position of the Address counter. All 8 outputs from the latches are available in parallel when Enable is in the low state. Data is entered into a selected latch from the Data pin when the Strobe is high. Master reset is available on both parts. · Serial Data Input · ThreeState Bus Compatible Parallel Outputs · ThreeState Control Pin (Enable) TTL Compatible Input · Open Drain Full Flag (Multiple Latch WireO Ring) · Master Reset · Level Shifting Inputs on All Except Enable · Diode Protection -- All Inputs · Supply Voltage Range -- 3.0 Vdc to 18 Vdc · Capable of Driving TTL Over Rated Temperature Range With Fanout as Follows: 1 TTL Load 4 LSTTL Loads BLOCK DIAGRAMS
2 RESET LOGIC 4 ENABLE
MC14597B MC14598B
L SUFFIX CERAMIC CASE 620
P SUFFIX PLASTIC CASE 648
D SUFFIX SOIC CASE 751B
ORDERING INFORMATION
MC14597BCP MC14597BCL MC14597BDW Plastic Ceramic SOIC
TA = 55° to 125°C for all packages.
L SUFFIX CERAMIC CASE 726
MC14597B
RESET
D0 RESET
3 6 8 LATCHES THREE STATE OUTPUT BUFFERS 1 15 14 13 12 11 10 9 D0 D1 D2 D3 D4 D5 D6 D7
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VDD D1 D2 D3 D4 D5 D6 D7 D0 RESET
P SUFFIX PLASTIC CASE 707
DATA STROBE 3BIT ADDRESS COUNTER 7 INCREMENT VDD = 16 VSS = 8 FULL LOGIC 5 FULL ADDRESS DECODER
DATA ENABLE FULL STROBE INCREMENT VSS
ORDERING INFORMATION
MC14598BCP MC14598BCL Plastic Ceramic
TA = 55° to 125°C for all packages.
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
VDD D1 D2 D3 D4 D5 D6 D7 A2
MC14598B
ENABLE 4 RESET DATA STROBE A0 7 A1 8 ADDRESS A2 10 DECODER VDD = 18 VSS = 9 2 3 6 8 LATCHES 1 17 THREE 16 STATE 15 OUTPUT 14 BUFFERS 13 12 11 D0 D1 D2 D3 D4 D5 D6 D7
OUTPUT TRUTH TABLE
Enable 1 0 Outputs High Impedance Dn
DATA ENABLE NC STROBE A0 A1 VSS
Dn = State of nth latch NC = NO CONNECTION
REV 3 1/94
©MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995
MC14597B MC14598B 1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol VDD Vin Vin Vout Iin, lout PD Tstg TL Parameter DC Supply Voltage Value Unit V V V V mA mW 0.5 to + 18.0 Input Voltage, Enable (DC or Transient) Input Voltage, All other Inputs (DC or Transient) Output Voltage (DC or Transient) Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature Lead Temperature (8Second Soldering) 0.5 to VDD + 0.5 0.5 to VDD + 12 0.5 to VDD + 0.5 ± 10 500 65 to + 150 260
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
v
v
_C _C
* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: "P and D/DW" Packages: 7.0 mW/C From 65_C To 125_C Ceramic "L" Packages: 12 mW/_C From 100_C To 125_C
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Min -- -- --
55_C
25_C 0 0 0
125_C
Max
Min -- -- --
Typ #
Max
Min -- -- --
Max
Unit Vdc
Output Voltage Vin = VDD or 0
"0" Level
0.05 0.05 0.05 -- -- -- 0.8 1.6 2.4 -- -- --
0.05 0.05 0.05 -- -- -- 0.8 1.6 2.4 -- -- --
0.05 0.05 0.05 -- -- -- 0.8 1.6 2.4
"1" Level Vin = 0 or VDD Input Voltage** -- Enable "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Input Voltage "0" Level Other Inputs (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) (VO = 0.5 or 4.5 Vdc) "1" Level (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current Source (Full -- Sink Only) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current ThreeState Leakage Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) **Total Supply Current at an **External Load Capacitance of **130 pF Sink
VOH
4.95 9.95 14.95 -- -- -- 2.0 6.0 10
4.95 9.95 14.95 -- -- -- 2.0 6.0 10
5.0 10 15 1.1 2.2 3.4 1.9 3.1 4.3
4.95 9.95 14.95 -- -- -- 2.0 6.0 10
Vdc
VIL
Vdc
VIH
Vdc -- -- -- Vdc 5.0 10 15 -- -- -- 3.5 7.0 11 1.5 3.0 4.0 -- -- -- -- -- -- 3.5 7.0 11 2.25 4.50 6.75 2.75 5.50 8.25 1.5 3.0 4.0 -- -- -- -- -- -- 3.5 7.0 11 1.5 3.0 4.0 -- -- -- Vdc
VIL
VIH
5.0 10 15
IOH 5.0 10 15 IOL 5.0 10 15 15 15 -- 5.0 10 15 5.0 10 1.0 -- -- 1.6 -- -- -- -- -- -- -- -- -- -- -- -- -- ± 0.1 ± 0.1 -- 5.0 10 20 1.0 -- -- 1.6 -- -- -- -- -- -- -- -- 2.0 6.0 12 3.2 6.0 12 ± 0.00001 ± 0.00001 5.0 0.005 0.010 0.015 -- -- -- -- -- -- ± 0.1 ± 0.1 7.5 5.0 10 20 1.0 -- -- 1.6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- ± 1.0 ± 3.0 -- 150 300 600
mAdc
mAdc
Iin ITL Cin IDD
µAdc µAdc pF µAdc
IT = (2.0 µA/kHz) f + IDD IT = (4.0 µA/kHz) f + IDD IT = (6.0 µA/kHz) f + IDD Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. IT
µAdc
MC14597B MC14598B 2
MOTOROLA CMOS LOGIC DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (TA = 25_C, CL = 130 pF + 1 TTL Load)
Characteristic Symbol tTLH, tTHL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 tWH, tWL 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 tsu 5.0 10 15 5.0 10 15 5.0 10 15 th 5.0 10 15 5.0 10 15 trem 5.0 10 15 100 50 35 100 50 35 20 20 20 50 25 20 50 25 20 25 15 10 -- -- -- -- -- -- -- -- -- ns 100 50 35 200 100 70 400 200 170 50 25 20 100 50 35 200 100 85 -- -- -- -- -- -- -- -- -- ns All Types Typ # 100 50 40 160 125 100 200 100 80 200 100 80 175 90 70 160 120 80 100 50 40 100 50 40 150 80 50 Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 320 240 160 200 100 80 200 100 80 300 160 100 Max 200 100 80 ns 320 250 200 400 200 160 400 200 160 350 180 140 ns -- -- -- -- -- -- -- -- -- -- -- -- ns Unit ns Output Rise and Fall Time tTLH, tTHL = (0.5 ns/pF) CL + 35 ns tTLH, tTHL = (0.2 ns/pF) CL + 25 ns tTLH, tTHL = (0.16 ns/pF) CL + 20 ns Propagation Delay Time Enable to Output tPLH, tPHL Strobe to Output Strobe to Full (MC14597B only) Reset to Output Pulse Width Enable Strobe Increment (MC14597B only) Reset Setup Time Data Address (MC14598B only) Increment (MC14597B only) Hold Time Data Address (MC14598B only) Reset Removal Time * The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
MOTOROLA CMOS LOGIC DATA
MC14597B MC14598B 3
MC14597B FUNCTION DIAGRAM
VDD ENABLE 4 TO OTHER LATCHES VDD R D Q CLK STROBE 6 VDD 5 FULL
RESET 2
DATA 3 1 D0 TO OTHER LATCHES SEVEN SELECT R 3 STAGE COUNTER AND DECODER CLK INCREMENT 7 ZERO SELECT
ONE LATCH
VSS 15 14 13 12 11 10 9 D1 D2 D3 D4 D5 D6 D7
ADDITIONAL 7 LATCHES
MC14597B TIMING DIAGRAMS
D6 (INTERNAL)
D7 (INTERNAL) tWL INCREMENT DATA STROBE tW FULL trem 50% tW tTLH Dn 1 tPHL FULL 10% 90% 90% tTHL 10% 20 ns 90% tsu th 10% 20 ns 90% tPHL tsu 10% tWH
RESET NOTE: Enable in High state.
ENABLE
* tWL
*
* 1.4 V with VDD = 5.0 V NOTES: 1. Highimpedance output state (another device controls bus). 2. Reset in High state.
MC14597B MC14598B 4
MOTOROLA CMOS LOGIC DATA
MC14598B FUNCTION DIAGRAM
RESET 2
VDD
DATA 3 TO OTHER LATCHES STROBE 6 1 D0
ENABLE 4 EACH LATCH TO OTHER LATCHES A0 7 A1 8 A2 10 (M.S.B) ADDRESS DECODER ADDITIONAL 7 LATCHES ZERO SELECT
VSS
17 16 15 14 13 12 11
D1 D2 D3 D4 D5 D6 D7
MC14598B TIMING DIAGRAM
90% 10% tTHL D7 tPLH RESET tW A0, A1, A2 1 50% tPHL tTLH 20 ns 50% tsu th DATA STROBE ENABLE * tW * 1.4 V with VDD = 5.0 V NOTES: 1. Highimpedance output state (another device controls bus). 2. Output Load as for MC14597B. 90% 10% 20 ns tsu 50% 90% 10% 20 ns tW th 90% 10% tPLH 90% 10%
50%
MOTOROLA CMOS LOGIC DATA
MC14597B MC14598B 5
LATCH TRUTH TABLE
Strobe 0 1 X Reset 1 1 0 Address Latch * Data 0 Other Latches * * 0 X X X X = Don't care Increment
TRUTH TABLE FOR MC14597B
Enable X X 1 0 1 Reset 1 1 0 1 1 Address Counter Count Up No Change Reset to Zero No Change If at ADDRESS 7 Full -- -- Set to One Set to One To Zero on Falling Edge of STROBE
* = No change in state of latch X = Don't care
TEST LOAD ALL OUTPUTS
+5.0 V RL = 2.5 k Dn
130 pF
11.7 k
Circuit diagrams external to or containing Motorola products are included as a means of illustration only. Complete information sufficient for construction purposes may not be fully illustrated. Although the information herein has been carefully checked and is believed to be reliable. Motorola assumes no responsibility for inaccuracies. Information herein does not convey to the purchaser any license under the
patent rights of Motorola or others. The information contained herein is for guidance only, with no warranty of any type, expressed or implied. Motorola reserves the right to make any changes to the information and the product(s) to which the information applies and to discontinue manufacture of the product(s) at any time.
MC14597B MC14598B 6
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 62010 ISSUE V
A
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
B
1 8
C
L
T
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
T B
S
0.25 (0.010)
T A
S
P SUFFIX PLASTIC DIP PACKAGE CASE 64808 ISSUE R
A
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
B
1 8
F S
C
L
T H G D
16 PL
SEATING PLANE
K
J T A
M
M
0.25 (0.010)
M
MOTOROLA CMOS LOGIC DATA
MC14597B MC14598B 7
OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B05 ISSUE J
A
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
16
9
B
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C T
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
T B
S
A
S
DIM A B C D F G J K M P R
L SUFFIX CERAMIC DIP PACKAGE CASE 72604 ISSUE G
A
18 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F FOR FULL LEADS. HALF LEADS OPTIONAL AT LEAD POSITIONS 1, 9, 10, AND 18. DIM A B C D F G J K L M N S INCHES MIN MAX 0.880 0.910 0.240 0.295 0.200 0.015 0.021 0.055 0.070 0.100 BSC 0.008 0.012 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 22.35 23.11 6.10 7.49 5.08 0.38 0.53 1.40 1.78 2.54 BSC 0.20 0.30 3.18 4.32 7.62 BSC 0_ 15_ 0.51 1.02
B
1 9 OPTIONAL LEAD CONFIGURATION (1, 9, 10, 18)
L C N T
SEATING PLANE
K F G D 18 PL 0.25 (0.010)
M
M J 18 PL 0.25 (0.010)
T A
S
M
T B
MC14597B MC14598B 8
MOTOROLA CMOS LOGIC DATA
P SUFFIX PLASTIC DIP PACKAGE CASE 70702 ISSUE C
NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. MILLIMETERS MIN MAX 22.22 23.24 6.10 6.60 3.56 4.57 0.36 0.56 1.27 1.78 2.54 BSC 1.02 1.52 0.20 0.30 2.92 3.43 7.62 BSC 0_ 15_ 0.51 1.02 INCHES MIN MAX 0.875 0.915 0.240 0.260 0.140 0.180 0.014 0.022 0.050 0.070 0.100 BSC 0.040 0.060 0.008 0.012 0.115 0.135 0.300 BSC 0_ 15 _ 0.020 0.040
18 1
10
B
9
A C L
DIM A B C D F G H J K L M N
N F H G D
SEATING PLANE
K M J
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MOTOROLA CMOS LOGIC DATA
*MC14597B/D*
MC14597B MC14598B MC14597B/D 9