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MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14599 See Page 6-174 8-Bit Bus-Compatible Latches The MC14597B and MC14598B are 8­bit latches, one addressed with an internal counter and the other addressed with an external binary address. The 8 latch­outputs are high drive, three­state and bus line compatible. The drive capability allows direct applications with MPU systems such as the Motorola 6800 family. With MC14597B, a 3­bit address counter (clocked on the falling edge of Increment) selects the appropriate latch. The latches of the MC14598B are accessed via the Address pins, A0, A1, and A2. A Full Flag is provided on the MC14597B to indicate the position of the Address counter. All 8 outputs from the latches are available in parallel when Enable is in the low state. Data is entered into a selected latch from the Data pin when the Strobe is high. Master reset is available on both parts. · Serial Data Input · Three­State Bus Compatible Parallel Outputs · Three­State Control Pin (Enable) TTL Compatible Input · Open Drain Full Flag (Multiple Latch Wire­O Ring) · Master Reset · Level Shifting Inputs on All Except Enable · Diode Protection -- All Inputs · Supply Voltage Range -- 3.0 Vdc to 18 Vdc · Capable of Driving TTL Over Rated Temperature Range With Fanout as Follows: 1 TTL Load 4 LSTTL Loads BLOCK DIAGRAMS 2 RESET LOGIC 4 ENABLE MC14597B MC14598B L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B ORDERING INFORMATION MC14597BCP MC14597BCL MC14597BDW Plastic Ceramic SOIC TA = ­ 55° to 125°C for all packages. L SUFFIX CERAMIC CASE 726 MC14597B RESET D0 RESET 3 6 8 LATCHES THREE STATE OUTPUT BUFFERS 1 15 14 13 12 11 10 9 D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD D1 D2 D3 D4 D5 D6 D7 D0 RESET P SUFFIX PLASTIC CASE 707 DATA STROBE 3­BIT ADDRESS COUNTER 7 INCREMENT VDD = 16 VSS = 8 FULL LOGIC 5 FULL ADDRESS DECODER DATA ENABLE FULL STROBE INCREMENT VSS ORDERING INFORMATION MC14598BCP MC14598BCL Plastic Ceramic TA = ­ 55° to 125°C for all packages. 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 VDD D1 D2 D3 D4 D5 D6 D7 A2 MC14598B ENABLE 4 RESET DATA STROBE A0 7 A1 8 ADDRESS A2 10 DECODER VDD = 18 VSS = 9 2 3 6 8 LATCHES 1 17 THREE 16 STATE 15 OUTPUT 14 BUFFERS 13 12 11 D0 D1 D2 D3 D4 D5 D6 D7 OUTPUT TRUTH TABLE Enable 1 0 Outputs High Impedance Dn DATA ENABLE NC STROBE A0 A1 VSS Dn = State of nth latch NC = NO CONNECTION REV 3 1/94 ©MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995 MC14597B MC14598B 1 ОООООООООООООООООООООООООООООООООО ОООООООООООООООООООООООООООООООООО ОООООООООООООООООООООООООООООООООО ОООООООООООООООООООООООООООООООООО ОООООООООООООООООООООО ОООООООООООООООООООООО ОООООООООООООООООООООО ОООООООООООООООООООООО MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol VDD Vin Vin Vout Iin, lout PD Tstg TL Parameter DC Supply Voltage Value Unit V V V V mA mW ­ 0.5 to + 18.0 Input Voltage, Enable (DC or Transient) Input Voltage, All other Inputs (DC or Transient) Output V