Motorola 4554 free download

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14554B 2-Bit by 2-Bit Parallel Binary Multiplier The MC14554B 2 x 2­bit parallel binary multiplier is constructed with complementary MOS (CMOS) enhancement mode devices. The multiplier can perform the multiplication of two binary numbers and simultaneously add two other binary numbers to the product. The MC14554B has two multiplicand inputs (X0 and X1), two multiplier inputs (Y0 and Y1), five cascading or adding inputs (K0, K1, M0, M1, and M2), and five sum and carry outputs (S0, S1, S2, C1 [S3], and C0). The basic multiplier can be expanded into a straightforward m­bit by n­bit parallel multiplier without additional logic elements. Application areas include arithmetic processing (multiplying/adding, obtaining square roots, polynomial evaluation, obtaining reciprocals, and dividing), Fast Fourier Transform processing, digital filtering, communications (convolution and correlation), and process and machine controls. · · · · · · · · Diode Protection on All Inputs All Outputs Buffered Straight­forward m­Bit By n­Bit Expansion No Additional Logic Elements Needed for Expansion Multiplies and Adds Simultaneously Positive Logic Design Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low­Power TTL Loads or One Low­Power Schottky TTL Load Over the Rated Temperature Range L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC TA = ­ 55° to 125°C for all packages. MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol VDD Parameter DC Supply Voltage Value Unit V V ­ 0.5 to + 18.0 ± 10 500 ­ 65 to + 150 Vin, Vout Iin, Iout PD Tstg Input or Output Voltage (DC or Transient) ­ 0.5 to VDD + 0.5 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. ООООООООООООООООООООО ООООООООООООООООООООО ООООООООООООООООООООО ООООООООООООООООООООО Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature mA mW v v EQUATIONS S = (X x Y) + K + M Where: x Means Arithmetic Times. + Means Arithmetic Plus. S = S3 S2 S1 S0, X = X1X0, Y = Y1Y0, K = K1 K0, M = M1 M0 (Binary Numbers). Example: Given: X = 2(1), Y = 3(11) K = 1(01), M = 2(10) Then: S = (2 x 3) + 1 + 2 = 9 S = (10 x 11) + 01 + 10 = 1001 _C TL Lead Temperature (8­Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: ­ 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: ­ 12 mW/_C From 100_C To 125