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SYSTEM MODULE GR8 01/98OJ Technical Documentation

NHE­4 8­1 Copyright © Nokia Mobile Phones

Contents of System Module GR8
System Module GR8 Introduction Technical Section WARNINGS External and Internal Connectors Internal Signals Between RF and ASIC Internal Signals Between RF and RFI Functional Description of Baseband Block Technical Specifications Names of Functional Blocks Clocking Sceme Reset and Power Control Watchdog System CTRLU PWRU DSPU AUDIO ASIC RFI Functional Description of RF block RF Frequency Plan Regulators Power Distribution Current Consumption Receiver Transmitter Synthesizer Block Diagram of Baseband Power Distribution Diagram of Baseband Block Diagram of RF Power Distribution Diagram of RF Connections between System and RF Blocks Connections between RF and TX Blocks Circuit Diagram of GR8; System Blocks Circuit Diagram of GR8; CPU & Memories Circuit Diagram of GR8; Power Supply IC & Batt. Charg. unit Circuit Diagram of GR8; DSP, Clock Generator & Memories Circuit Diagram of GR8; Audio Codec IC Circuit Diagram of GR8; ASIC IC 8­3 8­3 8­3 8­3 8­3 8­7 8­8 8­9 8­9 8­9 8­10 8­11 8­12 8­13 8­19 8­21 8­24 8­26 8­31 8­33 8­33 8­33 8­34 8­34 8­35 8­39 8­44 8­48 8­49 8­50 8­51 8­52 8­53 8­54 8­55 8­56 8­57 8­58 8­59

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Circuit Diagram of GR8; RFI IC Circuit Diagram of GR8; RF Receiver and Regulator Circuit Diagram of GR8; RF Transmitter Layout Diagram of GR8 Side 1 Version 09 Layout Diagram of GR8 Side 2 Version 09 Parts List of GR8 EDMS Issue: 6.8

8­60 8­61 8­62 8­63 8­64 8­65

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System Module GR8
Introduction
GR8 is the baseband/RF module NHE­4 cellular tranceiver. The GR8 module carries out all the system and RF functions of the tranceiver. System module GR8 is designed for a handportable phone, that operate in GSM system.

Technical Section
All functional blocks of the system module are mounted on a single multi layer printed circuit board. The chassis of the radio unit has separating walls for baseband and RF. All components of the baseband section are surface mountable. They are soldered using reflow. The connections to accessories are taken through the bottom connector of the radio unit. The connections to the User Interface module (UIF) are fed through a flex connector. There is no physical connector between the RF and baseband sections.

WARNINGS
The maximum battery voltage during the transmission should not exceed 8.0 V. Higher battery voltages may destroy the power amplifier. This will be quaranteed by hardware based limiting which has maximum value 7.6 ±0.3 V.

External and Internal Connectors
The system module has two connector, external bottom connector and internal UIF module connector.

4 Antenna connector 2 1

3 Battery connector 2 1 4 Charging connector 3 2 1

X100

16

9 30

1 X196 UIF module connector D0000323

1 8 System connector

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Bottom Connector X100 System Connector Pin: 1, 9 2 Name: GND MIC/JCONN Description: Digital ground External audio input from accessories or handsfree microphone. Multiplexed with junction box connection control signal. 16.8 k pull down in phone. Analog ground for accessories. Connected directly to digital ground on the PCB. Transmitted DBUS data to the accessories. Serial bidirectional data and control between the handportable and accessories. HOOK indication. The phone has a 100 k pull­up resistor. Data to flash from flash programmer. Handsfree device power on/off. Data to flash programming device. Battery charging voltage. External audio output to accessories or handsfree speaker. 100 k pull­down resistor in phone to turn on the junction box. DBUS data bit sync clock. DBUS received data from the accessories. Not used. Programming voltage for flash. DBUS data clock.

3 4 5 6

AGND TDA M2BUS HOOK/RXD2

7 8, 16 10

PHFS/TXD2 VCHAR EAR/HFPWR

11 12 13 14 15

DSYNC RDA NC VF DCLK

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Battery Connector Pin: 1 2 3 4 Charging Connector Pin: 1 2 3 4 Antenna Connector Pin: 1 2 Name: RF EXT GND Description: External antenna signal Ground Name: VCHAR GND VCHAR GND Description: Battery charging voltage Ground Battery charging voltage Ground Name: GND TBAT BTYPE VBATT Description: Ground Battery temperature Battery type Battery voltage

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UIF Module Connector X196 Pin: 1 2 3, 30 4 5­8 9 10 11 12 13 ­ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Name: VL1 GND VBATT BACKLIGHT UIF(0;3) UIF4 UIF5 UIF6 MIC ENA COL(0;3) CALL LED MICP MICN EARP EARN BUZZER XPWRON VA1 SIMCLK SIMRESET VSIM SIMDATA AGND Description: Logic supply voltage 4.65 V Ground Battery voltage Backlights on/off Lines for keyboard read and LCD controller Line for keyboard read and LCD controller read/write strobe Line for keyboard read and LCD controller data/instruction register selection LCD controller enable strobe Microphone bias enable Lines for keyboard write Call LED enable Microphone (positive node) Microphone (negative node) Earpiece (negative node) Earpiece (positive node) PWM signal buzzer control Power key (active low) Analog supply voltage 4.65 V Clock for SIM data Reset for SIM SIM voltage supply voltage Serial data for SIM Analog ground

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Internal Signals Between RF and ASIC
Symbol: SCLK Description: Synthesizer clock · load impedance: · frequency: Synthesizer data · load impedance: · data rate frequency: Synthesizer enable · PLL contr. disabled: · PLL activated: · current: RX supply voltage on/off · RX supply voltage on: · RX supply voltage off: · current: Supply voltage on/off · RF regulators on: · RF regulators off: · current: TX supply voltage on/off · TX supply voltage on: · TX supply voltage off: · current: TX enable · transmitter power enable: · transmitter power disable: 26 MHz clock to ASIC Values:

10 k 3.25 MHz 10 k 3.25 MHz 4.5...4.65...4.8 V 0...0.2...0.7 V 50 µA 4.5...4.65...4.8 V 0...0.2...0.7 V 0.5 mA 4.5...4.65...4.8 V 0...0.2...0.7 V 1.0 mA 4.5...4.65...4.8 V 0...0.2...0.7 V 0.5 mA 4.5...4.65...4.8 V 0...0.2...0.7 V

SDATA

SENA1

RXPWR

SYNTHPWR

TXPWR

TXP

CLKIN

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Internal Signals Between RF and RFI
Symbol: AFC Description: Values:

Automatic frequency control voltage 0.35...4.35 V · voltage min/max: · resolution: 11 bits · load impedance (dynamic): 10 k TX transmit power control voltage · voltage range min/max: 0.3...4.2 V · impedance: 10 k Differential TX quadrature signal 1.15...1.2...1.25 VPP · differential voltage swing: · D.C. level: 2.30...2.35...2.40 V · load impedance: 30 k Differential TX inphase signal · differential voltage swing: · D.C. level: · load impedance: Front end AGC control · reduced front end gain: · normal front end gain: · current: RX quadrature signal · output level: · source impedance: RX inphase signal · output level: · source impedance:

TXC

TXQP,TXQN

TXIP,TXIN

1.15...1.2...1.25 VPP 2.30...2.35...2.40 V 30 k 0...0.2...0.7 V 4.5...4.65...4.8 V 0.1 mA 25 mVPP 470 25 mVPP 470

PDATA0

RXQ

RXI

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Functional Description of Baseband Block
The purpose of the baseband module is to control the phone and process audio signals to and from RF. The module also controls the user interface.

Technical Specifications
There are three different operation modes: ­ active mode ­ idle mode ­ power off mode In the active state all circuits are powered and part of the module may be in idle mode. The module is usually in the idle mode when there is no call and the phone is in SERV. In the idle mode circuits are reset, powered down and clocks are stopped or the frequency reduced. All the clocks except the main clock from VCTCXO can be stopped in that mode. Whether the SIM clock is stopped or not depends on the network. In power off mode only the circuits needed for power up are powered. This means that only power up block inside the PSL+ is powered. The power key on the flex is pulled up with a pull up resistor inside the PSL+.

Names of Functional Blocks
Name: CTRLU PWRU DSPU AUDIO ASIC RFI Function: Control unit for phone Power supply Digital signal processing block Audio coding D2CA GSM/PCN system ASIC; several functions RF baseband interface

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Clocking Scheme
DSP Clock 60.2 MHz differential sine wave RFI Clock 13 MHz Sleep Mode: 135.4kHz RF System Clock 26 MHz

RFI

VCTCXO

OSCILLATOR
enable

ear mouth

AUDIO CODEC

ASIC
DSP

SIMCLK 3.25 / 1.625 MHz

Codec Sync Clock 8 kHz

Codec Main Clock and data Transfer clock 512kHz

MCU Clock 26 MHz

DBUSCLK 512kHz DBUSSYNC 8kHz

MCU

Most of the clocks are generated from the 26 MHz VCTCXO frequency by the ASIC: ­ 26 MHz clock for the MCU. MCU`s internal clock frequency is half of that (13 MHz). ­ 13 MHz for the RFI. The ASIC also generates 135.4 kHz sleep mode clock for the RFI. ­ 3.25 MHz clock for SIM. When there is no data transfer between the SIM card and the HP the clock can be reduced to 1.625 MHz. Some SIM cards also allows the clock to be stopped in that mode. ­ 512 kHz main clock for the codec and for the data transfer between the DSP and the codec. ­ 8 kHz synchronization clock for data transfer between the DSP and the codec. ­ 512 kHz clock and 8 kHz sync. clock for the DBUS data transfer.

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The DSP has its own crystal oscillator which can be turned off and on by the ASIC. The DSP uses differential sinusoidal clock. The frequency is 60.2 MHz. The system ASIC generates 8 kHz clock to the codec for the control data transfer. In the idle mode all the clocks can be stopped except 26 MHz main clock coming from the VCTCXO.

Reset and Power Control

RFI

reset in

Reset Out Reset Out

ASIC
DSP Vcc Reset in

SIMReset

resetreg

XPWRON

PSL+
VL1 XRES XPWRON XPwrOff approx 2Hz reset in

MCU

There are three different ways to switch power on: ­ Power key pressing grounds the XPWRON line. The PSL+ detects that and switches the power on. ­ Charger detection on PSL+ detects that charger is connected and switches power on. ­ PSL+ will switch power on when the battery is connected. After that the MCU will detect if power key is pressed or charger connected. If not the power will be switched off. All devices are powered up at the same time by the PSL+. It supplies the reset to the ASIC at power up. The ASIC starts the clocks to the DSP and the MCU. After 100 ms PSL+ releases the reset to ASIC.

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ASIC releases MCU and RFI reset after 256 13 MHz clock cycles. DSP reset release time from DSP clock activation can be selected from 0 to 255 13MHz clock cycles. In our case it is 255. SIM reset release time is according to GSM SIM specifications. To turn power off the user presses the PWR key. The MCU detects this. The MCU cuts off any ongoing call, exits all tasks, acts inoperative to the user and leaves the PSL+ watchdog without resets. After power­down delay, the PSL+ cuts off the supply from all circuitry. If charging is on the phone stays on but it looks to the user like it is powered off (lights are off and the display is blank) except the charging indicator stays on.

Watchdog System
4

reset

DSP

ASIC

1 5 2
POWER

4

PSL
XPWROFF

3
MCU

reset

Normal operation: 1. MCU tests DSP 2. MCU updates ASIC watchdog timer (> 2 Hz) 3. MCU pulses the XPWROFF input on the PSL+ (about 2 Hz) Failed operation: 4. ASIC resets MCU and DSP after about 0.5 s failure 5. PSL+ switches power off about 1.5 s after the previous XPWROFF pulse

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CTRLU
The Control block contains a microcontroller unit (MCU) and three memory circuits (FLASH, SRAM, EEPROM), a 20 bit address bus, an 8 bit data bus and memory circuit control signals. Main Features of the CTRLU block: MCU functions: ­ system control ­ communication control ­ user interface ­ authentication ­ RF monitoring ­ power up/down control ­ accessory monitoring ­ battery monitoring and charging control ­ self­test and production testing ­ flash loading Main Components of CTRLU ­ Hitachi H8/536 H8/536 is a CMOS microcontroller unit (MCU) comprising a CPU core and on­chip supporting modules with 16­bit architecture. The data bus to outside world has 8 bits. ­ 1024k*8bit FLASH memory ­ 150 ns. maximum read access time with 1 wait state ­ contains the main program code for the MCU; part of the DSP program code also located on FLASH ­ ASIC can address two 4 Mbit memories or one 8 Mbit memory. ­ 32 k x 8 bit SRAM memory ­ 100 ns. maximum read access time ­ 8 k x 8 bit EEPROM memory ­ 250 ns. maximum read access time with 1 wait state ­ contains user defined information. ­ there is a register bit on the ASIC which must be set before the write operation to the EEPROM.

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Input Signals of CTRLU Name(from): VL1(PWRU) VREF(PWRU) VBATDET(PWRU) VC(PWRU) ROMAD18(ASIC) ROMSELX(ASIC) ROM2SELX(ASIC) RAMSELX(ASIC) RESETX(ASIC) NMI(ASIC) MCUCLK(ASIC) IRQX(ASIC) PCMCDO(AUDIO) TRF(RF) VF(syst.conn.) RXD2_HOOK (syst.conn.) TBAT(batt.conn.) BTYPE(batt.conn.) MIC_JCONN (sys.conn.) Output Signals of CTRLU Name(to): Description: Description: Power supply voltage for CTRLU block Reference voltage for MCU A/D converter Battery voltage detection Charger voltage monitoring ROM address (paging) Chip select for the FLASH memory Chip select for the second FLASH memory Chip select for the SRAM memory Reset signal for MCU Non­maskable interrupt request Main clock for MCU Interrupt request Audio codec control data receiving RF module temperature detection Programming voltage for FLASH memory The use of handsfree monitoring FLASH programming data input on the production line Battery temperature detection. Vibra cont. for vibrabattery. Battery size identification Junction box connection identification

EROMSELX(ASIC) Chip select for the EEPROM memory

XPWROFF(PWRU) Power off control, PSL+ watchdog reset PWM(PWRU) VOLTLIM(PWRU) Charger on/off control Voltage limiting; affects to HW voltage limit level

WSTROBEX(ASIC) MCU write strobe RSTROBEX(ASIC) MCU read strobe MCUAD(19:0)(ASIC) 20 bit MCU address bus MBUSDET(ASIC) MBUS activity detection

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BATDET(ASIC) PCMCLK(AUDIO) PCMCDI(AUDIO) TXD2_PHFS (syst.connector) CALL_LED(UIF) BACKLIGHT(UIF) BUZZER(UIF)

Battery type and SIM card presence detection Clock for audio codec control data transfer Audio codec control data transmitting Power on/off control for HF device, verification output of the programmed data of FLASH during programming 'Incoming' call indicator light control LCD and display backlight on/off control Buzzer signal

XSELPCMC(AUDIO) Chip select for audio codec

Bidirectional Signals of CTRLU Name(to/from): Description:

MCUDA(7;0)(ASIC) MCU's 8 bit data bus M2BUS(sys. conn) Block Description of CTRLU ­ MCU ­ memories The MCU has a 20 bits wide address bus A(19:0) and an 8 bit data bus with memories. The address bits A(19:16) are used for chip select decoding. The decoding is done in the D2CA ASIC. The ASIC can address two 4 Mbit (or smaller) or one 8 Mbit flash memories. Hitachi HD647536 processor has internal ROM and RAM memories. One wait state is used with external memory access. On the Hitachi HD647536 internal memory map there is the following: · 00000 ­ 001FF · 00200 ­ 0F67F · 0F680 ­ 0FE7F · 0FE80 ­ 0FFFF · 10000 ­ 1FFFF · 20000 ­ 2FFFF · 30000 ­ 3FFFF · 40000 ­ 7FFFF · 80000 ­ FFFFF Vector tables 62 k bytes internal ROM 2 k bytes internal RAM 384 bytes register field 32 k * 8 bytes RAM 8 k * 8 bytes EEPROM 26 * 8 bytes ASIC 2 Mbit Flash, paged by ASIC page bit to 4 Mbit 4 Mbit Flash Asynchronous serial data bus

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Chip select generation: Chip select: RAM EEPROM ASIC FLASH1 (8 Mbit) ­ Flash programming In flash programming a special flash programming box and a PC is needed. Loading is done through the bottom connector of HP; multiplexed with HOOK and PHFS line. First MCU goes to minimum mode (MBUS command from PC or if MBUS is connected to MIC_JCONN line in power up). Then the flash software is loaded from PC to flash loading box. When the loading is complete flash loading to HP can be started by MBUS command from PC to the MCU. After that the MCU asks the test box to start flash loading to HP. The box supplies 12 V programming voltage for flash and starts to send 250 bytes data blocks to the MCU via HOOK line. The baud rate is 406 kbit/s. The MCU calculates the check sum, sends acknowledge via PHFS line and sends the data to flash. When all the data is loaded the HP makes reset and tells the flash loading box if the loading was succeeded or not. Only PSL+, ASIC and MCU must be active during the loading. ­ CTRLU ­ PWRU MCU controls the watchdog timer in PSL+. It sends a positive pulse at approximately 2 Hz to XPWROFF pin of the PSL+ to keep the power on. If MCU fails to deliver this pulse, the PSL+ will remove power from the system. MCU also controls the charger on/off switching in the PWRU block. When power off is requested or MCU leaves PSL+ watchdog without reset. After the watchdog time has elapsed PSL+ cuts off the supply voltages from the phone. Page: A19: A18: A17: A16: X X X X 0 0 0 1 0 0 0 X 0 1 1 X 1 0 1 X

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­ CTRLU ­ ASIC MCU and ASIC have a common 8­bit data bus and a 9­bit address bus. Bits A(4:0) are used for normal addressing whereas bits A(19:16) are decoded in ASIC to chip select inputs for CTRLU memories. ASIC controls the main clock, main reset and interrupts to MCU. The internal clock of MCU is half the MCUCLK clock speed. RESETX resets everything in MCU except the contents of the RAM. IRQX is a general purpose interrupt request line from ASIC. After IRQX request the interrupt register of the ASIC is read to find out the reason for interrupt. NMI interrupt is used only to wake up MCU from software standby mode. ­ CTRLU ­ DSPU MCU and DSP communicate through ASIC. ASIC has an MCU mailbox and a DSP mailbox. MCU writes data to DSP mailbox where DSP can only read the incoming data. In MCU mailbox the data transfer direction is the opposite. When power is switched on the MCU loads data from the flash memory to DSP`s external memory through this mailbox. ­ CTRLU ­ AUDIO When the the chip select signal XSELPCMC goes low, MCU writes or reads control data to or from the speech codec registers at the rate defined by PCMCLK. PCMCDI is an output data line from MCU to codec and PCMCDO is an input data line from codec to MCU. ­ CTRLU ­ RF/BATTERY monitoring MCU has internal 8 channel 10 bit AD converter. Following signals are used to monitor battery, charging and RF: ­ BTYPE ­ TBAT ­ VBATDET ­ VC ­ TRF battery size battery temperature (used also for vibrabattery control) battery voltage charging voltage RF temperature

­ CTRLU ­ keyboard and LCD driver interface MCU and user interface communication is controlled through ASIC.

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­ CTRLU ­ ACCESSORIES M2BUS is used to control external accessories. This interface can also be used for factory testing and maintenance purposes. There are also some control and indication signals for the accessories: ­ PHFS is used to turn power on to HF accessories. ­ JCONN is used to indicate that junction box is connected. Phone can also enter minimum mode when M2BUS is connected to MIC_JCONN line. ­ HOOK is used to indicate accessories hook state. ­ TBAT is used to control vibrabattery. (Used also for monitoring battery temperature.)

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PWRU
The power block creates the supply voltages for the baseband block and contains the charging electronics. Main Components of PWRU ­ PSL+ ASIC Generates voltages, contains power on switch, charger and battery voltage detector and watchdog. ­ Transistor BCP69­25 and schottky STPS340U The charging current is passed through these components. ­ Transistor BCX51 and BCP69­25 VL regulators of PSL+ external output transistors. Input Signals of PWRU Name(from): XPWRON(UIF) VOLTLIM(CTRLU) VBATT(syst.conn.) PWM(CTRLU) Description: PWR on switch Voltage limiting; affects HW voltage limit level Battery voltage Charger on/off control

XPWROFF(CTRLU) Power off control

VCHAR(syst.conn.) Charging voltage Output Signals of PWRU Name(from): XRES(ASIC) CHRDET(ASIC) VL1(CTRLU,ASIC, RFI,UIF) VL2(DSPU) VA1(AUDIO,UIF) VA2(RFI) VREF(CTRLU,RF) VC(CTRLU) Description: Master reset Battery charger detection Logic supply voltage, max 150 mA Logic supply voltage, max 150 mA Analog supply voltage, max 40 mA Analog supply voltage, max 80 mA Reference voltage 4.65 V ±2 %, max 5 mA Attenuated VCHAR

VBATDET(CTRLU) Switched VBATT divided by 2

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Block Description of PWRU The PSL+ IC produces the following supply voltages: Name: VL1, VL2 VA1 VA2 VREF Description: 150 mA for logic 40 mA for audios 80 mA for RFI 5 mA reference

In addition, it has internal watchdog, voltage detection and charger detection functions. The watchdog will cut off output voltages if it is not reset once in every 1.5 (±0.75) second. The voltage detector resets the phone if the battery voltage falls below 4.8 V (±0.2 V). The charger detection starts the phone if it is in power­off state when the charging voltage is applied. The charging electronics is controlled by the MCU. When the charging voltage is applied to the phone and the phone is powered up, the MCU detects it and starts controlling charging. If MCU detects too high charging voltage (over 14 volts) or current (over 78 A/D bit difference between VC and VBATDET) it will cut off the charging. The phone will accept charging voltages from 5 to 14 volts. If the phone is in power­off state, the PSL+ will detect the charging voltage and turn on the phone. If the battery voltage is high enough the reset will be released and the MCU will start controlling charging. If the battery voltage is too low the phone stays in reset state and the charging control circuitry will pass charging current to the battery. When the battery voltage has reached 5.25 V (± 0.2 V) the reset will be removed and the MCU starts controlling charging. MCU controls the charging with pulse width modulation output. Charging voltage is limited by hardware in normal operation to 8.9 V and during a call to 7.6 V. Battery and charging voltages are calibrated in production; 6V is fed to the battery and charger pin and the MCU`s A/D converter values are stored to EEPROM.

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DSPU
Main interfaces of the DSP: ­ MCU via ASIC mailbox ­ ASIC ­ audio codec ­ data bus interface (DBUS) for accessories ­ digital audio interface (DAI) for type approval measurements Main features of the DSP block: ­ speech processing ­ speech coding/decoding ­ RPE­LTP­LPC (regular pulse excitation long term prediction linear predictive coding) ­ voice activity detection (VAD) for discontinuous transmission (DTX) ­ comfort noise generation during silence ­ acoustic echo cancellation ­ channel coding and transmission ­ block coding (with ASIC) ­ convolutional coding ­ interleaving ­ ciphering (with ASIC) ­ burst building and writing it to ASIC ­ Reception ­ reading the A/D conversion results from ASIC ­ impulse response calculation ­ matched filtering ­ bit detection (with Viterbi on ASIC) ­ deinterleaving of soft decisions ­ convolutional decoding (with Viterbi) ­ block decoding (with ASIC) ­ Adjacent cell monitoring ­ signal strength measurements ­ neighbor timing measurements ­ neighbor parameter reception

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­ control functions ­ RF controls ­ synthesizer control ­ power ramp programming ­ automatic gain control (AGC) ­ automatic frequency control (AFC) ­ frame structure control ­ control the operations during a TDMA frame (with ASIC) ­ controlling the multiframe structure ­ channel configuration control ­ test functions ­ functions for RF measurements ­ debugging functions for product development Main Components of DSPU ­ AT&T DSP 1616­S11 ­ Digital signal processor with 12 kword internal ROM ­ Two 32 k * 8 70 ns SRAMs for DSP external memory ­ 60.2 MHz crystal osc. to generate differential small signal clock for the DSP Input Signals of DSPU Name(from): VL2(PWRU) DSPCLKEN(ASIC) DSP1RSTX(ASIC) PCMDATRCLKX (ASIC) CODEC_CLK PCMOUT(AUDIO) DBUSCLK DBUSSYNC RDA INT0, INT1(ASIC) PCMCOSYCLKX (ASIC) Description: Logic supply voltage, max 150 mA Clock enable for DSP clock oscillator circuit Reset for the DSP PCM data input clock DBUS data output clock PCM data output clock Received audio in PCM format DBUS data output clock DBUS data bit sync clock DBUS received data Interrupts for the DSP PCM data bit sync clock

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Output Signals of DSPU Name(to): PCMIN(AUDIO) IOX(ASIC) RWX(ASIC) DBUSDET(ASIC) Description: Transmitted audio in PCM format I/O enable, indicates access to DSP address space Read/write X DBUS activity detection

DSPAD(16;9)(ASIC) Address bus and control signals

Bidirectional Signals of DSPU Name(from/to): Description:

DSPDA(15;0)(ASIC) 16 bit data bus Block Description of DSPU The Control unit communicates with the DSP circuitry through a mailbox in the D2CA ASIC. The software for the external memories are loaded through this mailbox in start up. The DSP includes two serial busses. One is used for speech data transfer between the DSP and the codec. The other is used as an external data bus and it is connected to the bottom connector. This bus can be used by data accessories and also as a digital audio interface (DAI) in audio type approval measurements. The clocks (512 kHz main clock and 8 kHz sync. clock) are generated by the ASIC. In transmit mode the DSP codes the speech and routes the resulting transmit slots to the D2CA. The D2CA ASIC controls timing, and at specified intervals sends these bits to the RFI for DA conversion. In digital receive mode the RFI AD converts the IF signal from the RF unit under the control of the D2CA. The DSP controls the D2CA and receives the converted bits. After channel and speech decoding, bits are converted into an analog signal in the PCM codec, routed and fed to the earpiece. The DSP controls the RF through the D2CA ASIC, where all necessary timing functions are implemented, and control I/O lines are provided e.g. for synte loading. The DSP emulator can be connected to DSP pins TCK, TMS, TDO, TDI, GND and VDD.

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AUDIO
The AUDIO block consists of an audio codec with some peripheral components. The codec contains microphone and earpiece amplifier and all the necessary switches for routing. The codec is controlled by the MCU. The PCM data comes from and goes to the DSP. Main Components of AUDIO ­ Audio codec ST5080 Includes e.g. PCM codec, audio routing switches, microphone and earpiece amplifiers for 2 connections (internal and external devices) and DTMF generator. Input Signals of AUDIO Name(from): VA1(PWRU) PCMIN(DSPU) SYNC(ASIC) PCMCDI(CTRLU) PCMCLK(CTRLU) XSELPCMC (CTRLU) MIC_JCONN (syst.conn.) MICN,MICP(UIF) Output Signals of AUDIO Name(to): PCMOUT(DSPU) PCMCDO(CTRLU) MIC_ENA(UIF) EAR_HFPWR (syst.conn.) EARN,EARP(UIF) JCONN(CTRLU) Description: Transmitted audio in PCM format Audio codec control data Microphone enable External received audio Internal received audio Junction box connected signal (multiplexed with HFMIC) Description: Analog supply voltage, max 40 mA Received audio in PCM format 8 kHz frame sync Audio codec control data Clock for audio codec control data transfer Audio codec chip select External microphone Differential microphone signal

CODEC_CLK(ASIC) 512 kHz codec main clock

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Block Description of AUDIO The codec has two microphone inputs and two earphone outputs. Handportable and external audios can therefore be connected directly to the codec. The codec has internal switches to select which input or output is used. It also has microphone amplifier and earphone attenuator. Input/output selection and amplification/attenuation can be done with codec register settings. The register control is done by the MCU. Handportable microphone and earphone (located on the flex) are connected directly to the codec`s differential input and output. External audios are connected single sided. There is 21 dB attenuation in the external microphone line before the codec to prevent clipping. Microphone signal is routed to the microphone amplifier. After that it is fed to the bandpass filter and then to the A/D converter. After the conversion the digital speech is sent to the DSP. Digital downlink signal from the DSP is fed to the D/A converted. After the converter there is low pass filter and attenuator before the earphone output. All these are inside the codec. The ASIC generates the 512 kHz and 8 kHz clocks for the codec and data transmission between the codec and the DSP The audio codec communicates with the DSP (analog speech) through an SIO (signals: PCMIN, SYNC, CODEC_CLK and PCMOUT) . The MCU controls the audio codec function through a separate serial bus (signals: PCMCDO, PCMCDI, PCMCLK and XSELPCMC). The codec generates DTMF tones (key beeps) to the earphone and in HF mode to the external speaker. In portable mode the MCU generates ringing tones and also some warning tones to the buzzer. In HF mode they are generated by the codec and driven to the external speaker line. Several tones are network originated. Depending on network transceiver is either commanded to generate tone, or network sends the tone itself. One codec output pin is used to switch on/off the microphone bias circuit on the flex. External microphone line is used also to detect if junction box is connected to the bottom connector. Microphone signal is therefore routed to the MCU A/D converter. Also external earphone signal is multiplexed. 100 k pull down resistor is used to turn power on to the HF accessories.

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ASIC
The ASIC takes care of the following functions: ­ interface between MCU and UIF ­ interface between MCU, DSP and RFI ­ hardware accelerator functions to DSP ­ clock generation and disable/enable ­ RF controls ­ UIF interface ­ timers ­ M2BUS interface ­ SIM interface Main Components of ASIC ­ D2CA ASIC ­ RFC buffer Inverter buffer stage is used as a buffer for the VCTCXO clock. Input Signals of ASIC Name(from): VL1(PWRU) VL2(PWRU) CHRDET(PWRU) IOX(DSPU) RWX(DSPU) WSTROBEX (CTRLU) RSTROBEX (CTRLU) RFC(RF) XRES(PWRU) Description: Logic supply voltage, max 150 mA Logic supply voltage, max 150 mA Battery charger detection I/O enable, indicates access to DSP address space Read/write X MCU's write strobe MCU's read strobe Reference clock from VCTCXO Master reset

DSPAD(16;0)(DSPU)Address bus and control signals MCUAD(19;16,4;0) MCU's address bus (CTRLU) DAX(RFI) BATDET(CTRLU) Data acknowledge Battery type and SIM card presence detection

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MBUSDET(CTRLU) MBUS activity detection DBUSDET(DSPU) Output Signals of ASIC Name(to): INT0,INT1(DSPU) NMI(CTRLU) IRQX(CTRLU) RESETX (CTRLU,RFI) SIMRESET WRX(RFI) RDX(RFI) RFIAD(3;0)(RFI) SCLK(RF) SDATA(RF) SENA1(RF) RXPWR(RF) TXPWR(RF) SYNTHPWR(RF) TXP(RF) MCUCLK(CTRLU) RFICLK(RFI) RFI2CLK(RFI) CODEC_CLK (DSPU,AUDIO) PCMDATRCLKX (DSPU) SYNC(AUDIO) PCMCOSYCLKX (DSPU) DCLK(syst.conn.) Description: Interrupts for DSP Not maskable interrupt request Interrupt request Master (power µp) reset DBUS activity detection

DSP1RSTX(DSPU) Reset for the DSP Reset for the SIM Write strobe Read strobe RFI address bus Synthesizer load clock Synthesizer load data UHF and VHF PLL enable RX circuitry power enable TX circuitry power enable Synthesizer circuitry power enable Transmitter power control enable Main clock for MCU RFI master clock RFI sleep clock PCM data clock Inverted PCM data clock, used as input clock for codec and DBUS interface Bit sync clock Bit sync clock, inverted DBUS data clock

DSPCLKEN(DSPU) DSP clock circuit enable

DSYNC(syst.conn.) DBUS bit sync clock

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DBUSCLK(DSPU) SIMCLK(UIF) VSIM(UIF)

DBUS data clock SIM data clock SIM power control

DBUSSYNC(DSPU) DBUS bit sync clock

ROMAD18(CTRLU) ROM address (paging) ROMSELX(CTRLU) Chip select for the FLASH memory ROM2SELX (CTRLU) EROMSELX (CTRLU) COL(3;0)(UIF) Bidirectional Signals of ASIC Name(from/to): DSPDA(15;0) (DSPU) MCUDA(7;0) (CTRLU) RFIDA(11;0)(RFI) UIF(6;0)(UIF) SIMDATA(UIF) Description: 16 bit data bus MCU's 8 bit data bus 12 bit data bus LCD controller control and keyboard read bus Serial data to SIM Chip select for the second FLASH memory Chip select for the EEPROM memory

RAMSELX(CTRLU) Chip select for the SRAM memory Lines for keyboard column write

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Block Description of ASIC PSL+ supplies the reset to the ASIC at power up. The ASIC starts the clocks to the DSP and the MCU. MCU and RFI reset is released after 256 13 MHz clock cycles. DSP reset release time from DSP clock activation can be selected from 0 to 255 13 MHz clock cycles. In our case 255 is selected. SIM reset release time is according to GSM SIM specifications. The RFC buffer buffers the 26MHz clock from the VCTCXO to the ASIC. In the ASIC the clock is further buffered and divided for the MCU, RFI, SIM. It also generates main and sync clocks for audio codec, DSP`s SIOs and DBUS. The clock outputs can be disabled in order to save current when the clock is not needed. Also the DSP oscillator can be stopped by the ASIC. Interface to the MCU is done with 8 bit data bus ,5 bit lower address bus, 4 bit upper address bus, RSTRBEX, WSTROBEX, IRQX and NMI. ASIC is in the same memory space as MCU memories. The ASIC generates chip selects from the address bits A16­19. There is also M2BUS detector and netfree counter on the ASIC. Netfree interrupt IRQX occurs if no activity is detected in M2BUS in about 3ms. NMI is used to wake up the MCU from sleep mode. MCU and DSP communicate through ASIC. ASIC has an MCU mailbox and a DSP mailbox. MCU writes data to DSP mailbox where DSP can only read the incoming data. In MCU mailbox the data transfer direction is the opposite. The size of the mailbox is 64 * 8 bit. MCU and User Interface (keyboard and display) communication is controlled through the ASIC. COL(0­3) are used as column lines in keyboard. UIF(0­5) are used as row lines They are also multiplexed with display driver control signals. When a key is pressed the ASIC generates an interrupt from low input of row and starts scanning. One column at the time is written to low and rows are used to read which key it was. Row lines and UIF6 are used for display driver control. UIF(0­3) are used as 4 bit parallel data bus for the LCD driver. UIF4 is used as read/write strobe, UIF5 to select data or instruction register and UIF6 as enable strobe. The SIM interface is the electrical interface between the smart card used in the GSM and PCN applications and the MCU via the ASIC. ASIC converts the serial data received from the SIM to parallel data for MCU and converts parallel data from MCU to serial mode for the card. The SIM interface also takes care of the power up and down procedure to the card, frame and parity error checking. The communication between card and ASIC is asynchronous and half duplex. Four signals are used between the ASIC and the SIM card: SIMDATA, SIMCLK, SIMRESET and The clock frequency is 3.25 MHz. When there is no data transfer between the SIM card and the HP the clock can be reduced to 1.625 MHz. Some SIM cards also allows the clock to be stopped in that mode. Supply voltage VSIM can be switched off by the ASIC. The supply voltage is 4.65 V. The carddetect input on the ASIC is connected to BTYPE pin and when the battery is removed the ASIC will drive the SIM down.

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The interface to the DSP is done using 6 bit address bus, 16 bit data bus, IOX and RWX lines. Data bus is latched using IOX, address bus is not. The ASIC also generates interrupt INT0 when an edge occurs in DBUS line (if the mask bit is off). INT1 is used as RX interrupt and as MFI modulator interrupt to the DSP. Viterbi is used to perform GSM/PCN convolutional decoding and bit detection according to viterbi algorithm. It can be controlled and accessed thoroughly by the DSP. Coder is used to perform block encoding, decoding, and ciphering according to GSM algorithm A5 or A5/2. (D2CA supports both algorithms.) The ASIC takes care of the interface between the DSP and the RFI: TX modulator, RX filter, TX and RX sample buffers and controlling state machine. The interface to RFI is done using 12 bit data bus, 4 bit address bus, RDX and WRX. There is data acknowledge (DAX) from RFI to ASIC. Also in this block are the serial RF synthesizer interface (SCLK, SDAT) and the digital RF control signals (RXPWR, TXPWR, TXP, SYNTHPWR).

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RFI
The block consists of RFI ASIC and its reference voltage generator. This block is an interface between RF and baseband. The RFI block has the following functions: ­ IF receiving and A/D conversion ­ I/Q separation ­ I and Q transmit and D/A conversion ­ AFC D/A ­ TXC ­ AGC (in combination with TXC) Main Components of RFI ­ RFI ASIC ­ 4.096 V external voltage reference LM4040 for RFI Input Signals of RFI Name(from): VL1(PWRU) VA2(PWRU) RESETX(PWRU) RFIAD(3;0)(ASIC) RDX(ASIC) WRX(ASIC) RFICLK(ASIC) RFI2CLK(ASIC) RXQ(RF) RXI(RF) Description: Logic supply voltage, max 150 mA Analog supply voltage, max 80 mA Master (power up) reset RFI address bus Read strobe Write strobe RFI master clock RFI sleep clock RX quadrature signal RX inphase signal

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Output Signals of RFI Name(to): DAX(ASIC) AFC(RF) TXC(RF) TXQP,TXQN(RF) TXIP,TXIN(RF) PDATA0(RF) Bidirectional Signals of RFI Name(to): Description: Description: Data acknowledge Automatic frequency control voltage TX transmit power control voltage, AGC control Differential TX quadrature signal Differential TX inphase signal Front end AGC data

RFIDA(11;0)(ASIC) 12 bit data bus Block Description of RFI The RFI provides A/D conversion of the in­phase (RXI) and quadrature (RXQ) signals in receive path. It has 12 bit sigma­delta A/D converters and the sample rate is 541.667 kHz. Analog transmit path includes 8 bit D/A converters to generate the in­phase (TXI) and quadrature (TXQ) signals. RFI has differential outputs for TXI and TXQ. The sample rate is 1.0833 MHz. There is 11 bit D/A converter for automatic frequency correction. The sample rate is 1.3542 kHz. Power ramp is done with 10 bit D/A converter. The sample frequency is 1.0833 MHz. The AGC is voltage controlled in HD841. (In HD740 AGC control was digital.) Front end AGC control is done with PDATA0 output. Main part of AGC is controlled by TXC. The RFI has 12 bit data bus to the ASIC. The registers in the RFI are accessed using 4 address bits. Control and clock signals are coming from the ASIC. The RFI has external 4.096 V voltage reference.

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Functional Description of RF block
The RF block carries out all the RF functions of the transceiver. The RF block works in GSM system.

RF Frequency Plan GSM
935­960 1st IF 71 58 LO 1 1006­ 1031 2nd IF 13 CRFRT

f f/2 f/2

f

LO 2 232

116 890­915 f/2

f

PLL

VCXO: 26 MHz (I) 13 MHz (H)

Regulators
There is one regulator IC in the RF unit. The regulator IC CRFCONT is an RF power supply circuit basically intended for digital handportable phones. It has 8 separate linear regulators. Each regulator can be individually disabled and enabled. It also has a voltage reference output. See more details on Figure; Power Distribution Diagram of RF

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Power Distribution
All currents in the power distribution diagram are peak currents. Activity percentages are in SPEECH­mode 24.6 % for RXPWR, 15.8 % for TXPWR and 100 % for SYNTHPWR. In IDLE­mode activities are 0.4 %, 0.0 % and 1.77 % respectively. The current of each block is controlled independently and for example TXPWR and RXPWR are not on at the same time.

Current Consumption
In the following table the RF current consumption can be seen with different status of the control signals. The VCTCXO is not included in the results. SYNTHPWR: RXPWR: TXPWR: TXP: Typ. load current: Notes: L H H H H L L H L L L L L H H L L L L H 0.05 mA 41.5 mA 115.5 mA 93.5 mA 1393.5 mA Leakage current Synthesizer active Reception TX active Transmission

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Receiver
The receiver is a double conversion receiver. The received RF signal from the antenna is fed via a duplex filter to the receiver unit. The signal is amplified by a discrete low noise preamplifier. The gain of the amplifier is controlled by the AGC control line (PDATA0). The nominal gain of 16.5 dB in GSM is reduced in the strong field condition about 36 dB. After the preamplifier the signal is filtered by SAW RF filter. The filter rejects spurious signals coming from the antenna and spurious emissions coming from the receiver unit. In GSM the filtered RF signal is down converted by a passive diode mixer. The frequency of the first IF is 71 MHz. The first local signal is generated by the UHF synthesizer. The IF signal 71 is amplified and filtered by SAW filter in GSM. The filter rejects adjacent channel signal, intermodulating signals and the last IF image signal. The filtered IF signal is fed to the receiver part of the integrated RF circuit CRFRT. In CRFRT the filtered IF signal is amplified by an AGC amplifier which has gain control range of 57 dB. The gain is controlled by an analog signal via TXC line. The amplified IF signal is down converted to the last IF in the mixer of CRFRT. The last local signal is generated from VHF VCO by dividing the original signal by 4 in the dividers of CRFRT. The last IF 13 MHz is filtered by a ceramic filter. The filter rejects signals of the adjacent channels. The filtered last IF is fed back to CRFRT where it is amplified and fed out via RXIF line. IF signal is split to +45 and ­45 signals and then fed to RFI. Duplex Filter The duplex filter consists of two functional parts; RX and TX filters. The TX filter rejects the noise power at the RX frequency band and TX harmonic signals. The RX filter rejects blocking and spurious signals coming from the antenna.

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Pre­Amplifier The bipolar pre­amplifier amplifies the received signal coming from the antenna. In the strong field conditions the gain of the amplifier is reduced 36 dB in GSM, typically. Parameter Frequency band: Supply voltage (min/typ/max): Current consumption (min/typ/max): Insertion gain (min/typ/max): Gain flatness: Noise figure (typ/max): Reverse isolation (min): Gain reduction (min/typ/max): IIP3: (min/typ): Input VSWR; zo=50 (max): Output VSWR; zo=50 (max): RX Interstage Filter The RX interstage filter is a SAW filter in GSM. The filter rejects spurious and blocking signals coming from the antenna. It rejects the local oscillator signal leakage, too.

Value 935­960 Mhz 4.27...4.5...4.73 V 5...6....7 mA 15...16.5...17 dB
±0.5 dB

2.0...2.5 dB 15 dB 33...36...39 dB ­12...­10 dBm 2.0 2.0

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First Mixer The first mixer is a single balanced passive diode mixer. The local signal is balanced by a printed circuit transformer. The mixer down converts the received RF signal to IF signal. Parameter RX frequency range: LO frequency range: IF frequency: Conversion loss (min/typ/max): IIP3 (min/typ): LO ­ RF isolation (min): LO power level (min): First IF Amplifier The first IF amplifier is a bipolar transistor amplifier. Parameter Operation frequency: Supply voltage (min/typ/max): Current consumption (typ/max): Insertion gain (min/typ/max): Noise figure (typ/max): IIP3 (min/typ): First IF filter The first IF filter is a SAW filter in GSM. The IF filter rejects some spurious and blocking signal coming from the front end of the receiver.

Value 935­960 Mhz 1006­1031 Mhz 71 Mhz 5...6...7 dB 2...5 dBm 15.0 dB 3 dBm

Value 71 Mhz 4.27...4.5...4.73 12...20 mA 18...20...22 dB 3.5...4.0 dB ­5...­3 dBm

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Receiver IF circuit, RX part of CRFRT The receiver part of CRFRT consists of an AGC amplifier of 57 dB gain, a mixer and a buffer amplifier for the last IF. The mixer of the circuit down converts the received signal to the last IF frequency. After external filtering the signal is amplified and fed to baseband circuitry. The supply current can be switched OFF by an internal switch, when the RX is OFF. Parameter Supply voltage (min/typ/max): Current consumption (max/max): Input frequency range (min/max): Local frequency range of mixer (min/max): 2nd IF range (min/max): Voltage gain (max gain) of AGC amplifier (min): Noise figure (max): AGC gain control slope (min/typ/max): Mixer output 1 dB compression point (typ):

Value 4.27...4.5...4.73 V 35...44 mA 45 MHz (­1 db point) ...87 MHz (­3 dB point) 170...400 MHz 2...17 MHz 47 dB 15 max gain 40...84...100 dB/V 1.0 VPP

Max output level after last IF buffer (typ): 1.6 VPP Last IF Filter The last IF is a ceramic filter, which makes the part of the channel selectivity of the receiver.

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Transmitter
The TX intermediate frequency is modulated by an I/Q modulator contained on transmitter section of CRFRT IC. The TX I and Q signals are generated in the RFI interface circuit and they are fed differentially to the modulator. Modulated intermediate signal is amplified or attenuated in temperature compensated controlled gain amplifier (TCGA). The output of the TCGA is amplified and the output level is typically ­10 dBm. The output signal from CRFRT is band­pass filtered to reduce harmonics and the final TX signal is achieved by mixing the UHF VCO signal and the modulated TX intermediate signal with passive mixer. After mixing the TX signal is amplified and filtered by two amplifier and one filter. This filter is dielectric filter. After these stages the level of the signal is typically 1 mW (0 dBm). The discrete power amplifier amplifies the TX signal to the desired power level. The maximum output level is typically 1.8...2.0 W. The power control loop controls the output level of the power amplifier. The power detector consists of a directional coupler and a diode rectifier. Transmitted power is controlled with controlled gain amplifier (TCGA) on TX path of CRFRT. Power is controlled with TXC and TXP signals. The power control signal (TXC), which has a raised cosine form, comes from the RF interface circuit, RFI. Modulator Circuit, TX part of CRFRT The modulator is a quadrature modulator contained in TX section of CRFRT IC. The I­ and Q­ inputs generated by RFI interface are D.C. coupled and fed via buffers to the modulator. The local signal is divided by two to get accurate 90 degrees phase shifted signals to the I/Q mixers. After mixing the signals are combined and amplified with temperature compensated controlled gain amplifier (TCGA). Gain is controlled with power control signal (TXC). The output of the TCGA is amplified and the maximum output level is ­10 dBm, typically. Parameter Supply voltage (min/typ/max): Supply current (typ/max): Transmit frequency input LO input frequency (min/max): LO input power level (typ): LO input resistance (min/typ/max): LO input capacitance (typ):

Value 4.27...4.5...4.73 V 36...45 mA Value 170...400 MHz 0.2 VPP 70...100...130 4 pF

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Modulator Inputs (I/Q): Input bias current, balanced (max): Input common mode voltage (min/typ/max): Input level, balanced (max): Input frequency range (min/max): Input resistance, balanced (min): Input capacitance, balanced (max): Modulator Output: Output frequency (min/max): Available linear RF power (typ): Available saturated RF power (min/typ): Total gain control range (min): Gain control slope (typ): Suppression of 3rd order prods (min): Carrier suppression (typ): Single sideband suppression: Noise floor POUT · ­10 (max): · ­18 (max): · ­24 (max): · ­30 (max): · ­40 (max): Transmitted I/Q phase balance: drift in whole temperature range: Transmitted I/Q amplitude balance: drift in whole temperature range:

Value 100 nA 2.0...2.2...2.4 V 1.1 VPP 0...300 kHz 200 k 4 pF Value 85...200 MHz ­10 dBm, ZiL=50 k ­5...0 dBm, ZiL=50 k 45 dB 84 dB/V 35 dB 35 dB

­132 dBm/Hz avg. ­137 dBm/Hz avg. ­140 dBm/Hz avg. ­142 dBm/Hz avg. ­144 dBm/Hz avg. ­5...5 deg ­2...2 deg ­0.5...0.5 dB ­0.2...0.2 dB

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Upconversion Mixer The upconversion mixer is a single balanced passive diode mixer. The local signal is balanced by a printed circuit transformer. The mixer upconverts the modulated IF signal coming from quadrature modulator to RF signal. Parameter: RX frequency range: LO frequency range: IF frequency (nom): Conversion loss (min/typ/max): IIP3 (min): LO ­ RF isolation (min): LO power level (min): TX Interstage Filters The TX filters reject the spurious signals generated in the upconversion mixer. They reject the local, image and IF signal leakage and RX band noise, too. 1st TX buffer The TX buffer is a bipolar transistor amplifier. It amplifies the TX signal coming from the upconversion mixer. Parameter: Operating frequency range: Supply voltage (min/typ/max): Current consumption (typ/max): Insertion gain (min/typ/max): Input VSWR, Zo=50 (max): Output VSWR, Zo=50 (max):

Value 890...915 MHz 1006...1031 MHz 116 MHz 6.0...7.0...8.0 dB 0.0 dBm 15 dB 3.0 dBm

Value 890...915 MHz 4.25...4.5...2.8 V 4.5...5.0 mA 11...12...13 dB 2.0 2.0

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2nd TX buffer The TX buffer is a bipolar transistor amplifier. It amplifies the TX signal coming from the first interstage filter. Parameter: Operation frequency range: Supply voltage (min/typ/max): Current consumption (typ/max): Insertion gain (min/typ/max): Output power, Zo=50 (min/typ): Input VSWR, Zo=50 (max): Output VSWR, Zo=50 (max): Power Amplifier The power amplifier is a three stage discrete amplifier. It amplifies the 0 dBm TX signal to the desired output level. It has been specified for 6 volts operation. Parameter: D.C. supply voltage, no RF (max): D.C. supply voltage (min/typ/max): Operation frequency: Operating case temp. range (max): Max output power (min/typ/max): Max output power (min/typ/max): Input power (min): Gain (min/typ/max): Efficiency (typ): Input VSWR, Zo=50 (max): Output VSWR, Zo=50 (max): Harmonics, 2 fo: 3 fo, 4 fo, 5 fo: Noise power (max): Ruggedness (min): Stability, load VSWR 6:1 (min):

Value 890...915 MHz 4.25...4.5...4.8 V 9.0...10.0 mA 11...12...13 dB 0...3 dBm 2.0 2.0

Value 10 V 5.3...6.0...8.5 V 890...915 MHz 90 °C 34.5...35...36 dBm, norm cond. 33.5...34...35 dBm, extreme cond. VCC =5.4 V, Ta=55°C 0 dBm 34.5...35...36 dB 42 %, Po=35 dBm 2.0 2.0 ­30 dBc, Po=35 dBm ­40 dBc, Po=35 dBm ­114 dBm at receiver band 8 V VSWR=7, POUT =4 W 60 dBc, all spurious

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Power Control Circuitry The power control loop consists of a power detector and a differential control circuit. The power detector is a combination of a directional coupler and a diode rectifier. The differential control circuit compares the detected voltage and the control voltage (TXC) and controls voltage controlled amplifier (in CRFRT) or the power amplifier. The control circuit is a part of CRFRT. Parameter: Supply voltage (min/typ/max): using CRFRT: Supply current (typ/max): Power control range (min): Power control inaccuracy (max): Dynamic range (min): Input control voltage range (min/max):

Value 4.5...4.7...4.9 4.27...4.5...4.73 3.0...5.0 mA 20 dB
±1.0 dB

80 dB 0.1...2.8 V

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Synthesizer
The stable frequency source for the synthesizers and base band circuits is discrete voltage controlled crystal oscillator, VCXO. The frequency of the oscillators is controlled by an AFC voltage, which is generated by the base band circuits. The UHF PLL generates the down conversion signal for the receiver and the up conversion signal for the transmitter. The UHF VCO is a discrete oscillator. The PLL circuits is UMA1018. The VHF PLL signal (divided by 4 in CRFRT) is used as a local for the last mixer. Also the VHF PLL signal (divided by 2 in CRFRT) is used in the I/Q modulator of the transmitter chain. Reference Oscillator The reference oscillator is a discrete VCXO and the frequency is 26 MHz. The oscillator signal is used for a reference frequency of the synthesizers and the clock frequency for the base band circuits. Parameter: Centre frequency: Frequency control range: Supply voltage (min/typ/max): Current consumption (typ/max): Output voltage (min/typ/max): Harmonics (max): Control voltage range (min/max): Nominal voltage for centre frequency: Control sensitivity (min/typ/max): Frequency stability · temperature: · supply voltage: · load: · aging: Load impedance, resistive part: parallel capacitance:

Value 26 MHz 67 ppm 4.6...4.7...4.8 V 1.5..1.7 mA 1.3...1.7...2.0 VPP, sine wave for PLLs 5 dBc 0.25...4.45 V 2.2 V 12...16...22 ppm/V 10 ppm, ­25...+75 °C 1 ppm, 4.7 V ±5 % 0.1 ppm, load ±10 % 1 ppm, year 2 k 20 pF

Operating temperature range (min/max): ­20...70 °C

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VHF PLL The VHF PLL consists of the VHF VCO, PLL integrated circuit and loop filter. The output signal is used for the 2nd mixer of the receiver and for the I/Q modulator of the transmitter. Parameter: Start up setting time (max): Phase error (max): Sidebands (typ/max) · ±200 kHz: · ±400 kHz: · ±1 MHz: · ±2 MHz: · ±3 MHz: · >4 MHz: VHF VCO + buffer The VHF VCO uses a bipolar transistor as a active element and a combination of a chip coil and varactor diode as a resonance circuit. The buffer is combined into the VCO circuit so, that they use same collector current. Parameter: Supply voltage (min/typ/max): Control voltage (min/max): Supply current (typ/max): Operation frequency (typ): Output power level (typ): Control voltage sensitivity (typ): Phase noise (max) · fo ±200 kHz · fo ±1600 kHz · fo ±3000 kHz Harmonics (typ/max):

Value 5 ms 1 deg., rms ­75...­70 dB ­84...­70 dB <­85...­70 dB <­85...­75 dB <­85...­80 dB <­85...­80 dB

Value 4.2...4.5...4.8 V 0.5...4.0 V 2.5...5.0 mA 232 MHz 168 mVRMS /1 k 12 MHz/V ­123 dB ­133 dB ­143 dB ­32...­30 dB

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UHF PLL The UHF PLL consists of a UHF VCO, PLL circuit and a loop filter. The output signal is used for the 1st mixer of the receiver and the upconversion mixer of the transmitter. Parameter: Start up setting time (max): Phase error (max): Settling time ±93 MHz (typ/max): Sidebands (typ/max) · ±200 kHz: · ±400 kHz: · ±600 kHz: · 1.4...3.0 MHz: · >3.0 MHz: UHF VCO + buffer The UHF VCO uses a bipolar transistor as a active element and a combination of a chip coil and a varactor diode as a resonance circuit. UHF VCO Buffers The UHF VCO output signal is divided into the 1st mixer of the receiver and the upconversion mixer of the transmitter. The UHF VCO signal is amplified after division. There is one buffer for TX and one for RX. Parameter: Supply voltage (min/typ/max): Supply current (typ/max): Input power (typ): Harmonics (max): Output power (typ):

Value 5 ms 4 deg., rms 525...800 µs ­80...­60 dB ­87...­65 dB <­90...­70 dB <­90...­80 dB <­80 dB

Value 4.2...4.5...4.8 V 5.5...6.5 mA ­3 dBm ­10 dBc 700 mVRMS /1 k

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PLL Circuit The PLL is PHILIPS UMA1018. The circuit is a dual frequency synthesizer including both the UHF and VHF synthesizers. Parameter: Supply voltage (min/max): Supply current (typ): Principal input frequency (min/max): Auxiliary input frequency (min/max): Input reference frequency (min/max): Input signal level (min/max):

Value 2.7...5.5 V 8.5 mA 500...1200 MHz, VDD = 4.5 V 20...300 MHz, VDD = 4.5 V 3...40 MHz, VDD = 4.5 V 50...500 mVRMS

SYSTEM MODULE GR8 01/98OJ Technical Documentation

NHE­4 8­48 Copyright © Nokia Mobile Phones

Block Diagram of Baseband

RFI UIF­module
32K x 16 SRAM

RF

ear

mic

DBUS
A14:0, D15:0
sio DSP

12 bit parallel + 8 x control

UIF­module
SIM CARD READER

sio PCM CODEC

sio

ext mem

ASIC
A5:0, D15:0
LCD DRIVER

LCD

A4:0, A19:16, D7:0

xmic xear
A17:0,D7:0 A12:0,D7:0 A14:0,D7:0

A19:0,D7:0
PSL+ CHRGR FLASH LOAD

io io ext mem sio MCU
M2 BUS Interface

sio

E2PROM 8K X 8

1024K x 8 FLASH

32K x 8 SRAM

SYSTEM MODULE GR8 01/98OJ Technical Documentation

NHE­4 8­49 Copyright © Nokia Mobile Phones

Power Distribution Diagram of Baseband

PSL+ VBATT
VL1 VL2 VA2 VL1 VA1 VA2 VREF RFI RF VREF VBATT

VCHAR
UIF­module VL2
32Kx16 SRAM

VL2 VL1 DSP

VBATT VL1 VL2 ASIC VA1
LCD Driver

LCD

VL1

VA1
PCM CODEC

VREF

VL1

VL1
E2PROM 8K x 8

VL1
512K x 8 FLASH

VL1
32K x 8 SRAM

MCU

PCN CRFRT product H

H no external antenna
90 deg

product I

step AGC (25 ­ 30 dB) f f/2 f/2 UHF VCO PLL f f/2 clipped sinewave product H sinewave to ASIC Product I TX power control TXC TXP AFC VHF VCO f

Block Diagram of RF

(21 ­ 27 dB PCN)

01/98OJ

SYSTEM MODULE GR8

Technical Documentation

VCTCXO/ VCXO

CRFCONT

+6 V

+4.5V

PCN

PCN

Batt.volt.

+6 V PCN

TXIP TXIN

­4 V

TXP

BIAS TXP (GSM)

TXQP TXC TXQN

8­50 Copyright © Nokia Mobile Phones

NHE­4

SYSTEM MODULE GR8 01/98OJ Technical Documentation

NHE­4 8­51 Copyright © Nokia Mobile Phones

Power Distribution Diagram of RF

Battery 6V (min 5.3 V)

VCXO

2 mA

VREF

Switch

TXP

Power Amplifier

GSM: 1300 mA PCN: 900 mA

CRFCONT

Vbias

VR1

VR2

VR3

VR4

VR5

VR6

VR7

VR8

SYNTHPWR TXPWR RXPWR

+4V5_TX: TX buffers GSM: 13 mA PCN: 21 mA

VHLO: VHF LO GSM: 8 mA PCN: 17 mA

VPLL: PLL­IC Negat.volt. 18.5 mA

+4V5_RX: RF LNA IF amps GSM: 18 mA PCN: 31 mA

VTX: CRFRT (VTX) CRFRT (VTX_slow) 39 mA VRX: CRFRT (VRX) 35 mA

CRFRT (VB_ext)

VB_EXT

< 1 mA

VREF
PSL

SYSTEM MODULE GR8 01/98OJ Technical Documentation

NHE­4 8­52 Copyright © Nokia Mobile Phones

Connections between System and RF Blocks
Version: 5.0 Edit: 111

SYSTEM MODULE GR8 01/98OJ Technical Documentation

NHE­4 8­53 Copyright © Nokia Mobile Phones

Connections between RX and TX Blocks
Version: 6.0 Edit: 73

SYSTEM MODULE GR8 01/98OJ Technical Documentation

NHE­4 8­54 Copyright © Nokia Mobile Phones

Circuit Diagram of GR8; System Blocks

SYSTEM MODULE GR8 01/98OJ Technical Documentation

NHE­4 8­55 Copyright © Nokia Mobile Phones

Circuit Diagram of GR8; CPU & Memories

SYSTEM MODULE GR8 01/98OJ Technical Documentation

NHE­4 8­56 Copyright © Nokia Mobile Phones

Circuit Diagram of GR8; Power Supply IC & Batt. Charg. unit

SYSTEM MODULE GR8 01/98OJ Technical Documentation

NHE­4 8­57 Copyright © Nokia Mobile Phones

Circuit Diagram of GR8; DSP, Clock Generator & Memories

SYSTEM MODULE GR8 01/98OJ Technical Documentation

NHE­4 8­58 Copyright © Nokia Mobile Phones

Circuit Diagram of GR8; Audio Codec IC

SYSTEM MODULE GR8 01/98OJ Technical Documentation

NHE­4 8­59 Copyright © Nokia Mobile Phones

Circuit Diagram of GR8; ASIC IC

SYSTEM MODULE GR8 01/98OJ Technical Documentation

NHE­4 8­60 Copyright © Nokia Mobile Phones

Circuit Diagram of GR8; RFI IC

SYSTEM MODULE GR8 01/98OJ Technical Documentation

NHE­4 8­61 Copyright © Nokia Mobile Phones

Circuit Diagram of GR8; RF Receiver and Regulator

SYSTEM MODULE GR8 01/98OJ Technical Documentation

NHE­4 8­62 Copyright © Nokia Mobile Phones

Circuit Diagram of GR8; RF Transmitter

SYSTEM MODULE GR8 01/98OJ Technical Documentation

NHE­4 8­63 Copyright © Nokia Mobile Phones

Layout Diagram of GR8 Side 1 Version 09

SYSTEM MODULE GR8 01/98OJ Technical Documentation

NHE­4 8­64 Copyright © Nokia Mobile Phones

Layout Diagram of GR8 Side 2 Version 09

SYSTEM MODULE GR8 01/98OJ Technical Documentation

NHE­4 8­65 Copyright © Nokia Mobile Phones

Parts List of GR8
ITEM R070 R071 R072 R073 R074 R075 R076 R077 R078 R079 R110 R111 R112 R113 R114 R140 R141 R142 R143 R144 R145 R146 R147 R148 R149 R150 R151 R152 R160 R161 R162 R163 R164 R165 R166 R169 R170 R171 CODE 1430788 1430794 1430754 1430764 1430730 1430804 1430744 1430796 1430796 1430804 1430842 1430840 1430804 1430804 1430732 1430792 1430788 1430778 1430764 1430764 1430732 1430846 1430844 1430762 1430762 1430778 1430804 1430778 1430726 1430770 1430778 1430726 1430788 1430804 1430804 1430804 1430804 1430788

(EDMS Issue: 6.8 Code: 0200514) VALUE 22 k 39 k 1.0 k 3.3 k 150 100 k 470 47 k 47 k 100 k 680 k 220 k 100 k 100 k 180 33 k 22 k 10 k 3.3 k 3.3 k 180 2.7 k 3.9 k 2.2 k 2.2 k 10 k 100 k 10 k 100 4.7 k 10 k 100 22 k 100 k 100 k 100 k 100 k 22 k TYPE

DESCRIPTION Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor

5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 1 % 0.063 W 0402 1 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 1 % 0.063 W 0402 1 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402 5 % 0.063 W 0402

SYSTEM MODULE GR8 01/98OJ Technical Documentation

NHE­4 8­66 Copyright © Nokia Mobile Phones

R172 R173 R174 R175 R176 R177 R178 R179 R180 R181 R182 R183 R184 R185 R186 R190 R191 R192 R193 R194 R195 R196 R197 R198 R199 R210 R230 R231 R232 R233 R234 R235 R236 R237 R238 R239 R240 R241 R243 R246 R247 R248

1430798 1430794 1430754 1430700 1430726 1430726 1430726 1430726 1430762 1430726 1430726 1430734 1430726 1430726 1430726 1430726 1430754 1430754 1430754 1430754 1430754 1430754 1430754 1430804 1430804 1430754 1430804 1430804 1430842 1430788 1430778 1430762 1430762 1430762 1430762 1430762 1430762 1430744 1430788 1430804 1430762 1430726

Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Ch