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EXTDATA(0:31)
PAL_A_V(0:2)
UARTDO(0:5)
OSD PAL SYNC BLOCK FRONTEND BLOCK
FRONTEND_SCL FRONTEND_SDA EB_CLK403 FRONTEND_C1 FRONTEND_C2 PAL_DVB RF_A_MONO RF_CVBS CH3:4 BG_L-NORM TUNE_IN RESET_DMA LNB_IN(0:1) HSDI_SIG(0:8) HSDI_DATA(0:7) MDO_EC(0:10) EB_EXTINT(0:2) MDO_EC(0:10) PAL_A_V(0:2) HVSYNC(0:1)
1 2
HOST2 BLOCK
EB_CLK402 READ_STROBE CD1 CD2 MOD_RESET_A MDI_EC(0:10) IRQ-RDY1 IRQ-RDY2 +3.3V_SEP GND_SEP LNB_LARM DISEQ UARTDO(0:5) O_E INT_VER MDO_EC(0:10) MOD_RESET_B HSDI_SIG(0:8) HSDI_DATA(0:7) HSDI_STATUS(0:1) Sheet 10 (F) 3-5 16-31 0-1 4,6 1,2 GENERAL_IO(0:5) IIC(0:1) EXTDATA(0:31) EXTADDR(0:24) EB_OUT(0:2) CHIP_SELECT(0:6) JTAG_M_OUT(0:2) TDO RESET CLK_27 UARTDI(0:5) JTAG_M_TDO_M Sheet 5 (C) TDO SC_CONTROL(0:7) UARTDI(0:5) 0 JTAG_M_OUT(0:2) SC_CONTROL(0:7) 1 24-31 1,2 EB_EXTINT(0:2) 0 MDI_EC(0:10) EXTWAIT1
PAL_A_V(0:2) HVSYNC(0:1) PAL_DVB Sheet 11 (G)
VCO_CNT O_E INT_VER
AUDIO/VIDEO BLOCK
CH3:4 FRONTEND_C1 FRONTEND_C2 FRONTEND_SCL LATCH_CONTROL2 LATCH_CONTROL3 FRONTEND_SDA CA_5V_CTRL PAL_DVB RF_A_MONO RF_CVBS VREF_TRIM AUDIO_OUT(0:4) RGB_OUT(0:2) BG_L-NORM TUNE_IN RESET_DMA PAL_A_V(0:2)
DESCRAMBLER BLOCK
SMARTCARD_OUT(0:4) EB_CLK401 CA_5V_CTRL MDI_EC(0:10) EXTWAIT1 CHIP_SELECT(0:6) RESET EXTDATA(0:31) EXTADDR(0:24) EB_OUT(0:2) IIC_2(0:1) READ_STROBE CD1 CD2 MOD_RESET_A IRQ_RDY1 IRQ_RDY2 LATCH_CONTROL2 LATCH_CONTROL3 SAT_SW_WR RGB_OUT(0:2) MDO(0:10) EB_EXTINT(0:2) EB_IN(0:3) LATCH_CONTROL MDO(0:10) 2 0 AUDIO_OUT(0:4) STD_BY Sheet 6 (B)
SMARTCARD BLOCK
SMARTCARD_OUT(0:4) SC_CONTROL(0:7) SMARTCARD_SCDATAIO SMART_C_3.3_5V UARTDO(0:5) SMARTCARD_IN(0:2) UARTDI(0:5) 1,2
PCMCLK FBLK_IN REMOTECONTROL_SIRCSO
THIS DRAWING IS PROPERTY OF SCI DESIGN CENTER AND MUST NOT BE COPIED OR SHOWN OR GIVEN TO THIRD PERSON. VIOLATION OF THESE STIPULATIONS WILL BE SUBJECT TO LEGAL MEASURES ACCORDING TO EXISTING LAW.
HSDI_STATUS(0:1) 3 GENERAL_IO(0:5) IIC(0:1) MOD_RESET_B
COMPOUT_CVBS RESET 1,2,3 24-31 EXTADDR(0:24) EXTDATA(0:31) IIC(0:1) IIC_2(0:1) Sheet 7 (A)
PROCESSOR BLOCK
SMARTCARD_IN(0:2) SMARTCARD_SCDATAIO REMOTECONTROL_SIRCSO PCMCLK MDO(0:10) UARTDI(0:5) GENERAL_IO(0:5) IIC(0:1) RGB_OUT(0:2) IIC_2(0:1) RESET AUDIO_OUT(0:4) UARTDO(0:5) UART1_CK16 SMARTCARD_OUT(0:4)
GENERAL_IO(0:5) IIC(0:1)
Sheet 4 (D)
RESET
HSDI_DATA(0:7) HSDI_SIG(0:8)
HSDI_DATA(0:7) HSDI_SIG(0:8) HSDI_STATUS(0:1) FBLK_IN
HSDI_STATUS(0:1) EXTDATA(0:31) EXTADDR(0:24)
EXTADDR(0:24)
EB_EXTINT(0:2) EB_EXTINT(0:2) EB_IN(0:3) EB_IN(0:3)
COMPOUT_CVBS EB_OUT(0:2) CHIP_SELECT(0:6) EB_CLK401 EB_CLK402 EB_CLK403 JTAG_M_OUT(0:2) EB_DRAMOUT(0:4) JTAG_S_IN(0:3) JTAG_S_IN(0:3) SDATA(0:15) JTAG_S_TDO_S 24 SDRAM_CONTROL(0:8) SADDR(0:11) JTAG_S_IN(0:3) CLK_27 VREF_TRIM VCO_CNT SMART_C_3.3_5V MOD_RESET_B 1284_LEVEL HVSYNC(0:1) Sheet 2 (P) STDBY 1 0-2 EXTDATA(0:31) EXTADDR(0:24) RESET SAT_SW_WR STD_BY IIC_2(0:1)
EB_OUT(0:2) CHIP_SELECT(0:6)
HOST CONTROL BLOCK
LATCH_CONTROL JTAG_M_TDO_M
POWER BLOCK
+5V_OP +12V_OP +3,3V_OP +2,5V +3,3V +5V +6V +12V +33V +23V +3.3V_SEP GND_SEP LNB_LARM DISEQ LNB_IN(0:1) LIGHT_DISPLAY +5V_OP +12V_OP +3.3V_OP +2.5V +3.3V +5V +6V +12V +33V +23V +3.3V_SEP GND_SEP LNB_LARM DISEQ LNB_IN(0:1)
EB_OUT(0:2) EXTADDR(0:24) EXTDATA(0:31) RESET 1,3 CHIP_SELECT(0:6) EB_DRAMOUT(0:4) JTAG_S_TDO_S SDRAM_CONTROL(0:8) SADDR(0:11) SDATA(0:15) LIGHT_DISPLAY Sheet 3 (H) SDATA(0:15)
1284 BLOCK
HSDI_STATUS(0:1) HSDI_DATA(0:7) HSDI_SIG(0:8)
1284_LEVEL
Sheet 8 (E)
Sheet 9 (S) SADDR(0:11)
SDRAMCONTROL(0:8)
EB_DRAMOUT(0:4)
ENGINEER
DRAWN BY
SHEET
BLOCK ID
SIZE
SCI
Design Center Motala Sweden
Palm Nils Erik Block overview
Sven-Ake Larsson
1 of 11
DATE VARIANT
A3 MASTER
PCB
2001-03-07
TIME
MAIN BOARD
11:57:14
55 12212-01
+3.3V JP02 LP04 6u8 OPT CP65 22u CP34 22n CP35 100n CP33 100n JP03 LP03 6u8 OPT OPT CP64 22u
+3.3V JP04 LP02 6u8 OPT OPT CP63 22u
+3.3V
+3.3V
CP32 22n
CP31 100n
CP30 22n
CP67 100n
CP36 22n LP01 OPT 6u8 CP66 220u
OPT
OPT
OPT
SDRAM_CONTROL(0:8)
8 7 6 5 4 3 2 1 0 11 10 8 0 D20 D19 1 C20 2 C19 3 B20 4 B19 5 A20 6 A19 7 9 8 7 6 5 4 3 2 1
SADDR(0:11)
SDATA(0:15)
IP03-4 74AC04 9 8 1 +3V GND
IP03-5 74AC04 11 10 1 +3V GND
MDO(0:10)
0 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0 +3.3V
U11
C17
U19
V11
B17
V19
M2
M1
G3
G2
G1
D7
C3
D3
H3
R2
R1
N2
N1
H2
H1
D2
D1
C2
C1
D5
C7 AGND_RC
C9 AVCC_COMP
B5
E3
K3
P2
P1
K2
K1
E2
E1
B2
B1
B4
B7
AVCC_GY
AVCC_CPLL
AGND_CPLL
AVCC_APLL1
AGND_APLL1
AVCC_APLL2
AGND_APLL2
AGND_GY
DATAIN0
DATAIN1
DATAIN2
DATAIN3
DATAIN4
DATAIN5
DATAIN6
DATAIN7
SDATA15
SDATA14
SDATA13
SDATA12
SDATA11
SDATA10
AVCC_RC
AGND_COMP
SDOML
SCKE
SRAS
SCAS
AVCC_B
SADDR11
SADDR10
AGND_B
SCS2
SCS1
SADDR9
SADDR8
SADDR7
SADDR6
SADDR5
SADDR4
SADDR3
SADDR2
SADDR1
SADDR0
SDATA9
SDATA8
SDATA7
SDATA6
SDATA5
SDATA4
SDATA3
SDATA2
SDATA1
SDATA0
SCLK
SDOMU
SWE
A8
F3
F2
F1
L3
L2
L1
J3
J2
J1
IP04-1 TL082CD A2 C8 C5 A5 B3 A3 C6 A6 E4 G4 A7 C4 A4 B6 B8 D9 R18 R19 R20 T20 T19 4 3 2 CP73 CP70 CP71 100n CP69 100n 100n CP68 10u 0 100n CP72 100n RP72 1k82 RP73 1k00 RP80 6k8 RP76 470R RP77 470R RP74 432R RP75 470R 1 GND +23V
+
2 3
REMOTECONTROL_SIRCSO
10
N19 N20 P19 JP01 P20
DCLK PACCLK BYTE_START DERROR
OSD_ACTIVE BIAS_COMP BIAS_GY BIAS_RC BIAS_B B_OUT GY_OUT RC_OUT HSYNC VSYNC VREF COMP3 COMP2 COMP1 COMP0 COMP_OUT
SMARTCARD_IN(0:2) SMARTCARD_OUT(0:4)
1
9
V17 SCDET1 V18 SCDET2 RP33 33R U18 SCRESET V16 SCCLK T17 SCVPPEN U16 SCVCCEN T18 SCDATAIO V15 SCSEL
2 1 0 1 0 RP79 39k
FBLK_IN
SMARTCARD_SCDATAIO
+3.3V +3.3V RP01 VCC GND 220R +5V RP08 3k3 1 0 OUT IP05 TSOP1836SI3V RP09 3k3 RP52 33R RP51 33R OPT JP07 1k0 CP76 1n0 IP08 BSH111 +3.3V IP07 BSH111 RP82 5k6 IR CP01 22u RP89 4 0 3 1 RP88 12k 2
2
RGB_OUT(0:2) HVSYNC(0:1)
W19 RP81 5k6 B18 OPT JP06 A18 N18 P18
APLL_LOCK
VREF_TRIM
IIC(0:1)
IROUT IRIN IICS_SDA IICS_SCL UART_CK16 UART_RTS2 UART_RTS1 UART_DO3 UART_DO2 UART_DO1 UART_CTS2 UART_CTS1 UART_DI3 UART_DI2 UART_DI1 IO5 IO4 IO3 IO2 IO1 TRST TCK TMS TDI TDO CLK27 CLK_SEL IP01 SIMBA +2.5V +3.3V GND
SPDIF PCMDATA PCMCLK LRCLK ASCLK
COMPOUT_CVBS PCMCLK
THIS DRAWING IS PROPERTY OF SCI DESIGN CENTER AND MUST NOT BE COPIED OR SHOWN OR GIVEN TO THIRD PERSON. VIOLATION OF THESE STIPULATIONS WILL BE SUBJECT TO LEGAL MEASURES ACCORDING TO EXISTING LAW.
UART1_CK16 UARTDO(0:5)
3 XP01-1 OPT XP01-2 OPT 3 RP86 10k +3.3V 5 4 3 2 1
C15 C13 C11 D16 D14 D10 D12 5 4 3 2 1 5 4 C12 C16 C14 C10 P17 M17 K17 J17 G17 D18
AUDIO_OUT(0:4)
UARTDI(0:5) GENERAL_IO(0:5)
EXTDATA0 EXTDATA1 EXTDATA2 EXTDATA3 EXTDATA4 EXTDATA5 EXTDATA6 EXTDATA7 EXTDATA8 EXTDATA9 EXTDATA10 EXTDATA11 EXTDATA12 EXTDATA13 EXTDATA14 EXTDATA15 EXTDATA16 EXTDATA17 EXTDATA18 EXTDATA19 EXTDATA20 EXTDATA21 EXTDATA22 EXTDATA23 EXTDATA24 EXTDATA25 EXTDATA26 EXTDATA27 EXTDATA28 EXTDATA29 EXTDATA30 HSDIF_STATUS0 HSDI_STATUS1 EXTDATA31 HSDIF_DATA1 HSDIF_DATA2 HSDIF_DATA3 HSDIF_DATA4 HSDIF_DATA5 HSDIF_DATA6 HSDIF_DATA0 HSDIF_DATA7 HSDI_SIG2 HSDI_SIG3 HSDI_SIG4 HSDI_SIG5 HSDI_SIG6 HSDI_SIG7 HSDI_SIG8 HSDI_SIG9
A9 B9 A10 B10 A11 B11 A12 B12 A13 B13 A14 B14 A15 B15 A16 B16 T1 T2 U1 U2 V1 V2 W1 W2 Y1 Y2 Y3 W3 Y4 W4 Y5 W5 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+3.3V +5V IP10 BSH111 RP68 RP69 2k2 33R RP70 33R RP85 RP78 47k 12k 3 2 1 RP03 47R OPT OPTCP02 68p IP03-3 74AC04 5 6 1 +3V GND 0 RP84 5k6 JP09 IP09 BSH111 OPT JP08 RP83 5k6 RP87 5k6
IIC_2(0:1)
RP67 2k2 0
3
JTAG_S_IN(0:3) JTAG_S_TDO_S VCO_CNT
RP02 33R OPT RP10 1M0 IP03-1 74AC04 1 2 1
+3V GND
1
E18 F18 H18 G18 U12 V10
CLK_27
IP03-6 74AC04 RP35 13 12 22R 1
+3V GND
RP36 33R CP39 47p
CP03 RP13 220R +23V 220n RP15 180k CP38 100n RP16 47k +
GND +23V
VCXO_CTRL C18 RESET U20 TEST0 V20 TEST1 W20 TEST2 Y20 TEST3 T4 CLK40 P3 RAS3 N3 RAS2 M3 RAS1 L4 UCAS M4 LCAS V9 CS6 V8 CS5 V7 CS4 EXTADDR24 EXTADDR23 EXTADDR22 EXTADDR21 EXTADDR20 EXTADDR19 EXTADDR18 EXTADDR17 EXTADDR16 EXTADDR15 EXTADDR14 EXTADDR13 EXTADDR12 EXTADDR11 EXTADDR10 V6 CS3 V5 CS2 EXTACK0 EXTACK1 EXTACK2 EXTINT2 EXTINT1 EXTINT0 EXTRW EXTOE V4 CS1 EXTWAIT
V12
ZP01 27MHz CP04 68p RP14 100k DP01 BB640
CP05 22p
IP04-2 TL082CD 7
6 5
+3V CP58 22n
+3V CP75 100n
RP17 +3.3V 10k +3.3V CP06 220n RP20 470R 2 1 CP08 220n CP09 4n7 RP21 2k7
RP18 100k IP06 MC34164P-3 IN 3 GND RES
EXTADDR1
EXTADDR9
EXTADDR8
EXTADDR7
EXTADDR6
EXTADDR5
EXTADDR4
EXTADDR3
EXTADDR2
EXTADDR0
HSDIF_1
EXTDATA(0:31)
K18
U5
U7
U9
W6
Y6
L18
M19
L20
L19
K20
K19
J20
J19
J18
H19
G20
G19
F20
F19 5
E20 6
M20
W10
W17
W16
W15
W14
W13
W12
W11
+3.3V RP71 +5V RP19 100R OPT 0R0
RESET
+3V JP05 OPT CP07 100n FP01 R12C222 RP62 22R 1 2 3 1 2 3 3 EB_DRAMOUT(0:4) 2 1 4 0 6 5 4 3 2 1 RP22 47R 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RP60 CP74 22R 18p 0 2 3 4 5 1 6 7 8
U14
0
H20
Y10
Y18
Y17
Y16
Y15
Y14
Y13
Y12
Y11
V13
V14
1
2
3
4
7
E19
Y9
Y8
W9
W8
W7
U3
R3
Y7
T3
HSDI_DATA(0:7) HSDI_SIG(0:8) HSDI_STATUS(0:1) EXTADDR(0:24)
9
8
7
6
5
4
3
2
1
0
0
DP02 OPT BZT55C3V0
1
+2.5V
+3.3V CP11 CP12 CP14 CP15 CP19 CP21 CP22 CP62 CP37 CP60 22n 22n 22n 22n 22n 22n 22n 22n 22n 22n CP13CP16CP17CP18CP20 CP61 22n 22n 22n 22n 22n 22n
EB_CLK401 EB_CLK402 EB_CLK403
TEMP(0:3)
EB_DRAMOUT(0:4) CHIP_SELECT(0:6) EB_EXTINT(0:2)
0 2 1 0 1 2 3
ENGINEER
DRAWN BY
SHEET
BLOCK ID
SIZE
EB_IN(0:3)
1 0
SCI
Design Center Motala Sweden
Palm Nils Erik Processor block
Sven-Ake Larsson
2 of 11
DATE
P
VARIANT
A3
2001-03-07
TIME PCB
MASTER 55 12212-01
EB_OUT(0:2)
MAIN BOARD
11:57:14
+12V TH06 BC847B OPT RH86 390R RH90 220R OPT RH84 470R OPT JH08 TH07 BC817-25 RH94 6R8 RH92 6R8 TH09 BC327-25 RH91 6R8
+5V RH06 10k RH08 RH09 RH10 RH11 56k 56k 56k 56k RH46 0R0 3 T08 0 T09 RH07 0R0
T23 JH01
+3.3V
+5V
LIGHT_DISPLAY
RH83 OPT 4k7
OPT
0 +12V_OP TH08 BC857B RH88 1k8 RH89 1k0 JH02 OPT
ARM/JTAG
SPU TRST_S TDI_S TMS_S TCK_S JTAG_S_TDO_S T13 SECTOR_WP ICE_RST TDI_M XH05-1 XH05-3 XH05-5 XH05-7 XH05-9 XH05-11 XH05-13 XH05-15 XH05-2 XH05-4 XH05-6 XH05-8 XH05-10 XH05-12 XH05-14 XH05-16
+5V +5V CH28 100n 20 10 VCC GND 1 EN 11 CLK 31 30 29 28 27 26 25 24 2 3 4 5 6 7 8 9 IH11 74HCT574 D 19 18 17 16 15 14 13 12
RH85 OPT 470R
XH02-1 XH02-3 XH02-5 XH02-7 XH02-9 XH02-11 XH02-13
XH02-2 XH02-4 XH02-6 XH02-8 XH02-10 XH02-12 XH02-14 IH12 LTC45454G 11 RH93 6R8
JH12 TMS_M 1 JH13 OPT TCK_M T16 +12V T14 T15 T17
DH02 LS4148
JTAG_TDO
1 T10 2 T11
JTAG_M_TDO_M
2
CH16 100n RH51 8 16 VCC GND D MR LE A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 IH01 74HCT259 +5V IH20-1 74F32 1 6 2 1 +5V GND IH20-3 74F32 11 9 10 1 +5V GND DH01 LS4148 24 RH04 47k 8 3 RH01 1R5 OPT CH17 OPT 100u LOAD1 4 5 6 7 9 10 11 12 JH17 JH16 100R
JTAG_M_OUT(0:2)
RH52
13 15 14 2 1 3 2 4 3
RH16 100R RH17 RH18 100R RH20 100R RH22 100R 100R RH19 100R RH21 100R RH27 100R
JTAG_S_TDO_S JTAG_S_IN(0:3)
RH12 47k T12
a b c d e f g dp DIG1 DIG2 COLON DIG3 DIG4 2 11 6 7 3 10 5 8 14 16
RESET LATCH_CONTROL
100R
7 4 2 1 10 5 3 12 9 13 8 6
1284_LEVEL
RH32 OPT 68R LH01 1u0 19 OPT CH43 100p
IH25 MAX7219 DIG0 DIG1 DIG2 DIG3 DIG4 DIG5 DIG6 DIG7 A B C D E F G DP GND 4 9 DOUT GND DIN LOAD CLK ISET V+
SMART_C_3.3_5V MOD_RESET_B
+3.3V CH77 18 22n RH87 CH76 47k 47u 1 12 13 +3.3V IH18 TMS626162 0 1 2 3 4 5 6 7 8 9 21 22 23 24 27 28 29 30 31 32 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 CKE CLK DQML DQMU CS WE RAS CAS VCC VCC VSS VSS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 1 25 26 50 2 3 5 6 8 9 11 12 39 40 42 43 45 46 48 49 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SADDR(0:11) SDATA(0:15) CH44 22n 0 1 2 3 4 5 6 7 8 9 21 22 23 24 27 28 29 30 31 32 +3.3V IH19 TMS626162 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 CKE CLK DQML DQMU CS WE RAS CAS VCC VCC VSS VSS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 1 25 26 50 2 3 5 6 8 9 11 12 39 40 42 43 45 46 48 49 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CH45 22n +3.3V CH46CH67 CH47CH68 CH50CH69 CH51CH70 22n 100n 100n 22n 22n 100n 22n 100n CH48CH72 CH49 CH52 CH53 22n 22n 100n 22n 22n
RH28 1k2
TH01 BC807-25
DISPLAY CONN ALT
OPT OPT OPT OPT OPT OPT
RH29 1k2 RH30 1k2 TH02 BC807-25 RH55 1k2 RH56 1k2 TH03 BC807-25 TH04 BC807-25 TH05 BC807-25
IH20-2 74F32 4 5 1 +5V GND IH20-4 74F32 12 13 1 +5V GND
20 23 21 15 17 22 24
SDATA(0:15)
XH01-1 XH01-2 XH01-3 XH01-4 XH01-5 XH01-6
THIS DRAWING IS PROPERTY OF SCI DESIGN CENTER AND MUST NOT BE COPIED OR SHOWN OR GIVEN TO THIRD PERSON. VIOLATION OF THESE STIPULATIONS WILL BE SUBJECT TO LEGAL MEASURES ACCORDING TO EXISTING LAW.
EXTDATA(0:31) EXTADDR(0:24)
+3.3V OPT CH75 22n CH18 22n 37 VCC 25 A0 24 A1 23 A2 22 A3 21 A4 20 A5 19 A6 18 A7 8 A8 7 A9 6 A10 5 A11 4 A12 3 A13 2 A14 1 A15 48 A16 17 A17 16 A18 9 A19 10 A20 26 28 47 11 CE OE BYTE WE 27 VSS WP ACC RESET BY RY 12 15 RH02 10k 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RH57 100R 14 46 RH80 4k7 OPT RH03 220R +3.3V +3.3V 1 2 3 4 5 6 7 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 8 9 10 OPT 11 12 13 14 15 16 17 18 19 20 21 JH04 OPT 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9 10 26 28 47 11 37 VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 CE OE BYTE WE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RH61 100R RH58 100R RH50 IH14 AM29LV160 100R RH79 100R +3.3V RH42 100R 27 VSS WP ACC RESET BY RY 12 15 14 46 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 JH05 OPT 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9 10 26 28 47 11 37 VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 CE OE BYTE WE IH09 AM29LV160 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 27 VSS WP ACC RESET BY RY +3.3V CH71 22n CH27 22n 46 RH81 4k7 14 OPT RH26 T21 220R 12 15 T20 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 RH25 10k 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RH72 100R +3.3V RH68 100R +3.3V 2 3 +3.3V 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 JH19 OPT 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9 10 26 RH76 100R RH78 100R 28 47 11 37 VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 CE OE BYTE WE IH22 AM29LV160 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 0 1 2 3 4 5 6 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 0 1 IH10 SOCKEL 0 1 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 3 4 0 1 0 14 30 31 13 29 RAS UCAS LCAS WE OE +3.3V GND D12 D13 D14 D15 D16 2 3 4 5 7 8 9 16 17 18 19 20 21 22 2 3 4 5 6 7 8 9 10 11 2 4 0 1 0 17 18 19 20 23 24 25 26 27 28 16 15 14 30 31 13 29 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 RAS UCAS LCAS WE OE +3.3V GND D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 2 3 4 5 7 8 9 10 33 34 35 36 38 39 40 41 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 4 0 1 0 14 30 31 13 29 RAS UCAS LCAS WE OE +3.3V GND 0 1 2 3 4 5 6 7 8 9 10 11 17 18 19 20 23 24 25 26 27 28 16 15 IH24 uPD4218165 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 2 3 4 5 7 8 9 10 33 34 35 36 38 39 40 41 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 CH56CH60 CH57CH64 CH58CH65 22n 22n 22n 22n 22n 22n OPT OPT OPT +3.3V 0 1 8 9 10 11 IH13 SOCKEL 17 18 19 20 23 24 25 26 27 28 16 15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 12 1 4 0 1 0 7 +3.3V 1 6 12 25 19 20 21 22 23 24 27 28 29 30 31 32 33 14 37 38 13 36 OPT +3.3V CH66 22n CH54 22n 46 RH82 4k7 OPT RH65 220R +3.3V
10 20 11 19 7 34 8 35 0 14 1 36 2 18 4 15 6 17 5 16 +3.3V +3.3V OPT T18 T19
10 20 11 19 7 34 8 35 0 14 1 36 3 18 4 15 6 17 5 16
27 VSS
2 3 4 5 6 7 8 9 10 RH41 100R 3 4 1 11 12 13 14 15 16 +3.3V 17 18 19 20 21 22 JH03 OPT RH39 100R RH60 100R RH49 100R
WP ACC RESET BY RY
14 12 15
Driver power: +3.3V Driver ground: GND
RH63 10k
SADDR(0:11) SDRAM_CONTROL(0:8) EXTDATA(0:31) EXTADDR(0:24)
Driver power: +3.3V Driver ground: GND +3.3V CH55 22n +3.3V +3.3V
CH41 CH74 CH42 22n 22n 22n OPT OPT
CHIP_SELECT(0:6)
+3.3V IH23 uPD4265165 VCC VCC VCC VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 /NC RAS UCAS LCAS WE OE D1 D2 D3 D4 D5 D6 D7 D8 D9 2 3 4 5 7 8 9 16 17 18 19 20 21 22 GND GND GND GND 50 45 39 26 0 1 2 3 4 5 6 7 8 9 10 11 12 3 4 0 1 0 EXTADDR(0:24)
+3.3V
IH17 uPD4265165 1 6 12 25 19 20 21 22 23 24 27 28 29 30 31 32 33 14 37 38 13 36 VCC VCC VCC VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 /NC RAS UCAS LCAS WE OE D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 2 3 4 5 7 8 9 16 17 18 19 20 21 22 GND GND GND GND 50 45 39 26 0 1 2 3 4 5 6 7 8 9 10 11 12 2 4 0 1 0 1 6 12 25 19 20 21 22 23 24 27 28 29 30 31 32 33 14 37 38 13 36
IH16 uPD4265165 VCC VCC VCC VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12/NC RAS UCAS LCAS WE OE D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 2 3 4 5 7 8 9 10 41 42 43 44 46 47 48 49 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GND GND GND GND 50 45 39 26
RH53 100R
IH03 AM29LV160
10 23 41 24
10 23 41 24 42 25 43 26 44 27 46 28 47 29 48 30 49 31
EB_OUT(0:2)
EB_OUT(0:2)
+3.3V +3.3V
42 25 D10 43 26 D11 D12 D13 44 27 46 28
0 1 2 3 4 5 6 7 8 9 10 11
CH36CH61 CH37CH62 CH38CH63 CH32CH59 CH33CH73 CH34 22n 22n 22n 22n 22n 22n 22n 22n 22n 22n 22n OPT OPT OPT OPT OPT
47 29 D14 48 30 D15 D16 49 31
EB_OUT(0:2) EB_DRAMOUT(0:4)
10 23 33 24 34 25 35 26 36 27 38 28 39 29 40 30 41 31
EB_DRAMOUT(0:4)
ENGINEER
DRAWN BY
SHEET
BLOCK ID
SIZE
EB_OUT(0:2)
SCI
Design Center Motala Sweden
Palm Nils Erik Host control block
Sven-Ake Larsson
3 of 11
DATE
H
VARIANT
A3
2001-03-07
TIME PCB
MASTER 55 12212-01
MAIN BOARD
11:57:14
RD45-2
OPTION
EXTADDR(0:24)
20 RD45-3 0R OPTION RD47 21 0R
+5V CD15 100n CD19 100n 16 15 VCC GND 2 6 V+ V1 4 C1+ C2+ 3 5 C1C211 14 10 13 ID08-1 74LVT125 8 1 2 +3.3V GND ID08-2 74LVT125 EN 6 +3.3V GND ID06 MAX202 7 12 CTS_DTE 9 RXD_DTE CD16 100n CD17 100n +12V
CD12 22n
+3.3V
HSDI_STATUS(0:1)
0
RD45-1 XD15-1 XD15-3 XD15-5 XD15-7 6 XD15-9 4 XD15-11 2 +5V 0 5
OPTION
OPTION
XD15-2 1 XD15-4 XD15-6 XD15-8 XD15-10 5 XD15-12 3 XD15-14 1 XD15-16 0 XD15-18 XD15-20 XD15-22 XD15-24 XD15-26 XD15-28 16 XD15-30 17 RD22 0R0 0 RD20 OPTION 0R0 RD19 OPTION 0R0 RD46-1
OPTION
OPTION
0R0
24 19
0R
ID04 74LVC541A RD30 3k3
RESET
1 19 2 3 4 5 6 7 8 9
RD62 1k0 CD26 1n0
HSDI_SIG(0:8)
4 2
RD46-2
OPTION
HSDI_SIG(0:8)
CD18 100n 1 22 4 TXD_DTE RTS_DTE
DTE CONN
XD9-6 XD9-2 0R RD70-3 0R RD70-2 0R RD70-1 0R XD9-10 XD9-7 XD9-3 XD9-8 XD9-4 XD9-9 XD9-5
DCE CONN
RD71-4 XD16-5 0R XD16-9 XD16-4 RD71-1 0R RD71-2 0R RD71-3 0R XD16-10 XD16-11 XD16-8 XD16-3 XD16-7 XD16-2 XD16-6 XD16-1 23 22 21 20 19 18 17 16 18 17 16 15 14 13 12 11 +3.3V GND EN
G1 G2
0R
3 0R RD46-4
OPTION
HSDI_DATA(0:7)
0R
6
RD45-4
OPTION
RD70-4
HSDI_DATA(0:7)
7 5
0R
GENERAL_IO(0:5)
RD66 68R EN 3
O_E INT_VER CD1 IRQ-RDY1
1
JD12
XD15-13 RD46-3 0R
OPTION
XD15-15 XD15-17 XD15-19 XD15-21 XD15-23
4 RD48 0R0
RD65 68R
4 5 MD01
XD9-11
RD24 10k
+3.3V RD25 10k
XD08-1 XD08-3 XD08-5 XD08-7
XD08-2 XD08-4 XD08-6 XD08-8 XD08-10
+3.3V
RD17 0R0
RD18 0R0
OPTION
RD50 0R0
RD49 0R0
OPTION
8
7 1 +3.3V
OPTION
GENERAL_IO(0:5)
+5V +12V IA07-3 74LVT125 10 9 DTR +3.3V GND DCD IP03-2 74AC04 +3V GND JD15 OPT 4 4 +3.3V_OP RD31 220R RD28 10k DD01 S186P TD01 BC847B RD29 22k CD14 22u 1 EN 8 RD67 68R 3 CD11 22n ID03 74LVC541A EN 31 30 29 28 27 26 25 24 18 17 16 15 14 13 12 11 +3.3V GND G1 G2 1 19 2 3 4 5 6 7 8 9 X3 X2 X1 RD26 10k +3.3V RD27 10k
23
GND_SEP
OPTION
TELCO CONN
XD10-1 2 DO2 ID08-4 74LVT125 XD10-3 XD10-5 EN 11 +3.3V GND 13 12 XD10-7 XD10-9 XD10-2 XD10-4 XD10-6 XD10-8 XD10-10
XD08-9
+3.3V
+3.3V_SEP
4 5
ID09-2 74LVT125 EN OPTION +3.3V GND RD56 0R0 RD57 6 RD75 0R0
RD16 4k7
XD15-25 XD15-27 XD15-29 XD15-31 XD15-33 XD15-35 8 XD15-37 9
EB_EXTINT(0:2) EXTDATA(0:31)
5 RTS2
5
CTS2
RD64 68R
READ_STROBE LNB_LARM DISEQ CD2 IRQ-RDY2
EB_CLK402
+3.3V +3.3V_OP
ID08-3 74LVT125
OPTION
XD15-32 18 XD15-34 19 XD15-36 20 XD15-38 21 XD15-40 22 XD15-42 23 XD15-44 3 XD15-46 XD15-48 +3.3V XD15-50 24 XD15-52 25 XD15-54 26 CD31 22n
2
DI2
8 +3.3V +3.3V GND
9
0R0
68R
MOD_RESET_B MOD_RESET_A EXTADDR(0:24)
UARTDI(0:5)
CD25 100n
MOD_RESET_A GENERAL_IO(0:5)
5
JD13 OPT
3
UARTDO(0:5)
RD63
EN
10
EXTDATA(0:31)
JD14
THIS DRAWING IS PROPERTY OF SCI DESIGN CENTER AND MUST NOT BE COPIED OR SHOWN OR GIVEN TO THIRD PERSON. VIOLATION OF THESE STIPULATIONS WILL BE SUBJECT TO LEGAL MEASURES ACCORDING TO EXISTING LAW.
XD15-39 10 XD15-41 RD58 +5V +5V_OP 0R0 RD59 0R0 RD68 0 0R0 13 XD15-51 8 14 XD15-53 7 XD15-55 6 XD15-57 5 XD15-59 4 XD15-61 ID09-4 74LVT125 13 12 EN
OPTION
11 XD15-43 12 XD15-45 XD15-47 XD15-49
ID09-1 74LVT125
OPTION
9 1 2 6 7 6 5 4 3 2 1 0 10 8
RD54-4 RD53-1 RD53-3 RD53-4 RD53-2 RD55-2 RD55-1 RD54-1 RD55-3 RD54-3 RD54-2 RD55-4
0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R
9 7 6 5 4 3 2 1 0 10
9 7 6 5 4 3 2 1 0 10
+3.3V RD13 10k RD14 10k
RD15 10k
RD23 10k
OPTION
EN
CHIP_SELECT(0:6)
OPTION
+3.3V GND
EB_OUT(0:2)
ID09-3 74LVT125 10 9 EN
OPTION
+3.3V GND
XD15-56 27 XD15-58 28 XD15-60 29 XD15-62
+3.3V
+5V JD17 8 JD18 OPT CD32 100n
MDI_EC(0:10)
3 XD15-63 2 11 1 XD15-67 0 XD15-69 0 XD15-71 1 XD15-72 XD15-68 XD15-65 XD15-66 XD15-64
30 31
CD21 100n
9 10
EXTADDR(0:24)
15 16 +3.3V TS(0:10) 41 40 39 44 43 37 36 IO30 42 IO1 IO4 IO3 IO0 38 IO31 IO29 35 GND IO28 VCC IO2 34
+3.3V GND
IIC(0:1)
XD15-70 17 18 RD01 4k7
EB_OUT(0:2)
RD60 +3.3V +3.3V_OP
OPTION
RD69 1 0R0
XD15-73 XD15-75 XD15-77 XD15-79
XD15-74 XD15-76 XD15-78 XD15-80 MD_EC(0:10) RD05
OPTION
EXTWAIT1
CD10 47p
1 2 3 4 5 6 2 7 8 9 10 11
IO5 IO6 IO7 TDI CLK0 GND TCK IO8 IO9 IO10 IO11 GND IO13 IO14 IO15 IO16 IO17 IO18 IO12 IO19 IO20 VCC MACH4-64/32 ID07
IO27 IO26 IO25 IO24 TDO GND CLK1 TMS IO23 IO22 IO21
33 32 31 30 29 28 27 26 25 24 23
7 6 5 4
0R0 RD61 0R0
CLK_27
OPTION
TDO JTAG_M_OUT(0:2)
100R
JTAG_M_TDO_M JTAG_M_OUT(0:2)
1 3 2 1 +3.3V +5V
MDO_EC(0:10)
RD76 1k0 ID10 L4941BDT 1 3 IN OUT 2 REF
ID02-5 74LV04 11 10 1 +V_D2 GND ID02-3 74LV04 5 6 1 +V_D2 GND
ID02-6 74LV04 13 12 1 +V_D2 GND ID02-4 74LV04 9 8 1 +V_D2 GND
14
15
16
17
18
19
20
12
13
21
22
OPT JD03 0 CD13 22n ID05 24LC64 8 4 VCC VSS E0 E1 E2 MODE 1 2 3 7
JD04
T22 JD05 DV inverted OPT DV normal JD06 CD20 100n 0 1
XD17 PIN 1 JD19 2 3 4
6 5
JD02 OPT JD01
ID02-1 74LV04 1 2 1 +V_D2 GND RD51 1M0
ID02-2 74LV04 3 4 1 +V_D2 GND
IIC(0:1)
ZD01 17.734475MHz 10 9 7 5 8 6 4 3 2 1 0
RD52 100R JD10 OPT
+5V +3.3V
JD16 OPT +V_D2
OPT JD09
JD08
0R
FD01 R12C222 CD22 330p CD27 100n
ENGINEER
DRAWN BY
SHEET
BLOCK ID
SIZE
RD04-4 0R
RD04-3 0R
RD03-2 0R
RD03-4 0R
RD02-1 0R
RD03-3 0R
RD04-1 0R
RD04-2 0R
RD02-2 0R
RD02-3 0R
RD02-4 0R
RD03-1
CD24 33p
CD23 33p JD11 OPT
SCI
Design Center Motala Sweden
Palm Nils Erik Host2 block
Sven-Ake Larsson
4 of 11
DATE
D
VARIANT
A3
10
9
8
7
6
5
4
3
2
1
0
2001-03-07
TIME PCB
MASTER 55 12212-01
MDO_EC(0:10)
MAIN BOARD
11:57:14
RC146-1 0R 0 1 2
RC146-4 0R 3 4
RC145-3 0R 5 6
RC145-1 0R 7
RC144 0R0
MDO(0:10)
10 RC145-4 0R
8
9
10
1
2
3
4
5
6
7
0
8
9
+3.3V_CA +3.3V_CA CC04 22n +3.3V_CA OPT CC06 22n
100R RC61 +3.3V_CA CC19 22n +3.3V_CA CC20 22n
RC146-2 RC146-3 0R 0R
RC138 0R0
RC145-2 0R
RC149 0R0
OPT
OPT
CC05 22n
+3.3V_CA CC18 22n 16 8 VCC GND EN G1 1 1 7 9 YB 1 5 YC 2 6 YA 0 4 4 5 6 7 7
15 1 2 0 0 1 2 3 3 5 6 1 2 3 11 10 14 13
16 8 VCC GND EN G1 1 1 OPT 7 1 YB 5 9 2 YC 6 123 YD 7 IC01 74LVC257 7 6 5
15 1 2 4 4 3 5 6 11 10 14 13
16 8 VCC GND EN G1 1 1 OPT 7 YB 9 YC 12 YD 5 8 10 6 10 9 7 9 RC20 100R OPT 4 YA 4 2 3 5 6 11 10 14 13 15 1
8 16 VCC GND EN G1 1 1 OPT 7 YB
RC167 68R RC121 68R RC175 68R OPT
15 11 1 2 0 3 0 10 1 1 2 9 2 5 6 11 10 14 13 3
15 1 4 2 3 5 6 11 10 14 13
16 8 VCC GND EN G1 1 1 YA 4 YB 5 YC 6
15 OPT RC173 47R 1 2 8 3 8 10 7 9 10 9 12 YD 7 5 6 11 10 14 13
8 16 VCC GND EN G1 1 1 7 9 YA RC108 68R 8
4 0 YA
4 YA
8
4
OPT CC34 18p
8
4
RC178 YB68R 10 RC177 YC68R 9
IC02 74LVC257 MDO1(0:10)
12 YD IC03 74LVC257 3
12 YD 3 IC11 74LVC257
9
RC176 68R 9 YC OPT
12 YD IC12 74LVC257
+12V
IC13 74LVC257
RC180 10k 4 RC181 1k0 TC1 BC847B JC31 +5V_OP +5V_CI JC32 +5V 2 3
TC2 MMSF5N02HD GATE DRAIN 5 6 7 8
+5V
CA_5V_CTRL
SOURCE DRAIN SOURCE DRAIN DRAIN
0 RC87-2 0R 21 1 RC87-3 0R 22 2 RC87-4 0R 23 9 RC87-1 0R 20 +3.3V 10 RC156 0R0 28 11 RC157 0R0 29 CC25 22n MDI2(0:11) RC166 0R0 30 3 4 RC151-1 0R 31 0R 32 0R 33 0R 34 11
MDI_EC(0:10) JTAG_M_OUT(0:2)
1 TMS_M TDI_M TCK_M JC30
THIS DRAWING IS PROPERTY OF SCI DESIGN CENTER AND MUST NOT BE COPIED OR SHOWN OR GIVEN TO THIRD PERSON. VIOLATION OF THESE STIPULATIONS WILL BE SUBJECT TO LEGAL MEASURES ACCORDING TO EXISTING LAW.
0 2
17 16 15
TDO CD1 CD2 CHIP_SELECT(0:6)
2 5
IC17 74LVC138 +5V 1 2 3 A0 A1 A2 D0 D1 D2 D3 D4 4 5 6 E1 E2 D5 D6 15 14 RC171 13 RC119 12RC125 11RC164 10RC127 9 RC128 7 RC129 47R 47R 47R 47R 47R 47R 47R
5 RC151-2 6 RC151-3 7 RC151-4
RC133 10k
RC132 10k
RC112 100R +5V_CI +5V VCC_MAC CC23 100n +3.3V RC113 100R
LATCH_CONTROL3 LATCH_CONTROL SAT_SW_WR LATCH_CONTROL2 READ_STROBE
RC91-1 0R 0 1 RC91-2 0R 1 14 RC91-3 0R 2 2 RC91-4 0R 3 15 RC95-3 0R 4 3 RC95-4 0R 5 16 RC95-1 0R 6 4 RC95-2 0R 7 17 RC99 0R011 12 RC100 0R0 9 OPT 0 RC101 0R010 OPT 13
2 RC80 0R0 25 3 RC81-1 0R 13 4 RC81-2 0R 14 5 RC81-3 0R 15 6 RC81-4 0R 16 7 RC85 0R0 17 10 RC82-1 0R 35 MDO2(0:10) 9 RC82-2 0R 36 0 RC82-3 0R 37 1 RC82-4 0R 38
RC71-4 0R 0 6 RC70-4 0R 1 20 RC71-3 0R 2 7 RC70-3 0R 3 21 RC71-2 0R 4 8 RC70-2 0R 5 22 RC71-1 0R 6 9 RC70-1 0R 7 23 RC77 0R08 18 RC780R0 9 5 RC79 0R010 19 RC86 25 0R0 26
JC07 +3.3V_OP +3.3V +3.3V_CA
OPTION
JC10
JC15 +5V +3.3V VCC_MAC OPT JC14 RESET_CA2
CI
CI
IRDETO
IRDETO
E3 D7 +3.3V GND
CC17OPT 22n
UPPER CC16 22n CI CAM CONN
XC02-T35 XC02-T36 XC02-T37 XC02-T38 XC02-T39 XC02-T40 XC02-T41 XC02-T42 XC02-T43 XC02-T44 XC02-T45 XC02-T46 XC02-T47 XC02-T48 XC02-T49 XC02-T50 XC02-T52
44
43
41
40
39
37
36
35
42
38
34
RC42 10k OPT OPT RC40 10k
+3.3V 19 RC172 CC33 OPT OPT 100R 12p 1 2 IO5 IO6 IO7 TDI CLK0 GND TCK IO8 IO9 IO10 IO11 GND IO14 IO15 IO16 IO17 IO18 IO12 IO13 IO19 IO20 VCC IC20 MACH4-32/32-15VC 27 4 SDA2_OE IO27 IO26 IO25 IO24 TDO GND CLK1 TMS IO23 IO22 IO21 33 32 31 30 29 28 27 26 25 24 23 JC23 JC22 SDA2_RJC21 JC20 CC32 100n VCC_MAC RC174 390R CC35 10n 17 16 15 7 18 6 17 5 16 4 15 3 14 2 13 1 12 CC15 100n +3.3V 0 11 +3.3V GND 2 IC14 74LVC245A OE 3EN1 3EN2 1 2 3 4 5 6 7 8 9 1 19 11 9 8 13 14 31 30 29 28 27 26 25 24 12 7 6 5 4 3 2 1 0 RC169 0R0 0 1 +3.3V CC14 100n RC66 0R0 0 2 4 6 0 2 4 6 +5V_CI 28 29 JC27 2 11 5 6 7 8 5 6 7 8 9 10 11 JC13 JC19 T04 JC24 10 SDA2 T03 SCL2 JC26 JC25 +3.3V CC27 22n RC64 0R0 JC28 4 0 3 5 RC56 RC06 OPT OPT 10k 10k 9 +5V CA(0:38)
XC02-T1 3 4 5 6 7 10 11 9 8 13 14 XC02-T2 XC02-T3 XC02-T4 XC02-T5 XC02-T6 XC02-T7 XC02-T8 XC02-T9 XC02-T10 XC02-T11 XC02-T12 XC02-T13 XC02-T14 XC02-T15 XC02-T16 XC02-T18 10 8 12 7 6 5 4 3 2 1 0 0 1 2 XC02-T19 XC02-T20 XC02-T21 XC02-T22 XC02-T23 XC02-T24 XC02-T25 XC02-T26 XC02-T28 XC02-T29 XC02-T30 XC02-T31 XC02-T32 XC02-T33 XC02-T34
LOWER IRDETO/CI CAM CONN
XC02-B1 XC02-B35 XC02-B2 XC02-B36
IO4
IO3
IO1
IO0
IO31
IO30
IO29
GND
IO28
VCC
IO2
+5V RC58 10k
10k RC60 RC57 10k 12 13 14 15 16 10 RC62 100R +3.3V +5V JC08 OPT JC09 RC65 0R0 2 3 4 13 15 14 1 2 3 CC24 22n 16 8 VCC GND D MR LE A0 A1 A2 Q0 Q1 Q2 Q3 Q4 CC08 47n +5V_CI Q5 Q6 Q7 IC19 74LV259 8 4 5 6 7 9 10 11 12
3
3 T01 4 5 6 T02 1 0 9 0 7 8 9 10 11
5
4
6
1 2 3
0 1 2 3 4
6
XC02-B3 XC02-B37 XC02-B4 XC02-B38 XC02-B5 XC02-B39 XC02-B6 XC02-B40 XC02-B7 XC02-B41 XC02-B8 XC02-B42 XC02-B9 XC02-B43 XC02-B10 XC02-B44 XC02-B11 XC02-B45 XC02-B12 XC02-B46 XC02-B13 XC02-B47 XC02-B14 XC02-B48 XC02-B15 XC02-B49 XC02-B16 XC02-B50 XC02-B17XC02-B51 XC02-B18 XC02-B52 XC02-B19 XC02-B53 XC02-B20 XC02-B54 XC02-B21 XC02-B55 XC02-B22 XC02-B56 XC02-B23 XC02-B57 XC02-B24 XC02-B58 XC02-B25 XC02-B59 XC02-B26 XC02-B60 XC02-B27XC02-B61 XC02-B28 XC02-B62 XC02-B29 XC02-B63 XC02-B30 XC02-B64 XC02-B31 XC02-B65 XC02-B32 XC02-B66 XC02-B33 XC02-B67 1 3 5 7 JC11 RC123 RC155 33R 0R0
IRQ_RDY2 RESET
7
7
33R 19 20 21 22 23 30 JC12 31 32 33 34 26 24 4 35 36 37 38 25 RC59 10k +5V 24 RC67 0R0
+5V_CI
XC02-T17 XC02-T51 +5V 4 XC02-T53 XC02-T54 XC02-T55 XC02-T56 XC02-T57 XC02-T58 XC02-T59 XC02-T60 XC02-T62 XC02-T63 XC02-T64 XC02-T65 XC02-T66 XC02-T67 XC02-T68 RC114 OPT 33R
5
3
2
7
6
RC41 OPT 10k
CA_BYPASS2
0R0 RC122 18
14
15
16
18
19
20
12
13
17
21
22
CA_BYPASS1
17 RC159 27
1
MOD_RESET_A STD_BY
+3.3V CC28 22n
XC02-T27 XC02-T61 9 10 10 20 GND VCC 1 EN 11 CLK 14 19 13 18 12 17 11 16 10 15 9 14 13 12 RC147 0R0 IC15 74LV574 D 2 14 3 13 4 12 5 11 6 10 7 8 9 8
8
+5V
+5V RC39 OPT 10k
IRQ_RDY1
RC43 10k IC18-1 74LVC02 2 1 3 1 +3.3V GND IC18-2 74LVC02 5 6 1 IC18-3 74LVC02 8 10 1 9 +3.3V GND 4 RC150 0R0 2 RC179 47R
GND1=GND
2
1
0
EXTWAIT1
8
RC170 0R0
XC02-B34 XC02-B68 RC29 100R GND1=GND
RC30 100R
9 18 20 10 GND VCC 1 EN 11 CLK 7 6 19 18 17 16 15 14 13 12 IC07 74LV574 D 2 3 4 5 6 7 8 9 7 6 5 4 3 2 1 0 RC158 10k +5V
+3.3V GND 0 1
EB_EXTINT(0:2)
CA_A(0:14) CA_D(0:7) EB_CLK401 EB_OUT(0:2) EB_IN(0:3) EXTDATA(0:31) EXTADDR(0:24)
EXTWAIT
IIC_2(0:1) SC_CONTROL(0:7)
JC29 IC18-4 74LVC02 11 12 1 13
5 4 0 3 2 1 24 0 24
+3.3V GND
ENGINEER
DRAWN BY
SHEET
BLOCK ID
SIZE
SCI
Design Center Motala Sweden
Palm Nils Erik Descrambler block
Sven-Ake Larsson
5 of 11
DATE
C
VARIANT
A3
2001-03-07
TIME PCB
MASTER 55 12212-01
MAIN BOARD
11:57:14
+3.3V_OP RB106 RB01 4k7 33R TB01 BC847B RB105 2 CB02 47n RB04 4k7 CB10 100n RB02 10k 33R CB14 100n IB10 LM317LZ 2 3 OUT IN 1 REF RB104 33R 3 OPT CB15 100n CB12 100n RB103 33R 3 OPT CB13 100n
UARTDO(0:5)
SMARTCARD_IN(0:2)
UPPER BB01-2 DB03 BAV99 RB09 100R DB01 BAV99 RB06 100R CARD_READER RB05 UPPER C5U JB15 10k VCC GND C2U C6U RST VPP C3U C7U CLK IO C4U C8U RFU RFU RB10 S1U S2U 100R S1 S2 C1U VCC2 RB98 CB04 10n DB02 BAV99 243R CB08
OPTION
UARTDI(0:5)
RB23 18R
SMART_C_3.3_5V
RB96 OPT 634R TB18 BC847B RB92 OPT 10k
1n0 RB94 732R
+5V_OP RB07 3k3
OPT
DB14 LS4148
+12V_OP +12V_OP +12V_OP RB11 10k 16 VDD TB02 RB12 10k BC847B RB84 RB13 10k 100R 14 +3.3V_OP 15 IB09 BSH111 4 Y Z IB06 4053 JB01 & 12 13 SMARTCARD_SCDATAIO 2 IB08-1 74AC04
Vcc12 GND
CB07 22n 7 VEE TB07 BC807-25 RB26 6R8
8 VSS
11 10 9 6
A B C
RB24 10k
RB28 1k0
INH RB25 2k2 MUX/DX X X0 X1 Y0 Y1 Z0 Z1 12 13 2 1 5 3
OPTION OPTION OPTION JB04 JB05 JB06
TB08 BC847B
RB30 4k7
TB09 BC857B RB31 4k7
TB20 RB88 10k BC847B 6 4 +3.3V_OP
+3.3V_OP GND
THIS DRAWING IS PROPERTY OF SCI DESIGN CENTER AND MUST NOT BE COPIED OR SHOWN OR GIVEN TO THIRD PERSON. VIOLATION OF THESE STIPULATIONS WILL BE SUBJECT TO LEGAL MEASURES ACCORDING TO EXISTING LAW.
RB87 10k
JB02 JB03 1 1 6 IB08-3 74AC04
Vcc12 GND
GND
Vcc12 RB16 5k6 RB85 12k RB90 1k5 SC_RST
Vcc12 GND
9
1
Vcc12
3
IB08-2 74AC04
1
4
8
5
Vcc12 RB15 5k6
RB59 4k7
IB08-4 74AC04
1
RB91 1k5 SC_VCC2 SC_CLKS RB86 12k SC_SEL
0 Vcc12 CB05 22n
3
2
4
RB99 IB08-5 74AC04
Vcc12 GND
IB05 LM317LZ 2 3 OUT IN 1 REF
RB49 18R
1
1
DB16 LL103C IB08-6 74AC04
Vcc12 GND
243R CB09 OPT 1n0 RB95 732R RB97 OPT 634R TB19 BC847B RB93 OPT 10k
10
12
11
13
Vcc12 DB15 LL103C
OPT
SC_SEL 4 +5V_OP RB38 10k +12V_OP +3.3V_OP RB39 3k3 VCC1 CB01 10n LOWER BB01-1 CARD_READER C1 C5 RB45 VCC GND C2 100R C6 RST VPP C7 C3 RB46 100R IO CLK C4 OPTRB47 100R C8 RFU RFU S2A S1 OPT OPT S1 S2B RB48 OPT S2 100R DB08 BAV99 +5V_OP RB43 OPT 10k 6 SC_RSRVD +5V_OP SC_PWREN OPT JB08 5 SC_RESET OPT JB09 OPT RB74 10k 3 DB09 BAV99 TB14 BC807-25 RB55 6R8 TB15 BC857B
+3.3V_OP
5
IB03-4 74HC08T
IB03-2 74HC08T
+3.3V_OP GND
11
&
RB100 OPT 10k TB21 BC847B OPT OPT RB89 10k
RB76 4k7
JB14
RB51 10k DB11 BAV99
RB57 1k0
TB17 1 BC847B
DB06 BAV99
RB41 100R
RB50 2k2 TB16 BC847B RB53 10k DB12 LS4148
RB58 4k7
CB03 47n RB77 4k7 CB11 100n RB73 10k RB40 OPT 4R7
DB10 BAV99
+3.3V_OP 8 IB03-3 74HC08T
+3.3V_OP GND
1
2
OPT JB07 SC_PROGV SC_IO1
RB42 4k7OPT 1SC_SENSE
+3.3V_OP GND
&
IB03-1 +3.3V 74HC08T LS4148 DB18 OPT
TB03 BC847B OPT
OPT
OPT
0 SC_CLK
4 SC_IO2
10
DB19 LS4148
9
&
CB06 22n
3
OPT RB44 4k7 SC_CONTROL(0:7)
DB17 LS4148 RB54 100k
SC_CONTROL(0:7)
RB101 0R0 SC_VCC1
RB102 0R0
RB29 OPT 2k2
RB03 33k
7
2
+3.3V_OP 2 RB52 10k RB61 10k
SMARTCARD_OUT(0:4) ENGINEER DRAWN BY SHEET BLOCK ID SIZE
SCI
Design Center Motala Sweden
Palm Nils Erik Smartcard block
Sven-Ake Larsson
TIME
6 of 11
DATE
B
VARIANT PCB
A4P
2001-03-07 11:57:14
MASTER 55 12212-01
MAIN BOARD
IIC(0:1) FBLK_IN
TV_CVBS_OUT +12V_OP RA159 4k7 TA22 BC857B OPT JA20 JA21 CVBS_ANALOGUE RA04 47R CA01 470p CA03 33p LA01 3u9 OPT CA02 82p RA07 820R OPT CA06 10u +12V_OP CA04 180p RA06 RA160 330R 4k7 TA23 CA21 BC857B 33p LA07 3u9 OPT CA20 150p CA22 220p RA161 4k7 CA15 33p CA13 330p CA14OPT 150p LA05 3u9 LA06 10u +12V_OP CA16 220p RA162 4k7 CA09 33p LA03 3u9 CA08OPT 150p RA08 82R LA04 10u CA17 68p RA15 390R JA12 JA11 RA146 TA25 BC857B 820R OPT CA12 10u RA11 390R RA173 0R0 OPT CA69 10u DA01 OPT DA02 OPT LS4148 LS4148 RA127 33R LA08 10u +12V_OP CA23 68p RA19 390R 1 2 JA14 JA13 RA176 1k0 CA32 100u 3 4 5 6 7 8 9 10 11 RA128 33R 12 13 14 15 16 17 18 RA138 270R RA140 2k43 0 A_R_in RA139 10k RA143 2k43 RA142 10k CA86 1u0 OPT CA70 10u JA02 CA71 10u JA15 OPT 19 LIN1 VIN5 1 2 3 JA22 B G R SYNC_CVBS OPT XA05-1 XA05-3 XA05-5 XA05-7 XA05-9 XA05-11 XA05-13 XA05-15 XA05-2 XA05-4 XA05-6 XA05-8 XA05-10 XA05-12 XA05-14 XA05-16 CVBS_SECAM AUX_PIN8 17
RA122
OPT 0R0 RA64 1k0 1 IR_TRANSMIT DA10 DA09 TSIP5201 TSIP5201 TA13 BC337-25
RA65 2R7
RA66 2R7 +5V +12V_A RA67 1R5 +12V CA44 1000u
RA123 OPT 0R0 IR_TRANSMIT 1 SPDIF 0 0 16 JA01 RA174 0R0 OPT RA28 100k RA29 100k RA27 100k RA164 2k2 RA163 2k2 TA27 BC847B
REMOTECONTROL_SIRCSO AUDIO_OUT(0:4)
TV_CVBS_OUT 16
OPT RA24 4k7
OPT TA08 BC857B
+12V
FA01 628LHN-1729 6 4
+12V_A 7 RF_A_MONO RA34 6k8 OPT TA02 BC847B RA35 100R OPT TA03 BC857B 23 RF_CVBS +12V_A RA37 0R0 RA38 OPT 100R RA71 180k 16 TV_CVBS_OUT TV_FB_OUT +12V_A 11 RA72 +5V 39k RA78 220R RA74 2k2 TA16 BC847B TA14 BC847B RA73 100R
RA157 22k TA26 BC807-25
RF_A_MONO RF_CVBS
TA15 BC557B
CA35 100n CA36 OPT 47u DA11 BAV21 OPT RA185 15k CA37 100n
RA158 22k +12V_OP +5V_OP 10u CA78 CA33 47u CA34 100n
RA133 OPT 39k
RA36 2k2
RA121 82R RA75 0R0 RA76 100R RA80 120R RA77 75R 0
21A 20A 19A 18A 17A 16A 1 15A 14A 12A 11A 10A 9A A3 13A A2 A1
COMPOUT_CVBS
RA03 120R
RA05 100R
LA02 10u
CA05 68p
TA01 BC547B
RA82 RA83
75R 75R
BOUT 2
RA18 220R
CA24 10u 64 63 62 61 60 59 58 57 56 55 54 53 52 CA38 47u 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DA04 BZV55C4V7 OPT DA05 BZV55C4V7 OPT RA169 100R CA39 100n
OPT RA134 39k +12V_A
TV_B_OUT RA42 2k2 19 AV_LINK RA84 2k7 TA17 BC847B
3
VIDEO_VCC
LIN5
FBLK_IN
VREG_BASE
VIN3
RIN1
VIN1
RIN5
VOUT1
FBLK_OUT
VREG_9V
VCC_12V
VOUT2
RA16 82R RA13 0R0 (Y) GOUT 1 RA14 220R
8A 4 5 7A 6A 5A 4A 3A RA89 100R RA181 12k OPT RA93 470R RA94 RA183 0R0 OPT 2A 1A XA01-2 GND1=GND RA188 OPT 100R TA28 BC847B XA02-4 +12V_A A4
RA145 TA24 BC857B 820R OPT CA18 10u
RTV VOUT3 LTV VOUT4 DIG_VCC LOG_1 LOG_2 LOG_3 LOG_4 DIG_GND FBLK_IN1 HWMUTE LIN4 FNC_TVA FNC_TVB RIN4 TRAP
RA46 6k8 OPT
TA06 BC847B
RA47 100R
TA07 OPT BC857B RA50 OPT 100R
13 TV_PIN8_12V
RA85 10k RA86 2k7
BIAS_VIDEO VIN9 FNC_VCR VIN6 FNC_AUX VIN10 VIDEO_GND SCL SDA ADR AUDIO_GND VIN7 RIN2 VIN11 LIN2 BIAS_AUDIO AUDIO_VCC VIN2 RIN3 VIN4 VIN8 LIN3 IA02 CXA2092Q
RA49 0R0 OPTRA135 39k RA48 2k2
RA88 1k0
RA90 1k0
12 TV_PIN8_6V
RA12 82R RA09 0R0 (C) ROUT 0 RA10 220R
TA18 BC847B RA87 10k CA50 10u
CA07 330p
0 1
2 TV_A_L_OUT TV_A_R_OUT 3 3 TV_A_R_OUT
THIS DRAWING IS PROPERTY OF SCI DESIGN CENTER AND MUST NOT BE COPIED OR SHOWN OR GIVEN TO THIRD PERSON. VIOLATION OF THESE STIPULATIONS WILL BE SUBJECT TO LEGAL MEASURES ACCORDING TO EXISTING LAW.
RGB_OUT(0:2)
CA10 220p
CA11 68p
RA199 CA90 1k5 2 CVBS_IN
TV_A_L_OUT 2 TV_PIN8_12V 13 TV_PIN8_6V 12 RA30 1k8 RF_A_MONO AUX_FB_IN +12V_A 7 5
CA51 10u
RA91 100k
RA92 100k +3.3V CA74 22n IA07-1 74LVT125 1
220p RA137 220R
MONOTV ROUT2 VOUT7 VOUT6 VOUT5 LOUT2 LOUT1 ROUT1 VOUT8
470R RA189 OPT 2k2 RA190 OPT 2k2 RA95 470R RA96 470R
OPT RA25 100R
RA182 OPT 68R RA184 OPT 4k7
XA02-3 XA02-5 XA02-2 XA02-1 CA84 100n
SPDIF CVBS out Audio Left ch Audio Right ch
BUS_1(0:5)
PAL_A_V(0:2)
VIN12
20
28
21
22
23
24
25
26
27
29
30
31
32
0 +12V_A RA124 47k TA10 BC857B RA125 47k RA147 1k5
EN 3 +3.3V GND
DA03 BAV99
SPDIF
2
RA153 180R CA87 470p
RA177 220R
RA178 220R
1
A_L_in
CA40 47u
RA31 68R TA21 BC847B 8 AUX_A_R_OUT
15 AUX_CVBS_IN
6 AUX_A_L_OUT
RA154 10 AUX_A_R_IN 22 AUX_B_IN 100k
RA155 20 AUX_G_IN 21 AUX_R_IN 100k 9 AUX_A_L_IN RA156 100k
AUX_CVBS_OUT 14
CA41 CA42 47u 100n
RA126 22k 15 AUX_CVBS_IN RA141OPT 1k0 RA187 82R RA98 100R RF_CVBS 23 +12V_A
CA52 10u
RA20 470R RA21 470R CA25 3n3 CA26 3n3 IA08 UDA1320ATS 4 RA171 1R0 RA172 1R0 CA77 47u 2 3 4 CA81 100n 5 13 15 12 3 1 2 6 VDDD VSSD VDDA VSSA VREF DATAI BCK WS SYSCLK VOL VOR 14 16 APPSEL APPL0 APPL1 APPL2 APPL3 7 11 10 9 8 RA168OPT 1k0 RA166 1k0 RA165 1k0
RA22 470R
CA27 1u0 CA28 1u0
RA193 0R0 RA194 0R0 RA195 0R0 RA196 0R0 RA197 0R0 RA198 0R0 RA97 75R
0 1 2 3 4 5
0 1 2 3 4 5
CA79CA76CA80 100n 47u 100n +3.3V
RA23 470R
CA60 1u0
CA61 1u0
JA18 OPT JA19 OPT A_V_signals(0:23) 14 AUX_CVBS_OUT TA19 BC847B RA99 2k2 17 AUX_PIN8 RA100 0R0
OPT
TA20 BC857B
RA101 OPT 100R RA102 75R
BUS_2(0:5)
RA167 1k0 RA117 10k RA118 10k 1 2 3 4 CA63 10u PAL_NTSC_SW IA02_STBY RA129 33R 5 6 7 8 9 RA130 33R 10 IA06 CXA1846 20 19 18 17 16 15 13 12 11 CA62 47u CA65 10u +12V CA64 10u +5V RA120 10k RA119 10k
INP2 INN2 VCT2 INAO2 VRIN2 OUT2 CE DATA CLK INIT
INP1 INN1 VCT1 INAO1 VRIN1 OUT1 GND VCT VCC
+3.3V DA13 LS4148 5 AUX_FB_IN CA53 10u CA54 10u CA55 10u JA23
DA14 LS4148 RA103 6k8 0 CA85 10n GND 1 2
21B 20B 19B 18B 17B 16B 15B 14B 13B 12B 11B 3 10B 9B 8B
PCMCLK
RA170 47R
BG_L-NORM
RA01 220R
RA02 22k AV_LINK CA89 100p 19
21
AUX_R_IN
20
AUX_G_IN
24
CA83 1n0
22 4
AUX_B_IN AV_LINK
EXTDATA(0:31)
+5V JA16 OPT +3.3V CA82 22n 16 8 VCC GND D MR LE A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 IA04 74LV259 4 5 6 7 9 10 11 12 13 15 14 1 2 3 +5V +3.3V JA09 OPT CA31 22n 16 8 VCC GND D MR LE A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 IA05 74LV259 1 4 5 6 7 9 10 11 12 RA175 0R0 RA151 0R0 4
RA104 75R
RA105 75R
RA106 75R
RA107 75R
JA17
9 AUX_A_L_IN 10 AUX_A_R_IN 6 AUX_A_L_OUT 8 AUX_A_R_OUT CA58 10u CA59 10u RA111 100k RA112 100k
RA108 470R RA109 RA110 470R 470R
CA56 1u0 CA57 1u0
4 5
7B 6B 5B 4B 3B 2B 1B
JA10
13
RESET LATCH_CONTROL3
2 3 4
15 14 1 2 3
RA113 470R RA191 OPT 2k2 RA192 OPT 2k2 RA114 15k RA115 15k
LATCH_CONTROL2 PAL_DVB CH3:4 TUNE_IN
2 IA07-2 74LVT125 4 EN 6 +3.3V GND 3 4
Composite video Audio
CA_5V_CTRL FRONTEND_SCL FRONTEND_SDA FRONTEND_C1 FRONTEND_C2
XA01-1 GND1=GND
VREF_TRIM_TRIS 5
VREF_TRIM
RESET_DMA
T06
RA116 100R
T05
ENGINEER
DRAWN BY
SHEET
BLOCK ID
SIZE
EXTADDR(0:24) IIC_2(0:1)
T07
SCI
Design Center Motala Sweden
Palm Nils Erik Audio/video block
Sven-Ake Larsson
7 of 11
DATE
A
VARIANT
2001-03-07
TIME PCB
MASTER 55 12212-01
MAIN BOARD
11:57:14
AUX SCART
A6
A3
TV SCART
RA17 0R0
CA19 330p
RA144 820R OPT
DA06 BAV21
OPT DA12 BAV21
RA40 6k8 OPT
TA04 BC847B
RA41 100R
OPT
TA05 BC857B
11 TV_FB_OUT
RA152 RA79 680R 220R
RA186 15k
RA43 0R0
RA44 OPT 100R
TV_R_OUT TV_G_OUT
RA81
75R
2
IE03-2 74LVC04 3 4 1
+3.3V GND
IE03-3 74LVC04 5 6 1
+3.3V GND
+3.3V
+3.3V
IE03-4 74LVC04 9 8 1 CE16 22n CE17 22n
+3.3V GND
IE03-5 74LVC04 11 10 1
+3.3V GND
IE03-6 74LVC04 13 12 1
+3.3V GND
CE19 22n
+5V
CE14 22n
CE15 22n
IE03-1 74LVC04 1 2 1
XE01-1 XE01-2 XE01-3 XE01-4 XE01-5 XE01-6
THIS DRAWING IS PROPERTY OF SCI DESIGN CENTER AND MUST NOT BE COPIED OR SHOWN OR GIVEN TO THIRD PERSON. VIOLATION OF THESE STIPULATIONS WILL BE SUBJECT TO LEGAL MEASURES ACCORDING TO EXISTING LAW.
+3.3V +5V 7 18 31 42 0 1 2 IE01-2 74LVT125 RE01 68R EN 6
+3.3V GND
IE02 PDI1284P11 VCC VCC VCCB VCCB A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 HD PLHI HLHI
+3.3V GND
GND GND GND OEA B1 B2 B3 B4 B5 B6 B7 B8 Y9 Y10 Y11 Y12 Y13 C14 C15 C16 C17 DIR PLHO HLHO
10 15 39 34 41 40 38 37 36 35 33 32 47 46 45 44 43 29 28 27 26 48 30 24 0
XE01-7 XE01-8 XE01-9 XE01-10 XE01-11 XE01-12 XE01-13 XE01-14 XE01-15 XE01-16 XE01-17
HSDI_DATA(0:7)
8 9 11 12 13 14 16 17 1 8 7 5 0 2 3 4 5 6 20 21 22 23 1
3 4 5 4 5 6 7 1 2
IE01-1 74LVT125 +3.3V RE02 68R EN 3
+3.3V GND
CE18 22n
2 4 6 3 RE03 68R 11
IE01-4 74LVT125 EN
+3.3V GND
13 12
XE01-18 XE01-19 XE01-20 XE01-21 XE01-22 XE01-23 XE01-24 1 XE01-25 XE01-26 XE01-27
IE01-3 74LVT125 RE04 68R EN 8
+3.3V GND
10 9
19 25
HSDI_SIG(0:8)
1284_LEVEL
HSDI_STATUS(0:1)
ENGINEER
DRAWN BY
SHEET
BLOCK ID
SIZE
SCI
Design Center Motala Sweden
Palm Nils Erik 1284 block
Sven-Ake Larsson
TIME
8 of 11
DATE
E
VARIANT PCB
A4P
2001-03-07 11:57:14
MASTER 55 12212-01
MAIN BOARD
DS25 LS4148 TS01 BC847B RS45 10k RESET_OVERLOAD
TS06 BC857B
RS46 1k0 +5V
+5V
RS17 22k
RS47 47k
CS38 100n
TS05 BC847B
TS11 BC847B
RS83 2k2
RS32 2k2 TS13 RS33 BC847B 8k2 RS44 4k7
LNB_LARM
LNB-ON_OFF
RS82 OPT 10k LS04 68n OPT LS05 68n OPT CS64 470u DS32 UG2D LS12 BLM41P600S JS01 OPT
RS34 5k6
IIC_2(0:1)
1 OPTRS38 10k
+3.3V_SEP
+23V LNB_IN(0:1)
NOTE:SMD-JUMPER GND_SEP
DS22 1N4002 Jumper DS29 0 OPT DS31 JS04 1N5819 1 JS03
OPT DS30 1N4002
JS05
DS26 MBRB745 MS1
LS10 10u CS59 2200u CS60 1u0
+3.3V
LNB_Y
JS06
LNB_X
TS21
+300V
17 CS40 10n RS60 9k1 RS61 9k1 RS62 9k1 CS51 47p KS01 S1 DS01 DS02 1N4007 1N4007 2 LS03 1 3 XS01-2 LS02 20u LS15 20u 4 DS04 1N4007 CS05 47u CS02B 100u RS01 47R 2x47m CS01 DS03 100n 1N4007 CS02 47u CS03 100n DS05 P6KE200 3 DS06 UF4005 6 1 4 18 16 15 14 13 12 11 10 2 1 LS01 XS01-1 20u LS14 FS01 SOURCE DRAIN CONTROL IS01 TOP224Y DS07 BAV203 CS04 100n RS16 1k0 RS03 100R 3 LS11 TRANSFORMER
RS86 56k TS20
RS85 68k RS90 2k2 CS66 33n DS33 OPT 1N4002 LS13 220u
RS73 OPT 10k
OPT TS16 BC369
RS42 1k8 RS74 OPT 10k
RS81 OPT OPT TS17 1k8 BC369
CS08 22u
S3 DS09 BAV21 CS09 22u LS06 10u LS07 10u RS04 3k32
DS10 BZX55B33 CS10 100n +23V CS12 47u OPTCS31 100n OPTCS30 100n RS63 15k
DISEQ +33V
BC847B BC847B RS88 10k CS65 47n RS89 8k2
RS78 RS79 OPT OPT 3k3 3k3 JS10 OPT RS84 18R RS71 RS75 OPT OPT 33k 10k TS18 BC847B
RS77 RS80 OPT 3k3 OPT 3k3 TS19 BC847B OPT RS72 OPT OPT 33k
RS59 9k1
THIS DRAWING IS PROPERTY OF SCI DESIGN CENTER AND MUST NOT BE COPIED OR SHOWN OR GIVEN TO THIRD PERSON. VIOLATION OF THESE STIPULATIONS WILL BE SUBJECT TO LEGAL MEASURES ACCORDING TO EXISTING LAW.
DS11 UG2D DS12 UG2D RS02 1R1
DS08 UG2D CS11 470u
RS87 27k
KS03 S7
CS13 470u DS14 UG2D CS15 1000u LS08 10u
+19V
IS04 LM317T
CS50 1n0 2 1 CS26 22n RS25 243R
+12V
OPT LS08B BLM41P600S 10u CS19 100u 5 6 7 8 4 2 3 JS08 OPT JS07 IS03 L4941BDT 1 3 IN OUT 2 REF CS20 100n RS93 0R0 IS07 LF25ABDT 1 3 IN OUT 2 REF CS67 22u CS32 1u0
3
IN OUT REF
RS55 1R1
20u T1.25A
+6V
TS15 MMSF5N02HD DRAIN GATE 4 2 3 10k
+3,3V
RS21 TS07 BC369
CS25 47u
LS09 CS06 2n2 OPT DS15 MBRB745
CS18 2200u
DRAIN SOURCE DRAIN SOURCE DRAIN
+3,3V_OP +5V +5V_OP
TS08 BC847B
RS22 2k74
RS26 8k25 RS24 3k83 RS23 68k
TS09 BC847B
CS07 2n2 S2
TS02 MMSF5N02HD 5 6 7 8 DRAIN GATE CS33 1u0
RS28 8k2
13_18V-CONTROL
+13V
DRAIN SOURCE DRAIN SOURCE DRAIN
RS27 6k8
+5.7V
DS19B PC123FY 4 3 1 2 DS23 LS4148 RS10 3k09 RS08 82R RS56 680R
RS29 68k
TS10 BC847B RS30 6k8
RS31 13_18V-ADJUST 8k2
+2,5V
+5V RS37 RS35 RS51 1k0 680R CS27 RS36 3k3 CS29 5n6 75k LM393 IS05-1 1
GND +5V
+1.24V
REF 5
CS68OPT 100u
CS23 22u
+5V RS57 10k0 +5V IS05-2 LM393 COMP 7 +
+5V GND
RS11 1k82 CS22 100n
COMP S8 RS39 270k
2
RS43 4k7
+12V 6 5 CS37 22u RS07 0R0 TS03 2SD1858
RS40 100k
+12V_OP
CS41 47u RS15 1k00 RS19 4k7 CS42 100n RS91 1k00
CS28 150p
TS04 BC847B
STD_BY EXTADDR(0:24) EXTDATA(0:31)
IS06 74LV259 24 13 15 14 1 2 3 +3.3V +3.3V CS63 22n
CS34 47u
RS18 4k7
16 8 VCC GND D MR LE A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 4 5 6 7 9 10 11 12 LNBY LNBX
RESET SAT_SW_WR
2 3 4
TS22 BC857B
LIGHT_DISPLAY
RS94 1k0
ENGINEER
DRAWN BY
SHEET
22kHZ-ON_OFF
CS47 10n
CS36 100u
RS58 4 1k0 3
RS41 + 3 33k
IS02 TLV431
RS12 1k0
RS70 1k0
1u0
BLOCK ID
SIZE
SCI
Design Center Motala Sweden
Palm Nils Erik Power block
Sven-Ake Larsson
9 of 11
DATE
S
VARIANT
A3
2001-03-07
TIME PCB
MASTER 55 12212-01
MAIN BOARD
11:57:14
+5V_OP
+33V CVBS_A_IN(0:1)
+10V_OP
CF23 10n +3.3V_OP
CF20 10n +12V
ansluts till pin 7
CF22 10n
FRONTEND_SCL FRONTEND_SDA IIC(0:1)
CF13 10n LF01 68n UF06 CABLE_MODEM AUDIO_IN VIDEO_IN 12V_SPLIT SCL SDA ADSW +12V +33V +5V SCL SDA ADSW +5V SCL SDA +3V3 +12V IRQ FS D7 D6 D5 D4 D3 D2 D1 D0 DV CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 +5V +3.3V_OP +5V_OP +3.3V RF45 OPT 330R OPTRF34 150R +3.3V OPT RF44 0R0 3 8 1 5 7 +3.3V CF27 180p 0 0 RF25 100R 2 1 4 3 JF22 6 5 7 2 4 6 3 0 1 UF05 QPSK LNB_Y LNB_X 12V_SPL CL DA EN +12V +33V +5V SCL SDA ADSW +5V SCL SDA +3V3 NC IRQ FS D7 D6 D5 D4 D3 D2 D1 D0 DV CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 UF03 OFDM NOT_MOUNTED 1 AUDIO_IN 2 VIDEO_IN 3 12V_SPLIT 4 SCL 5 SDA 6 ADSW 7 +12V 8 +33V 9 +5V 10 SCL 11 SDA 12 ADSW 13 +5V 14 SCL 15 SDA 16 +3V3 +12V IRQ FS D7 D6 D5 D4 D3 D2 D1 D0 DV CLK 18 19 20 21 22 23 24 25 26 27 28 29 30 RF07 33R 9 7 6 5 4 3 2 1 0 10 8 JF02 LF02 OPT68n RF02 0R0 CF14 100n OPT 0 1 1 0 RF01 0R0 +12V RF03 OPT10k CF35 1n0 RF04 OPT OPT 10k +5V_OP UF04 AM-VSB AUDIO_IN VIDEO_IN 12V_SPLIT SCL SDA ADSW +12V +33V +5V JF16 SCL SDA ADSW +5V_OP +5V SCL SDA +3.3V_OP +12V_OP +3V3 +12V IRQ FS D7 D6 D5 D4 D3 D2 D1 D0 DV CLK GND +5V_OP SOUND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 JF21 OPT 1 +12V_OP RF38 OPT 10k NOT MOUNTED UF01 OFDM 1 AUDIO_IN 2 VIDEO_IN 3 12V_SPLIT 4 SCL 5 SDA 6 ADSW 7 +12V 8 +33V 9 +5V 10 SCL 11 SDA 12 ADSW 13 +5V 14 SCL 15 SDA 16 +3V3 +12V IRQ FS D7 D6 D5 D4 D3 D2 D1 D0 DV 18 19 20 21 22 23 24 25 26 27 28 29 UF02 QAM AUDIO_IN VIDEO_IN 12V_SPLIT SCL SDA ADSW +12V +33V +5V SCL SDA ADSW +5V SCL SDA +3V3 +12V IRQ FS D7 D6 D5 D4 D3 D2 D1 D0 DV CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 33R RF37 10k RF39 0R0 9 7 6 5 4 3 2 1 0 10 RF10 8 +5V_OP +5V_OP RF19 10k RF20 0R0 MUX/DX 12 14 X0 X 13 X1 2 15 Y0 Y 1 Y1 5 4 Z0 Z 3 Z1 IF01 74HCT4053 +12V_OP CF12 100n +12V_OP +3.3V_OP
OPTION
CF24 10n
CF21 10n
LNB_IN(0:1)
+5V RF17 0R0 JF03 +12V CF15 10n CF19 10n +12V_OP JF17 +33V +5V_F +3.3V_OP RF47 IF03 5k6 BSH111 IF02 BSH111 RF08 33R 0 +12V 1 1 RF35 0R0 RF36 0R0 RF15 100k RF16 100k +33V
0 RF18 0R0
+10V_OP JF19 OPT JF15 CF31 100n +33V +5V_F
JF18 OPT +5V_OP
RF48 5k6
OPTION
RF09 33R
CF01 100n
+5V
VEE
VSS
VDD
JF25
JF24
7
8
16 A B C INH 11 10 9 6 RF26 100R
+12V_OP
CF16 10n +5V_OP
CF33 1u0
CF17 10n
CF04 100u
+6V TF01 BC818-40 +5V_F
THIS DRAWING IS PROPERTY OF SCI DESIGN CENTER AND MUST NOT BE COPIED OR SHOWN OR GIVEN TO THIRD PERSON. VIOLATION OF THESE STIPULATIONS WILL BE SUBJECT TO LEGAL MEASURES ACCORDING TO EXISTING LAW.
Body connected to: GND
Body connected to: GND
30 CLK Body connected to: GND
Body connected to: GND
RF21 0R0
HSDI_STATUS(0:1)
NICAM +12V_OP SCL SDA SOUND2 VIDEO TUNE DVB-PAL NS1 NS2
RF22 0R0
RF42 470R DF01 BZV55C5V6
CF32 1u0
HSDI_SIG(0:8) HSDI_DATA(0:7)
+12V_OP TF02 BC818-40
+10V_OP
TUNE_IN PAL_DVB BG_L-NORM
0
+3.3V_OP
RF43 270R CF03 10u
JF20
OPTION
FRONTEND_C2
2
Body connected to: GND
CF18 10n
CF05 100u
PAL_A_V(0:2) MOD_RESET_B
RF27 33R JF09 JF10 OPT JF08 JF07 OPT RF24 220R +33V JF05 JF06 OPT 1 2 3 4 5 6 7 DATA CLOCK VIDEO TU+B AUDIO MD+B 1 2 3 4 5 VIDEO AUDIO MD+B CTRL OPT CHSEL 1 0
MDO_EC(0:10) FRONTEND_C1
CF29 33p LF06 8u2 CF28 150p 0 1
RF28 33R
RF_CVBS
GENERAL_IO(0:5)
RF33 4k7 1
CF34
JF11 JF12 JF14 OPT
RF_A_MONO
22u +5V_OP
EB_EXTINT(0:2) RESET_DMA EB_CLK403
+5V
LF04 15u JF23 OPT LF03 15u
BST+B UF08 MDLM5 UF07 MDLM3E502A Body connected to: GND Body connected to: GND
CF11 47u
CF26 4n7
RF46 2k2
JF13 OPT LF05
CF10 47u
+5V
RF40 10k OPT
RF41 10k OPT
4u7
CF25 1n0
CH3:4
Body connected to: GND
ENGINEER
DRAWN BY
SHEET
BLOCK ID
SIZE
SCI
Design Center Motala Sweden
Palm Nils Erik Frontend block
Sven-Ake Larsson
10 of 11
DATE
F
VARIANT
A3
2001-03-07
TIME PCB
MASTER 55 12212-01
MAIN BOARD
11:57:14
+5V +3.3V CG13 100n CG12 100n IG02-3 +5V RG15 47R IG01-1 74HCT74 4 2 3 1 R IG02-2 GND 74LVC02 5 4 1 6 +5V IG01-2 74HCT74 10 12 11 13 R
+5V GND +3.3V GND +5V
+5V
HVSYNC(0:1)
RG13 470R IG02-4 IG02-1 74LVC02 74LVC02 11 13 2 1 12 1 3 1
+3.3V GND +3.3V GND
1 RG14 3k3
74LVC02 8 10 9 1
+3.3V GND
S 1D C1
5 6
TG01 BC847B
PAL_DVB
RG02 1k0
VCO_CNT
RG03 1k0 CG01 100n +5V
S 1D C1
9 8 TG02 BC857B RG04 6k8 IG04-2 74HC4538 CG02 10n 15 14 12 11 +5V 13 R
+5V GND
C R 10 9
THIS DRAWING IS PROPERTY OF SCI DESIGN CENTER AND MUST NOT BE COPIED OR SHOWN OR GIVEN TO THIRD PERSON. VIOLATION OF THESE STIPULATIONS WILL BE SUBJECT TO LEGAL MEASURES ACCORDING TO EXISTING LAW.
DG01 LL103C
+5V
+5V IG04-1 74HC4538 CG10 2u2 1 2 4 8 4 VSUP GND 5 +5V 1 3 5 7 RG11 1k0 RG10 1k0 3 R
+5V GND
CG11 100n
LG01 15u +5V CG14 1u0
RG12 39k CG07 100n
C R 6 7
INT_VER
PAL_A_V(0:2)
2
RG05 470R
CG05 2u2 RG06 1M0 CG06 100n
6 2
RSET VIDEO CSYNC VSYNC BURST FIELD INDEX IG03 LM1881M
CG03 680p
CG04 150p
RG07 2M2
O_E
CG08 470p CG09 470p
TG04 BC847B
RG09 4k7
TG03 BC847B
RG08 4k7
ENGINEER
DRAWN BY
SHEET
BLOCK ID
SIZE
SCI
Design Center Motala Sweden
Palm Nils Erik
Sven-Ake Larsson
11 of 11
DATE
G
VARIANT PCB
A4P
OSD PAL sync block
2001-03-07
TIME
MASTER 55 12212-01
MAIN BOARD
11:57:14