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INTEGRATED CIRCUITS
DATA SHEET
TDA8356 DC-coupled vertical deflection circuit
Product specification Supersedes data of 1998 Sep 07 File under Integrated Circuits, IC02 1999 Sep 27
Philips Semiconductors
Product specification
DC-coupled vertical deflection circuit
FEATURES · Few external components · Highly efficient fully DC-coupled vertical output bridge circuit · Vertical flyback switch · Guard circuit · Protection against: Short-circuit of the output pins (7 and 4) Short-circuit of the output pins to VP. · Temperature protection · High EMC immunity because of common mode inputs · A guard signal in zoom mode. QUICK REFERENCE DATA SYMBOL DC supply VP Iq Vertical circuit IO(p-p) Idiff(p-p) Vdiff(p-p) Flyback switch IM VFB Tstg Tamb Tvj peak output current flyback supply voltage - - -55 -25 - - - - - - ±1 50 output current (peak-to-peak value) differential input current (peak-to-peak value) differential input voltage (peak-to-peak value) - - - - 600 1.5 2 - 1.8 supply voltage quiescent supply current 9 - 14.5 30 25 - PARAMETER MIN. TYP. GENERAL DESCRIPTION
TDA8356
The TDA8356 is a power circuit for use in 90° and 110° colour deflection systems for field frequencies of 50 to 120 Hz. The circuit provides a DC driven vertical deflection output circuit, operating as a highly efficient class G system.
MAX.
UNIT
V mA
A µA V
A V °C °C °C
Thermal data (in accordance with IEC 747-1) storage temperature operating ambient temperature virtual junction temperature +150 +75 150
ORDERING INFORMATION TYPE NUMBER TDA8356 PACKAGE NAME SIL9P DESCRIPTION plastic single in-line power package; 9 leads VERSION SOT131-2
1999 Sep 27
2
Philips Semiconductors
Product specification
DC-coupled vertical deflection circuit
BLOCK DIAGRAM
TDA8356
handbook, full pagewidth
VP VO(guard)
VFB 6
3 VP
8
CURRENT SOURCE
TDA8356
VP 7 VO(A) IS IT IT 9 VP V I(fb) VO(A)
I drive(pos)
1
I drive(neg)
2 V IS
4 VO(B)
VO(B)
5 GND
MGC091
Fig.1 Block diagram.
1999 Sep 27
3
Philips Semiconductors
Product specification
DC-coupled vertical deflection circuit
PINNING SYMBOL Idrive(pos) Idrive(neg) VP VO(B) GND VFB VO(A) VO(guard) VI(fb) PIN 1 2 3 4 5 6 7 8 9 DESCRIPTION input power-stage (positive); includes II(sb) signal bias input power-stage (negative); includes II(sb) signal bias operating supply voltage output voltage B ground input flyback supply voltage output voltage A guard output voltage input feedback voltage FUNCTIONAL DESCRIPTION
TDA8356
The vertical driver circuit is a bridge configuration. The deflection coil is connected between the output amplifiers, which are driven in opposite phase. An external resistor (RM) connected in series with the deflection coil provides internal feedback information. The differential input circuit is voltage driven. The input circuit has been adapted to enable it to be used with the TDA9150, TDA9151B, TDA9160A, TDA9162, TDA8366 and TDA8376 which deliver symmetrical current signals. An external resistor (RCON) connected between the differential input determines the output current through the deflection coil. The relationship between the differential input current and the output current is defined by: Idiff × RCON = Icoil × RM. The output current is adjustable from 0.5 A (p-p) to 2 A (p-p) by varying RM. The maximum input differential voltage is 1.8 V. In the application it is recommended that Vdiff = 1.5 V (typ). This is recommended because of the spread of input current and the spread in the value of RCON. The flyback voltage is determined by an additional supply voltage VFB. The principle of operating with two supply voltages (class G) makes it possible to fix the supply voltage VP optimum for the scan voltage and the second supply voltage VFB optimum for the flyback voltage. Using this method, very high efficiency is achieved. The supply voltage VFB is almost totally available as flyback voltage across the coil, this being possible due to the absence of a decoupling capacitor (not necessary, due to the bridge configuration). Built-in protections are: · Thermal protection · Short-circuit protection of the output pins (pins 4 and 7) · Short-circuit protection of the output pins to VP. A guard circuit VO(guard) is provided. The guard circuit is activated at the following conditions: · During flyback · During short-circuit of the coil and during short-circuit of the output pins (pins 4 and 7) to VP or ground
handbook, 2 columns
I drive(pos)
1 2
I drive(neg) VP VO(B) GND V FB VO(A) VO(guard) V I(fb)
3 4 5 6 7 8 9
MGC092
TDA8356
Metal block connected to substrate pin 5. Metal on back.
· During open loop · When the thermal protection is activated. This signal can be used for blanking the picture tube screen.
Fig.2 Pin configuration.
1999 Sep 27
4
Philips Semiconductors
Product specification
DC-coupled vertical deflection circuit
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL DC supply VP VFB Vertical circuit IO(p-p) VO(A) Flyback switch IM Tstg Tamb Tvj tsc Notes 1. IO maximum determined by current protection. 2. Up to VP = 18 V. THERMAL CHARACTERISTICS SYMBOL Rth vj-c Rth vj-a PARAMETER thermal resistance vj-case thermal resistance vj-ambient in free air CONDITIONS VALUE 4 40 peak output current - -55 -25 - note 2 - output current (peak-to-peak value) output voltage (pin 7) note 1 - - 2 supply voltage flyback supply voltage non-operating - - - PARAMETER CONDITIONS MIN.
TDA8356
MAX.
UNIT
40 25 50
V V V
A V
52 ±1.5 +150 +75 150 1
A °C °C °C hr
Thermal data (in accordance with IEC 747-1) storage temperature operating ambient temperature virtual junction temperature short-circuiting time
UNIT K/W K/W
1999 Sep 27
5
Philips Semiconductors
Product specification
DC-coupled vertical deflection circuit
TDA8356
CHARACTERISTICS VP = 14.5 V; Tamb = 25 °C; VFB = 45 V; fi = 50 Hz; II(sb) = 400 µA; measured in test circuit of Fig.3; unless otherwise specified. SYMBOL DC supply VP VFB IP VO operating supply voltage flyback supply voltage supply current no signal; no load 9.0 VP - 13.2 14.5 - 30 - 25 50 55 - V V mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Vertical circuit output voltage swing (scan) Idiff = 0.6 mA (p-p); Vdiff = 1.8 V (p-p); IO = 2 A (p-p) IO = 2 A (p-p); note 1 IO = 50 mA (p-p); note 1 VO VDF Ios Vos VosT VO(A) Gvo output voltage swing (flyback); VO(A) - VO(B) forward voltage of the internal efficiency diode (VO(A) - VFB) output offset current offset voltage at the input of the feedback amplifier (VI(fb) - VO(B)) output offset voltage as a function of temperature DC output voltage V 7-4 open-loop voltage gain --------- V 1-2 V 7-4 open loop voltage gain --------- ; V 1 2 = 0 V 9-4 VR V 1-2 voltage ratio --------V 9-4 frequency response (-3 dB) current gain (IO/Idiff) current gain drift as a function of temperature signal bias current flyback supply current power supply ripple rejection DC input voltage common mode input voltage input bias current common mode output current II(sb) = 0 II(sb) = 0 II(sb) = 300 µA (p-p); fi = 50 Hz; Idiff = 0 6 during scan note 6 open loop; note 5 Idiff = 0.3 mA; IO = 1 A IO = -1 A; Idiff = 0.3 mA Idiff = 0; II(sb) = 50 to 500 µA Idiff = 0; II(sb) = 50 to 500 µA Idiff = 0 Idiff = 0; note 2 notes 3 and 4 V
LE
linearity error
- - - - - - - - - - - - - - 50 - - - 0 - -
1 1 40 - - - - 6.5 80
4 4 - 1.5 40 24 72 - - - - - - 10-4 500 100 - - 1.6 0.5 -
% % V V mA mV µV/K V dB
note 3
80
dB
0
dB
fres GI GcT II(sb) IFB PSRR VI(DC) VI(CM) Ibias IO(CM)
40 5000 - 400 - 80 2.7 - 0.1 0.2
Hz K µA µA dB V V µA mA
1999 Sep 27
Philips Semiconductors
Product specification
DC-coupled vertical deflection circuit
TDA8356
SYMBOL Guard circuit IO output current
PARAMETER
CONDITIONS
MIN. - 1 4.6 -
TYP. - - - -
MAX. UNIT µA mA V V
not active; VO(guard) = 0 V active; VO(guard) = 3.6 V IO = 100 µA maximum leakage current = 10 µA;
50 2.5 5.5 40
VO(guard)
output voltage on pin 8 allowable voltage on pin 8
Notes 1. The linearity error is measured without S-correction and based on the same measurement principle as performed on the screen. The measuring method is as follows: Divide the output signal I4 - I7 (VRM) into 22 equal parts ranging from 1 to 22 inclusive. Measure the value of two succeeding parts called one block starting with part 2 and 3 (block 1) and ending with part 20 and 21 (block 10). Thus part 1 and 22 are unused. The equations for linearity error for adjacent blocks (LEAB) and linearity error for not adjacent blocks (LENAB) are given below: a max a min ak a( k + 1 LEAB = ---------------------------) ; LENAB = ----------------------------a avg a avg 2. Related to VP. 3. The V values within formulae relate to voltages at or across relative pin numbers, i.e. V7-4/V1-2 = voltage value across pins 7 and 4 divided by voltage value across pins 1 and 2. 4. V9-4 AC short-circuited. 5. Frequency response V7-4/V9-4 is equal to frequency response V7-4/V1-2. 6. At V(ripple) = 500 mV eff; measured across RM; fi = 50 Hz.
1999 Sep 27
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Philips Semiconductors
Product specification
DC-coupled vertical deflection circuit
TDA8356
handbook, full pagewidth
2.2 k VO(guard) 8 I I(sb) signal bias I drive(pos) R CON 3 k I drive(neg) signal bias I I(sb) I diff 2 V 4 1 FEEDBACK 9 INPUT 6 3 VP
VFB
TDA8356
7 R = 6.0
R M = 0.7
5 GND
MGC093
Fig.3 Test diagram.
handbook, full pagewidth
I diff I sb 0
I sb
I sb 1
I diff I diff I diff 2 I diff I sb I sb
MGC094
R CON
TDA8356
I sb 0
Fig.4 Input currents.
1999 Sep 27
8
Philips Semiconductors
Product specification
DC-coupled vertical deflection circuit
APPLICATION INFORMATION
TDA8356
handbook, full pagewidth
VO(guard) 8 6 3
VFB 10 nF 10 µF 100 nF VP 100 µF
II(sb) signal bias Idrive(pos) RCON 3 k Idrive(neg) signal bias II(sb) Idiff 2 V 1
TDA8356
100 nF 7 VO(A) I(coil)
V FEEDBACK 9 I(fB) INPUT 4 VO(B)
deflection coil L = 10.7 mH R = 6.2 RM = 0.8
5 GND
MGC095
VP = 13.5 V; IO(p-p) = 1.87 A; II(sb) = 400 µA; Idiff(p-p) = 500 µA; VFB = 42 V; tFB = 0.6 ms.
Fig.5 Application diagram.
1999 Sep 27
9
Philips Semiconductors
Product specification
DC-coupled vertical deflection circuit
PACKAGE OUTLINE SIL9P: plastic single in-line power package; 9 leads
TDA8356
SOT131-2
non-concave x Dh
D Eh
view B: mounting base side d A2
B seating plane j E
A1 b
L
c 1 Z e bp w M 0 5 scale DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT131-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION A1 max. 2.0 A2 4.6 4.2 b max. 1.1 bp 0.75 0.60 c 0.48 0.38 D (1) 24.0 23.6 d 20.0 19.6 Dh 10 E (1) 12.2 11.8 e 2.54 Eh 6 j 3.4 3.1 L 17.2 16.5 Q 2.1 1.8 w 0.25 x 0.03 Z (1) 2.00 1.45 10 mm 9 Q
ISSUE DATE 92-11-17 95-03-11
1999 Sep 27
10
Philips Semiconductors
Product specification
DC-coupled vertical deflection circuit
SOLDERING Introduction to soldering through-hole mount packages This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. Soldering by dipping or by solder wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joints for more than 5 seconds.
TDA8356
The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds.
Suitability of through-hole mount IC packages for dipping and wave soldering methods SOLDERING METHOD PACKAGE DIPPING DBS, DIP, HDIP, SDIP, SIL Note 1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. suitable suitable(1) WAVE
1999 Sep 27
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Internet: http://www.semiconductors.philips.com
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Printed in The Netherlands
545004/03/pp12
Date of release: 1999
Sep 27
Document order number:
9397 750 06205