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Service Manual

Introduction
This is the Electronic Service Manual for the MP5J1L1 Dual Band GSM Digital Cellular Telephone from NEC. It contains specific information on repair and test procedures. For details on user functions, general operation and installation, please refer to the User Guide. The Service Manual is set out in the following sections. 1. Precautions for Repair Work provides general guidelines for undertaking safe and efficient repair work. Unit Specification provides the technical specifications for the MP5J1L1 GSM Digital Cellular Telephone. Circuit Description provides functional details of the circuits, block diagrams and component purpose descriptions. Servicing defines the jigs, fixtures and test configurations required for servicing the product; and describes the processes of assembly and disassembly. Troubleshooting provides an aid to fault finding the product. Includes; using the engineering functions, signal levels and plots at various parts of the circuit and fault codes. Device Information provides functional information and pin-outs of most of the semiconductor devices within the HHP. Parts provides information for the ordering of replacement parts. Circuit Diagrams and Board Maps contains all the schematics and component layout diagrams. Glossary, terms used in this manual. ,

2.

3.

4.

5.

6.

7. 8.

9.

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Section 2

Unit Specifications

Performance
General
Talktime Standby Dimensions Volume Weight SIM Size RF power output DB2000 (Standard Battery) 150 mins 300 hours 130 x 45.5 x17.5 100cc 130g Plug in SIM Class 4 GSM

Transmitting Frequency Range:

GSM: 890 - 915 Mhz PCN: 1710 - 1785 Mhz GSM: 935 - 960 Mhz PCN: 1805 - 1880 Mhz GSM: 45 MHz / PCN: 95Mhz GSM: 200 Khz / PCN: 200 Khz GSM: 124 (Numbered 1 to 124) PCN: 374 (Numbered 512 to 885)

Receiving Frequency Range:

TX - RX Duplex Spacing: Channel Spacing: Number of Channels:

Transmitter (GSM)
Frequency Stability RF Power Output Power Levels Power Control Level 5 Power Control Level 6 Power Control Level 7 Power Control Level 8 Power Control Level 9 Power Control Level 10 Power Control Level 11 Power Control Level 12 Power Control Level 13 Power Control Level 14 Power Control Level 15 Power Control Level 16 Power Control Level 17 Power Control Level 18 Power Control Level 19 TX Frequency Output Low Channel (Ch 1) Mid Channel (Ch 62) High Channel (Ch 124) TX Frequency Calculation (Ftx) TX UHF VCO Frequency Low Channel (Ch 1) Mid Channel (Ch 62) High Channel (Ch 124) TX UHF VCO Freq. Calculation (Ftuhf) TX VCO Frequency Phase Error Peak Phase Error RMS Phase Error < +/- 90Hz 33dBm 11, decrementing in 2dB steps 33dBm +/-2dB 31dBm +/-3dB 29dBm +/-3dB 27dBm +/-3dB 25dBm +/-3dB 23dBm +/-3dB 21dBm +/-3dB 19dBm +/-3dB 17dBm +/-3dB 15dBm +/-3dB 13dBm +/-3dB 11dBm +/-5dB 9dBm +/-5dB 7dBm +/-5dB 5dBm +/-5dB

890.2 MHz 902.4 MHz 914.8 MHz 890 + (ARFCN x 0.2) = Ftx MHz

1160.2 MHz 1172.4 MHz 1184.8 MHz Ftx + 270 = Ftuhf MHz 270 MHz

< 20 degrees < 5 degrees

Transmitter (PCN)
Frequency Stability RF Power Output Power Levels Power Control Level 0 Power Control Level 1 Power Control Level 2 Power Control Level 3 Power Control Level 4 Power Control Level 5 Power Control Level 6 Power Control Level 7 Power Control Level 8 Power Control Level 9 Power Control Level 10 Power Control Level 11 Power Control Level 12 Power Control Level 13 Power Control Level 14 Power Control Level 15 TX Frequency Output Low Channel (Ch 512) Mid Channel (Ch 699) High Channel (Ch 885) TX Frequency Calculation (Ftx) TX UHF VCO Frequency Low Channel (Ch 512) Mid Channel (Ch 699) High Channel (Ch 885) TX UHF VCO Freq. Calculation (Ftuhf) TX VCO Frequency Phase Error Peak Phase Error RMS Phase Error < +/- 180Hz

30dBm +/-2dB 28dBm +/-3dB 26dBm +/-3dB 24dBm +/-3dB 22dBm +/-3dB 20dBm +/-3dB 18dBm +/-3dB 16dBm +/-3dB 14dBm +/-3dB 12dBm +/-4dB 10dBm +/-4dB 8dBm +/-4dB 6dBm +/-4dB 4dBm +/-4dB 2dBm +/-5dB 0dBm +/-5dB

1710.2 MHz 1747.6 Mhz 1784.8 Mhz 1710.2 + (0.2 x (ARFCN - 512)) = Ftx Mhz

1530.2 Mhz 1567.6 Mhz 1604.8 Mhz Ftx - 180 = Ftuhf MHz 180 Mhz

< 20 degrees < 5 degrees

Receiver (GSM)
RX Frequency Input Low Channel (Ch 1) Mid Channel (Ch 62) High Channel (Ch 124) RX Frequency Calculation (Frx) RX UHF VCO Frequency Low Channel (Ch 1) Mid Channel (Ch 62) High Channel (Ch 124) RX UHF VCO Freq. Calculation (Fruhf) RX VCO Frequency Demodulation Frequency IF Frequency BER (Bit Error Ratio) 935.2 MHz 947.4 MHz 959.8 MHz 935 + (ARFCN x 0.2) = Frx MHz 1160-1230 MHz 1205.2 MHz 1217.4 MHz 1229.8 MHz Frx + 270 = Fruhf MHz 540 MHz 270 MHz (540/ 2) 270 MHz Type II BER <2.4% at -102dBm Type II BER <0.1% at -15dBm

Receiver (PCN)
RX Frequency Input Low Channel (Ch 1) Mid Channel (Ch 62) High Channel (Ch 124) RX Frequency Calculation (Frx) RX UHF VCO Frequency Low Channel (Ch 1) Mid Channel (Ch 62) High Channel (Ch 124) RX UHF VCO Freq. Calculation (Fruhf) RX VCO Frequency Demodulation Frequency IF Frequency BER (Bit Error Ratio) 1805.2 MHz 1842.6 MHz 1879.8 MHz Ftx + 95 Mhz = Frx MHz 1535-1610 MHz 1535.2MHz 1572.6 MHz 1609.8 MHz Frx - 270 = Fruhf MHz 540 MHz 270 MHz (540/ 2) 270 MHz Type II BER <2.4% at -102dBm Type II BER <0.1% at -15dBm

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Section 3

Circuit Description
Part 1 Part 2 Part 3 Part 4 Part 5 Part 6 Receiver Transmitter Power Amplifier Control 13Mhz Clock Power Supplies and Control Signals (RF) Logic Circuit Descriptions

Part 1 : Receiver
The front end
The RF receive signal (GSM 935Mhz - 960Mhz, PCN 1805Mhz-1880Mhz) is input via the antenna or coaxial connector S400. The coaxial connector has a built in switch, which is used to switch between the antenna and auxiliary RF input. See Fig.1: The Receiver. The Diplexor IC400 and D400/D401 diode packs are used to control the Tx and Rx paths. These diodes are enabled by the control signals:- GSM_PRE_ON (Tx), V_G_LNA (Rx), PCN_PRE_ON (Rx) and V_P_LNA (Tx) respectively. When combined with the diplexor they provide sufficient protection for the receiver LNA's from Tx signals. The receiver front end requires Band Pass Filter's (BPF) FL303 and FL300 to further protect the LNA's from out-of-band signals and Tx signals. For the GSM path the RF signal passes into the BPF FL303, through a matching circuit and into IC300 #29. At this stage the signal passes through a LNA within IC300 to improve the signal to noise characteristics. This LNA is controlled by the enable supply:- V_G_LNA ( derived from IC27-#29) and the output from IC300 #26 is then fed to the input of BPF-FL302. After this the RF signal is then passed to the Dual Balanced BalunL305 for filtering and then fed via balanced outputs to IC300 #13-14 for conversion into an intermediate frequency (IF). In the PCN path the RF signal passes through FL300 into a discrete LNA (TR300), which is controlled by the enable supply:- V_P_LNA (derived from IC27- #30) and then passed through BPF-FL301 to L305. The interstage filters provide further out-of-band signal rejection and further image rejection. The two balanced outputs from L305 are then passed into the PMB2410 IC300 ready for conversion into an intermediate frequency.

Fig.1: The Receiver
V_G_LNA 29 27

RX_ON2
15

PMB2410 (IC300)
To IF Amp

270Mhz
LNA LNA

26

13

17 20 21
FL304

8 9

GSM

FL303

FL302

PCN

FL300

FL301
GSM UHF VCO = 1205 1230Mhz PCN UHF VCO 1535 1610Mhz

LNA L305 RX UHF VCO

Mechanical Switch

Diplexer

V_P_LNA

External RF

GSM RX = 935-960Mhz PCN RX =1805-1880Mhz

The rf signals from L305 form the inputs to the active double-balanced rf mixer of IC300 #13-#14. These are mixed with the UHF VCO (GSM 1205Mhz-1230Mhz, PCN 1535Mhz -1610Mhz) which is input to IC300 #17-18. When these two rf signals are mixed a resultant signal of 270Mhz is produced, this is the intermediate frequency (IF). The signal RX_ON2 (derived from IC27-#28) is the control input which enables the mixer. Outputs from the mixer are differential with the signals phase shifted by + and - 90 degrees. These are then fed into a Dual IF SAW filter (FL304) and then back into IC300 #8-#9. The RX IF of 270Mhz has been selected based on the number of image response and intermodulation products in the IF band, subject also to the constraints that harmonics of the IF do not fall within any RX and TX band and harmonics of the 13Mhz TCXO do not fall in the IF band. The differential IF signal is then fed to the IF amplifier, within IC300 (see figure.3: The IF Amp and demodulator). The gain of the amplifier is controlled by the Superchip IC27, using 3 AGC Control lines: SYGCDT: AGC Programming Data Line (#75) PGCSTR: AGC Programming Enable Line (#72) SYGCCL: AGC Programming Clock Line (#74) These signals are output from IC27 on the logic board. The IF amp can be programmed to a range of 0dB to 70dB in 2dB steps, some 36 levels.

Fig.2:The UHF Synthesiser (RX)

IC201 LMX2331L RF-PLL
PHASE COMPARATOR

11,12,13
PRESCALER

SERLT SERCK SERDA

13MHz CLK

8

DIV 65

EG :1205Mhz (GSM) 5

200Khz

200Khz

3
PHASE DIFFERENCE (CURRENT)
V_VC01/2

PHASE DIFFERENCE (VOLTAGE) 3
LOOP FILTER

NC 1
GND

4
VCC

2

IN UHF VCO OUT

5 GND GND

(IC202/3)

UHF Synthesiser (Rx)
The RX & TX UHF Synthesisers are implemented within IC201- LMX2331L. The RX UHF VCO output is fed to IC201 #5, where it is divided down (via a Prescalar) to a 200khz signal and input to a phase comparator. The phase comparator compares this signal with a 200khz reference signal (which is derived down from the 13Mhz clock). A current phase difference signal is produced, which is in turn converted to a voltage phase difference and filtered at the output on #3, using the loop filter:(R205,R206,R207,C215,C216 & C217). This voltage is then applied to the control input #3 of the UHF VCO (IC202/3). This voltage determines the RX UHF VCO oscillator frequency, i.e.: RX GSM :1205 -1230Mhz / RX PCN:1535 1610Mhz. There are three control inputs for the UHF synthesiser:-

SERDA: Synthesiser Programming Data (#12) SERCK: Synthesiser Programming Clock (#11) SERLT: Synthesiser Programming Enable (#13) :
The SERDA input sets and controls the Pre-scalar inside IC201, this is totally dependant on the chosen traffic channel that is active at the time.

Fig.3:The IF AMP and Demodulator
AGC Control :-PGSTR

PMB2410 (IC300)

11,12,13 46 45 40 39

SYGCCL SYGCDT

First Mixer

270Mhz
RINO

540MHz 1st IF 270Mhz
20-21 8-9 32-35

Div2
36

RINO RIPO RQNO RQPO
RX_ON2 PUPLO2
GSM_TX

Div2/3
31 23-24

Varactor Network D303 (A,B)

FL304 LOOP FILTER

TO W2013 (IC100) (TX IF Modulator)

From (IC201#18) IF PLL (See Fig.4)

Rx I&Q Demodulator
The modulated IF signal of 270Mhz is demodulated by mixing it with another 270Mhz signal, which is derived from an 540Mhz oscillator located inside IC300. The 540Mhz is reduced by a pre-selectable divider, which can be set by the control signal GSM_TX (from IC27#23). The output from the 540Mhz oscillator is divided down by a factor of 2 or 3 to produce either a 180 or 270Mhz signal, depending on whether the mobile is in TX or RX modes . It is this signal which is mixed with that from the IF amplifier to produce the baseband I and Q signals. The I and Q signals are then buffered and fed differentially to the Superchip (IC27) for filtering and digitising. The signal RX_ON2 (from IC27#28) enables both the demodulator and internal buffers. The signal PUPLO2 which is supplied from IC27 #26, enables the 540Mhz internal oscillator.

Fig.4:The IF Synthesiser (RX)
To RX Demodulator

IC201 LMX2331L IF-PLL
PHASE COMPARATOR

IC300
23-24 16 2

13MHz 8 CLK

DIV 13

1Mhz

1Mhz

DIV 180

180Mhz

180Mhz

DIV2

DIV3

PHASE DIFFERENCE (CURRENT)

18
PHASE DIFFERENCE (VOLTAGE)

GSM_TX 32 33
D303B

540Mhz

GSM_TX ="1"= 180Mhz GSM_TX ="0"= 270Mhz

LOOP FILTER

D303A

34-35

31 PUPLO2

GND

The RX IF Synthesiser
The IF synthesiser (IF- PLL) is contained within IC201 - LMX2331L. It is used to tune the 540Mhz TX/RX IF oscillator inside IC300. The 540Mhz oscillator output is first divided down by a factor of 3 within IC300. This is achieved by an internal pre-selectable divider, which is set by the signal GSM_TX from IC27 #23. In receive mode the signal is high, which sets the divider to 3 so therefore the 540Mhz is reduced to 180 Mhz, which is output on pins #23 and #24. This signal is then fed to #16 of IC201, where it is then divided down by a factor of 180 to give a 1Mhz signal. A 1Mhz reference signal derived from the 13Mhz clock is input to the phase comparator and compared with the 1Mhz signal derived from the 270Mhz signal. The phase comparator then derives a current phase difference of the two signals and outputs it to the loop filter on pin #18 of the device. The loop filter (C218, C219, C220,R202,R204 & L205) then uses the current phase difference to produce a voltage phase difference and outputs this to the Varactor network (D303 A/B). The Varactor network and circuit at #33-35 form part of the 540Mhz oscillator circuit, which is tuned by the phase voltage applied to the network. The control signal: PUPLO2 from IC27 #26 is used to switch the 540Mhz signal ON or OFF.

Part 2 : Transmitter Fig.5:TRX -The TX IF Modulator W2013 (IC100)
PMB2410 (IC300)

Loop Filter

540Mhz Osc
TIF Filter 270MHz
Div2/3

32

IF-PLL

GSM_TX

3V_G_TX

To IC101
TR106 GND 3V_P_TX

9 180 - 270Mhz

2 3 W2013

5 4 6 7

To IC102
TIF Filter 180MHz TR107 GND

TIPI TINI TQPI TQNI
(1,16,20)

2v85_rf3

The TX IF Modulator
The TX I & Q signals from IC27 #86-89 are fed to #4-7 of the W2013 TX modulator (IC100), where they are then modulated onto either a TX IF of 270Mhz (for GSM- TX) or 180Mhz (for PCN-TX) by the quadrature mixer inside IC100. The signal TX LO IF (180-270Mhz) is input on #9 of IC100 (W2013) from (IC300) #24. This signal is produced by the internal 540Mhz oscillator within IC300, which has been divided down by a factor of 2 for GSM-TX or 3 for PCN-TX. This division factor is set by the control signal GSM_TX from IC27 #23. The TX modulated IF signal of 270Mhz is output on #2 of IC100 for GSM or a modulated IF signal of 180Mhz is output on #3 of IC100 for PCN. Pre-amp transistors TR106 and TR107 amplify the signal and then pass it through to BPF's: FL100 or FL101 for filtering and then after to the RF Mixer's (IC101 or IC102).

Fig.5: The IF Synthesiser (TX)

To W2013

IC201 LMX2331L IF-PLL
PHASE COMPARATOR

IC300
180 or 270Mhz DIV2/3

13MHz 8 CLK

DIV 13

1Mhz

1Mhz

DIV 180 or 270

180 or 270Mhz 16

23-24
GSM_TX

PHASE DIFFERENCE (CURRENT)

18
PHASE DIFFERENCE (VOLTAGE)

32 33
D303B

540Mhz

LOOP FILTER

D303A

GND

34 35
PUPLO2
31

The TX IF Synthesiser
TX IF Synthesiser(IF-PLL) is the same PLL as used in the RX process and is located within the LMX2331L (IC201). In this case the synthesiser is used to tune the 540Mhz TX IF oscillator inside IC300. The 540Mhz signal from IC300 is divided by a factor of 2 (for GSM) to produce a 270Mhz signal or divided by 3 (for PCN) to produce a 180Mhz signal. This signal is then fed to #16 (IC201) and #9 (IC100) the TX modulator. At IC201, it is divided down further by a factor of 180 or 270, dependant on which tx band the mobile is set to. This produces a 1Mhz signal which is then input to a phase comparator where it is compared with a 1Mhz signal derived from the 13Mhz clock to produce a current phase difference signal. This signal is output from IC201 on #18 to the loop filter (C218, C219, R202, C228, R283, R204 & L205), which aswell as filtering the signal also converts it to a phase difference voltage. The phase difference voltage is then applied to the varactor network (D303 A/B). The varactor network forms part of the 540Mhz oscillator circuit inside IC300 and is tuned by the applied voltage.

Fig.6: The UHF Mixer / Amplifier (IC101 / IC102)

GSM VCO = (1160-1230MHz) PCN VCO = (1530-1610MHz)
(IC203)VCO 2 V_VCO1 4 (IC202)VCO 2 V_VCO2 4 9 To IC103 15
BPF

TCXO

1 3 Loop Filter 3 8

RF-PLL

5

3

2 16GSM_PRE_ON

6

11 270Mhz - W2013 PMB2333 9 11 180Mhz - W2013 PMB2333

To FL103

15

BPF

2 163V_P_TX

6

The UHF Mixer Amplifier
The PM2333 IC's (IC101/102) converts the IF modulated signal to RF and incorporates an active double-balanced mixer. The modulated TX IF signal GSM(270Mhz) or PCN(180Mhz) is mixed onto the GSM(890Mhz-915Mhz) or PCN(1710Mhz-1785Mhz) TX RF frequency. This is achieved by mixing the TX IF signal with the TX UHF VCO output from IC202 for GSM and IC203 for PCN. Hence:GSM TX = UHF VCO 270 ie, (1160 270 = 890Mhz) PCN TX = UHF VCO +180 ie, (1530 + 180 = 1710 Mhz) The modulated RF signal is then output on #6 to a BPF and then re-enters the PMB2333 (IC101/102) at #2. The RF modulated signal is then amplified by the pre-driver within the PMB333 IC .GSM_PRE_ON and 3V_P_TX are control lines for the pre-driver amplifier. The RF signal is then output on #15 of the PMB2333 and passed through another stage of filtering (BPF:FL103) and pre-amplified via IC103/104 before the power amplifier stage (See Fig.8: The P.A. Circuit and its Control).

Fig.7: The UHF Synthesiser (TX)

IC201 LMX2331L RF-PLL
PHASE COMPARATOR

11,12,13
PRESCALER

SERLT SERDA SERCK

13MHz CLK

8

DIV 65

200Khz

200Khz

EG:1160Mhz (GSM)

5

3
PHASE DIFFERENCE (CURRENT)
V_VC01/2

GND

VCC

PHASE DIFFERENCE (VOLTAGE) 3
LOOP FILTER

NC 1

4 2

IN UHF VCO OUT

5 GND (IC201/2) GND

The TX UHF Synthesiser
The TX UHF Synthesiser (RF-PLL) is the same as the PLL used in the RX and is contained in the LMX2331L (IC201). In TX mode the TX UHF VCO output is fed to #5 (IC201) and then pre-scaled down to 200khz. The phase comparator within IC201 compares this signal with a 200khz signal derived from the 13Mhz clock and outputs a current phase difference at #3. A loop filter then converts this signal into a voltage phase difference and feeds it to #3 (IC201) or (IC202). The voltage phase difference determines the UHF VCO frequency i.e. GSM TX 1160Mhz -1185Mhz, PCN TX 1530Mhz - 1610Mhz . Three control inputs are used in the UHF Synthesiser SERDA, SERCK, SERLT. It is the SERDA control input which initially sets the TX VCO frequency. This is totally dependent on the chosen traffic channel the logic circuit has selected at the time.

Part 3 : The P.A. Circuit and its Control Fig.8: The Power Amp Circuit
To Antenna

PCN = (1710-1785MHz) GSM = (890-915MHz)
(FL106) (IC106) PA
(IC105) GSM_PRE_ON BPF
V_ERROR TXP_MOD

(IC103)

mech switch

Diplexor

From IC101

(IC107) PA
PCN_PRE_ON

(FL105)

(FL103)

From IC102
BPF (IC104) (IC108)
V_ERROR TXP_MOD

The P.A Circuit and its control
The power amplifier control circuit ensures that the RF signal is regulated to the required limits of operation. The TX RF signal is input on #1(IC106) or (IC107) and the power amplifier outputs the signal at #4. IC105 and IC108 are op-amps, which output a control signal to the P.A. Power control is carried out by measuring the current drawn by the P.A (see Fig.9: P.A Circuit Control). The current drawn by the P.A. is directly proportional to the output power and is measured as a voltage drop across a known resistance path or "Fixed Control Loop Stripline". This consists of a 47mOhm resistor (R144) for GSM or two resistors in series, a 47mOhm (R144) and 27mOhm (R136) for PCN. The voltage drop (V_ERROR) is then integrated by the operational amplifier (IC108) to give an error voltage, which regulates the TXP signal. The TXP input signal to the power control circuit is generated by the IC27 #90. TXP provides a limit for the frequency spectrum caused by burst modulation.

The signals 3V_P_TX and 3V_G_TX are controls supplies used to enable the two power control op-amps IC105 and IC108. The output from the P.A follows the TX path, which uses the control supplies:GSM_PRE_ON or PCN_PRE_ON to enable the TX switching diodes D400/D401. The RF signal then passes through the diplexor and onto the antenna. The diplexor is tuned to the GSM or PCN duplex spacing so enabling selectivity between GSM and PCN Rx or Tx.

Fig. 9. The PA Control Circuit

V_CONT 4

3 TR110 2 1 GND TR109 1

V_CONT

GND VBAT

6 VCC

Fixed Control Loop Stripline

IC109 4 3

D101 V_ERROR V_CONT

VBATR144 VBAT_PCN

+

R136

V_CONT

TR108 GND

GND

2

Part 4 : 13Mhz Clock
To IC201-#8 (IF/RF PLL) 2V8_RF1

2V8_RF1

GND 4 GND

13Mhz To Logic Board
1 TR204

X200
GND GND GND 6 5 2 GND

GND

GND

GND

The 13Mhz-clock (X200) consists of a TCXO ( Temperature Compensated Crystal Oscillator ) which oscillates at a frequency of 13Mhz. It is used within the LMX2331A Synthesisers on the TRX board and also in the Superchip and Nell on the logic board. TR204 and TR205 buffer the output to the logic board.

Part 5: Power Supplies and Control signals (RF Board)
5.1: MicroMoe IC204 Power Supply IC
The RF section has its own dedicated power supply device called: MicroMoe. This is a smaller version of the ASIC MiniMoe, which is located on the logic board. MicroMoe performs all power supply requirements of the RF circuitry, except for a dedicated 5-volt supply (5VRF) for the UHF VCO's which is supplied from MiniMoe. The device consists of three voltage regulators that supply the power rails for the RF circuits and is supplied from VBAT. See: Fig.6.C: Power Supplies MiniMoe (IC19) & MicroMoe (IC204). MicroMoe provides the following outputs:2V8_RF1 (Regulator 3): 2.85V RF supply for the 13Mhz clock and LMX2331 synthesiser. (Regulator 2): 2.85V RF supply which supplies V_G_LNA and V_P_LNA. (Regulator 1): 2.85V RF supply used in the transmitter circuitry.

2V8_RF2

2V8_RF3

There are two enable signals which control the regulator's:TCXO_ON Enables supplies: 2V8_RF1 and 2V8_RF2. Signal derived from NELL #P2. Enables supply: 2V8_RF3, signal derived from IC27 #17.

TX_ON

5.2: Control signals and additional power supplies
The RF board has the following additional voltage supplies and control signals. 5V_RF Regulated 5V supply for the VCO circuits and to supply V_CONT. 5V derived from MiniMoe on logic board. Switched version of the 5V_RF. This is supplied to the power control circuitry and is switched on a frame before the TX burst. Switched version of 2V8_RF2 to power the GSM LNA and the RX switching diode: D400. Switched version of 2V8_RF2 to power the PCN LNA and RX switching diode: D401.

V_CONT

V_G_LNA

V_P_LNA

GSM_TX

Control signal from IC27 #23 which switches the 2V8_RF3 supply to give 3V_G_TX. It also sets the internal frequency divider inside IC300. Control signal from the superchip, which switches the 2V8_RF3 supply to give 3V_P_TX. Switched version of 2V8_RF3 to power the PMB2333 IC in the GSM TX path. Switched version of 2V8_RF3 to power the PMB2333 IC in the PCN TX path. Switched version of 2V8_RF3 used to turn on the preamplifier MMIC (µPC2771) in the GSM TX path and the TX switching diode: D400 . Switched version of 2V8_RF3 used to turn on the preamplifier MMIC (µPC2771) in the PCN TX path and the TX switching diode: D401. Control signal from the IC27 #29 which switches V_G_LNA. Control signal for the 1st mixer, RX demodulator and internal buffers. Control signal from IC27 #19 which switches 2.85V through to PCN_PRE_ON. Control signal from IC27 #18 which switches 2.85V through to GSM_PRE_ON. Control signal from IC27 #22 which switches 2.85V through to GSM/PCN_PRE_ON.

PCN_TX

3V_G_TX

3V_P_TX

GSM_PRE_ON

PCN_PRE_ON

GSM_LNA RX_ON2

PCN_ON

GSM_ON

PRE_ON

Part 6: Logic Circuit Description
This section describes the architecture and hardware functionality of the logic circuit. The logic circuit performs the following functions: · · · · · · · · · · · · · · Channel coding/ decoding Speech coding / decoding Data encryption Layer 1,2 and 3 software tasks I/O System interface SIM interface and management Audio and tone control Vibrator control Power supply and battery management RF power control Synchronisation Real time clock Key-Pad control and scanning LCD control and driver

The logic and RF circuits are primarily controlled and administered by two main devices, these being:· "Superchip"- CSP and DSP Combined (IC27) The "Superchip" combines the functions of both the CSP and DSP in a single package. The device performs channel and speech coder/decoder tasks, equalisation, encryption, frame timing, A/D conversion, RF power control and audio interfacing, including tone generation. · Nell - (IC8) Nell incorporates the main CPU for the mobile and controls the functions; Layer 1,2 and 3 software, the SIM, system interfaces, real time clock, buzzer, vibrator, battery management, Key-Pad scanning and LCD control. Nell also controls the integrated power supply devices:- "MiniMoe" and "MicroMoe" . The Logic circuit is divided into six main functional areas: 1) 2) 3) 4) 5) 6) Superchip (CSP and DSP combined) Nell and CPU Memory Battery Interface and Power Supply Keypad, Display and SIM Audio and Miscellaneous Interfaces System Connector - P5

6.1 "Superchip" (CSP and DSP combined) - (IC27)
The superchip is the interface between the RF circuitry, the audio circuits and the digital domain. It also carries out layer 1 signal processing, this includes data coding/decoding, data interleaving/de-interleaving, error detection/correction and provides burst generation data. Unlike previous versions of DSP package which used external static random access memory (SRAM) devices for data storage of signal processing operations. The superchip incorporates its own internal 8K * 16 RAM capability to perform these functions. The device has the following control functions and connections:· Transmit power control O/P: The signal TXP (#90) controls the ramp shape from the RF Power amplifier. Transmit I and Q outputs O/P: TIPI,TINI,TQPI and TQNI (#86-89) Digital Audio Interface O/P: DAICK, DAIRN, DAIDI and DAIDO (#6-9) Control outputs for the RF Circuit O/P: VCO_ON (#16) : Power enable for VCO TX_ON (#17) : Power enable for transmit circuitry GSM_ON (#18): Power enable for GSM circuitry PCN_ON (#19) : Power enable for PCN circuitry PRE_ON (#22) : Power enable for RF pre amplifier GSM_TX (#23) : Power enable for GSM TX path PCN_TX (#24) : Power enable for PCN TX path PUPLO2 (#26) : Power enable for 2nd local Osc RX_ON1 (#27) : Power enable for RX circuitry RX_ON2 (#28) : Power enable for RX circuitry GSM_LNA (#29) : Power enable for GSM RX path PCN_LNA (#30) : Power enable for PCN RX path RF Synthesiser controls - (IC201) O/P: SERLT (#12) : Synthesiser data latch enable SERCK (#13) : Synthesiser data clock SERDA (#14) : Synthesiser serial data 13MHz system clock I/P:

·

·

·

·

·

13MHz (#59)

·

Receive I and Q inputs I/O:

RQNO, RQPO, RINO and RIPO (#77-80)

·

Audio outputs for hands free operation O/P: RXAF- and RXAF+ (#95-96) Audio output to earpiece O/P: AOUTN and AOUTP (#93-94) Audio inputs from microphone I/P: MICOUT and MICIN (#4-5) Audio inputs for hands free operation I/P: TXAF- and TXAF+ (#98-99) Tone Generation GMSK modulation, transmit frequency correction Digital to analogue conversion of the transmit I and Q signals A/D and D/A conversion / gain control for audio inputs/outputs Serial Interface to NELL This is a direct serial I/O interface to the NELL device used to pass data destined for the PCMCIA interface: I/O: ICK (#67), OCK (#70) OLD (#71), ILD (#66), OBE (#63), DSP RXD (#64) and DSP TXD (#65)

·

·

·

· · · · ·

·

Parallel Host Interface (PHIF) to CPU in NELL The DSP communicates with the CPU in NELL via a dedicated interface called the (PHIF) Parallel Host Interface: I/O: PB0-PB7 (#32-40) = Data I/O lines to CPU POBE (#47), OE (#43) and WE (#41) = Interface control

·

Receiver IF Gain Control The DSP sets the receiver IF gain to IC300 via control signals: O/P: PGCSTR (#72) - Receiver gain control SYGCCL (#74) - Receiver gain control clock SYGCDT (#75) - Receiver gain control data

·

Interrupt generation to NELL I/O: This bit I/O port performs interrupt control of NELL: EXTINT(#73) Superchip interrupt and reset inputs The superchip has the following interrupt and reset inputs: I/P: DSP INTO (#48) - DSP Interrupt 0 DSPRSTB (#50) - DSP Reset bar

·

·

JTAG test interface The JTAG interface provides extensive test and diagnostic functions to be utilised in the repair process. This is controlled by:I/O: TCK (#54) - JTAG test clock TMS (#55) - JTAG test mode select TDI (#57) - JTAG test data input TDO (#56) - JTAG test data output

·

Supply and ground connections +3VSC = (#10,21,36,49,62 & 92) +3VAUDIO = (#2,85,58) GND = (#11,20,31,42,52,69,76,91 & 61) AGND1 = (#1)

A functional block diagram of the Superchip can be seen in Figure 10a.

6.2 NELL
The NELL device is an in-house designed ASIC (Applications Specific A Integrated Circuit) which has been developed to replace the existing Albert and CPU devices currently used in G9 and G9D. The NELL performs the following functions:CPU CPU Interface Interrupt Controller Baseband Power Control Keypad Control Display Interface EEPROM Interface SIM Interface Buzzer Control UART control/interface: (Universal Asynchronous Receiver Transmitter) PCMCIA Data Interface: (Personal Computer Memory Card International Association)

· · · · · · · · · · · ·

· · · · ·

I/O System Connector Interface - P5 Analogue Signal Measurement Charge Control Real Time Clock CPU Timers The NELL is divided into two main function blocks:-

1. 2.

The Isolated Logic Block (ILB) The CPU core, peripherals and interfaces.

6.2.1 The ILB Block
The ILB's main functions are:· To control and monitor the application of power to various key sections of the mobile, which creates the various power saving conditions. A real time clock (RTC) with programmable alarm Event detection/monitoring of the following: 1. A key-board entry 2. The power key being pressed 3. Charger voltage being applied to the mobile 4. The external sense line being activated 5. RTC alarm 6. Data being received from either the PCMCIA card or the hands free kit via the system connector. 7. Keyboard scanning and decoding 8. Isolation, reset and power control of the SIM interface 9. Control through a external device register that allows the display, CPU RAM and Flash ROM CS lines to be activated.

· ·

A functional block diagram of NELL can be seen in Figure 10b

6.2.2 The CPU, Peripherals and Interface
The remainder of NELL performs the following functions:· · · · · · CPU and ARM interface (Advanced Risk Machine) Address decoding and data multiplexing Timer and watch-dog timer generation Serial interface to and from the SIM UART administration for the system connector serial port Pulse width modulator used to drive the buzzer;

·

A 5 channel 8 bit A/D converter used for battery management and to measure the pcb temperature

6.3

CPU Memory

Flash PROM - (ICI 5) An 8Mbit programmable ROM which is capable of being written to while still in circuit. Contains all the main command software for the HHP Static Random Access Memory (SRAM) - (IC9) A 16 bit (64k by 16) temporary memory device which is used by NELL for CPU program execution. EEPROM - (IC10) A 4Kbyte electrically erasable and programmable ROM, which communicates via the EECLK / EEDAT (#5-6) lines to NELL. It contains all the user memories and calibration data. The location of these devices relative to NELL can be seen in Figure 10b.

6.4 Battery Interface and Power Supply
6.4.1 Battery Monitors and PCB Temperature Interface
The HHP can monitor the state of the battery through the battery interface connector P8. This can be done during both normal and charging operations. The battery provides a number of interface connections that enable the HHP to determine the battery type, its capacity, temperature and whether it is possible to re-charge the cell(s). The thermister (R124) which is attached to the logic board pcb is used to produce an analogue reading of the board's own surface temperature. The P8 connector provides a connection between the battery power contacts VBAT/GND to the RF board and BATTEMPMON/BATID battery monitoring circuits to the battery. IC30 #2 provides the bias/reference supply: VREF for these analogue monitors and is also fed to IC29. Battery voltage monitoring (BATVMON) is performed by the circuit:IC30/IC29, with the output of the regulator IC30 #2 feeding the comparator IC29 #3. IC29 uses this input as a stabilised voltage reference level, which it compares to VBAT to produce the analogue output BATVMON. This output is then supplied to NELL #M9 for A/D conversion. BATVMON enables the HHP to measure the battery voltage and hence determine how much charge remains in the cells. The remainder of the analogue inputs from these circuits are also fed to NELL for A/D conversion.

These monitor's being :BATTEMPMON (Battery Temperature Monitor) - NELL (#L9) BATID (Battery Identification) - NELL (#N9) The battery pack includes an internal thermister, which is used to produce the analogue signal BATTEMPMON. This enables the HHP and external charger to determine the battery temperature, which is used to protect the battery from overheating while charging.

Figure 10a. CSP and DSP Functional block diagram
G4H Functional Block Diagram
(
cipher_block_int 2v85_ln

bit manipulation unit dsp1600 core
ds p_ clk

csp_dsp_reset nell_to_dsp_int (INT0)

"CSP1089 core" "CSP and DSP cores" Combined in Superchip 1 frequency correction
tx_I

A5.1/A5.2

dac I&Q gen gmsk modulator 160-bit tx buffer
cs p_ to _d sp _in t (IN T1

tx_Q

dac

error correction co-processor

timer

not connected

overload detection prog gain amp prog gain amp 11-bit adc 32 word rx buffer 11-bit adc

rx_I

8 k x 16-bit of dual port ram

sio_input_clk sio_output_clk sio_output_load

sio_input_load

rx_Q

tx_pwr_cntl

dac

power level & burst ramp-up cntl

48k x 16 rom (FLASH available for development)
end_of_tx_int ext_overflow_int int_overflow_int

sio_output_buffer_empty sio_data_tx sio_data_rx

bit input/

1/4-bit counter frame counter

rx_buffer_int timeout_int

interrupt control and status

div M

div N

dsp_to_nell_int (EXTINT) if_digital_gain_cntl 3

prog pll

audio_in_int

Superchip1

we oe dsp_cs address bus (2:3)

vco_on tx_on Note:PCN only signals indicated by dashed lines: gsm_on pcn_on pre_on gsm_tx pcn_tx pupl02 rxon1 rxon2 gsm_lna pcn_lna

octl_0 octl_2

audio frequency correction & gain control control lines

aux_audio

data bus (0:7)

octl_3 octl_4 octl_6 octl_7 octl_8 octl_9 octl_10 octl_11 octl_12 octl_13

16-bit reg

dac

ear_audio_out

"DSP1628 core"
13_mhz_clk

digital audio interface double buff reg

dai_do_di_rn_ck 2v85_anlg

synth_ser_chl_data

3

synthesizer serial control

adc

prog gain amp vreg

aux_audio_in

audio

mic_in mic_drv

Figure 10b. NELL and Memory
G4H Functional Block Diagram
2v85_main 32_khz_clk

isolated logic block
32_khz_clk

nell
not connected

psu sync generator

timer & wdt
13_mhz_clk

real time clock rtc alarm
ilb_caltrig

cal trig counter
keycol(0:3) keyrow(0:5)

NELL and Memory
adc_ref_en
Note: these i/o ports revert inputs when NELL is to

13_mhz_clk

32 kHz calibration cntr
start/stop

ref

buzzer_en

pulse width modulator

13_mhz_clk

6 NV storage registers
32_khz_clk

keypad interface

pwr_key reserved for mech_ip charging_volt_det

adc_ref
ref

timer 1
13_mhz_clk

rf_5v_en battery_thermistor_en ext_charger_en backlight_en red_charger_led_drv green_call_led_drv headset_jack_insert_det trx_pa_bias

battery_voltage_monitor battery_temp_monitor battery_id pcb_temp_mon

converter

sleep duration timers
sleep time + sleep enable/disable

5 x 8 bit ad c 8 bit dac (DAC1)
cpu_irqs

timer 2

isolation logic timer
pll time

watch dog timer i/o interface
reserved for future lithium charger

13m clock start-up timer
clock time

asynch event detect

ext_sense_in

reserved for future VCXO adjustment vibrator_en 2v85_main pcmcia_txd nell_to_dsp_int (INT0) uart_txd not used

8 bit dac (DAC2) uart reg
cpu_irqs

nell_ reset

reset duration timer
reset time

uart_rxd pcmcia_rxd

ais time

ais trigger timer interrupt status and control
cpu_wake_up_irq hard_pwr_en

isolation
cpu_irqs ee_data ee_clk

2k x 8 eeprom

eeprom interface

sio_input_clk sio_output_clk sio_output_load sio_input_load sio_output_buffer_empty sio_data_tx sio_data_rx other_cpu_irqs soft_pwr_en ilb_irqs

data services support

size of the eeprom presently under study

power control module

OR

rg3_pwr_en

2v85_ilb

dsp_to_nell_int(EXTINT)

nell internal bus and data mux external interface
uart_reset eeprom_reset sim_reset wdt_reset 2v85_main 2v85_ilb uart_clks

we oe address bus & data bus

device reset control registers device clock control registers

cpu interface arm7tdmi core
sim_irq

enable external devices register
ilb_sim_data sim_ilb_data

ilb ports control

csp_dsp_reset lcd_pwr_drv sim_3v_5v_sel lcd_cs sim_pwr_en sim_data sim_clk sim_rst ilb_reset

512k x 16 flash prom
Additonal storage space required for Chinese variants with MO/MT SMS dsp_cs

64k x 16 ram

pwm_clks sim_clks wdt_clks

sim interface

32.768 kHz osc and clock division circuitry

sim maintenance interface

rom_cs

ram_cs

6.4.2 Power Supply
MiniMoe - (IC19) MiniMoe is a dedicated power supply, which provides most of the power requirements for the logic circuit. The RF section has its own dedicated power supply device MicroMoe which is separate to MiniMoe, except for a dedicated 5 volt supply (5VRF) for the VCO's. MiniMoe consists of six voltage regulators that supply the power rails for the logic circuit. MiniMoe provides the following functions:· · · · · · · · Generation of a reset pulse to ILB - when battery voltage is at cut-off threshold (2.85V- 3.1V ) or UVLO2- (Under Volts Lock Off 2). A function that disables the regulators 2, 3, 5, 6 and 7 when the battery voltage is less than UVLO2. Back-up battery management: (BUB - #12) ILB power supply: (+3VILB - #31) Logic supply rail: (+3VNELL - #3) SIM supply, configurable between 3 and 5 volt operation: (SIMVCC - #6) Dedicated 5 volt supply for the transceiver VCO: (5VRF - #10) A low noise regulator for the handset audio and CSP analogue sections: (+3VSC -#4) and (+3VAUDIO - #2)

With the exception of regulator 1, each of these regulators can be controlled by individual enable signals. These are configured as shown in Figure 6c and table1. Regulator outputs. Regulator
Regulator 1 +3VOILB Regulator 2 +3VNELL Regulator 3 +3VSC Regulator 5 SIMVCC Regulator 6 +5VRF Regulator 7 +3VAUDIO

Pin
31 3 4 6 10 2

Voltage
2.85 ±0.15V 2.85 ±0.15V 2.85 ±0.15V 3.0 ±0.15V 4.75 ±0.25V 5.0V± 0.25V 2.85 ±0.15V

Powers
ILB part of NELL CPU, RAM, LCD NELL, Flash ROM, EEPROM & 13MHz Oscillator SC1 digital circuitry SIM VCO CSP Audio circuitry

Enable Signal/PIN
Supplied from battery HARD_PWR(28) +RG3VPWR(21) SIMPWR(20) SIMVSEL(18) 5VRFON(19) +RG3VPWR (21)

Table1. - MiniMoe

6.4.3 Reset :- ILBRST / UVLO2
The MiniMoe generates a reset pulse (active low) to the NELL (#L4 -ILBRST) when it detects that the battery voltage is below the UVLO2 threshold of (2.85V- 3.1V). The device also disables internal regulators R2, R3, R5, R6, and R7, this then holds the ILB in reset mode, allowing only the real time clock to run. When the battery is recharged or replaced the ILB reset pulse is reversed and the regulator's re-activated. There is another under volt lock off point (UVLO1) which is activated when the battery voltage reaches the range of between (2.6V-2.85V). This then disables regulator 1 (ILB/RTC regulator) and via the output pin (BUB-#12) drives the external FET TR25, which switches ILB/RTC supply over to the back-up battery BATT1.

6.4.4 Power Control
The ILB section of NELL performs the power control management of the HHP. It is this power control management that enables the HHP to execute its power saving functions. The ILB runs the 32kHz clock and controls the transition of the HHP between various power modes. The ILB controls the power mode(s) of the HHP via two signals: 1. +RG3VPWR This connects to MiniMoe (IC19) #21 (EN3). A high on this pin switches regulator 3 (+3VSC) on thus powering IC27and the SRAM (IC9). A low switches it off. 2. HARD_PWR This connects to MiniMoe #28 (EN2). A high on this pin switches regulator 2 (+3VNELL) on thus powering the NELL (IC8), the flash ROM (IC15), and the EEPROM (IC10). A low switches it off and powers down NELL etc. 3. SIMPWR (NELL#L5) This output from NELL connects to MiniMoe (IC19) #20. A logic high switches The output SIMVCC (#1) to on, and supplies power to the SIM connector(#6). 4. SIMVSEL (SIM Voltage Select) (NELL#L3) This output from NELL connects to MiniMoe #18. A logic high on this pin selects the SIMVCC supply voltage to either 3v or 5v. 5. +5VRFON This output from NELL connects to MiniMoe #19. A logic high on this pin switches the output +5VRF on and is then fed to the RF board.

There are four main power states that the HHP can be set into. These are :1. ILB Reset When the battery is disconnected (or very low), the ILB is held in a reset state via the generation of an ILB reset pulse from MinMoe (UVLO2OUT-#22). Only the real time clock remains in operation. The rest of the HHP, including the NELL and 3VSC supply, is powered off. Hence the ILB will not respond to any asynchronous event such as key-presses etc. In this mode the ILB may be powered from the back-up battery if the main battery voltage is too low e.g. (13 Mhz clock and driver RF CSP DSP NELL (ILB) NELL (CPU) EEPROM CPU FLASH ROM CPU SRAM SIM LCD DISPLAY LED's Back-Light Back-up Battery OFF OFF OFF OFF ON OFF OFF OFF OFF OFF OFF OFF OFF Powering ILB

Table 2 - DB2000 Power States Hard Off Soft Off
OFF OFF OFF OFF ON OFF OFF OFF OFF OFF OFF OFF OFF Kept charged from the battery via Reg 1. OFF OFF In Idle state In S/W stop mode. ON OFF OFF OFF ON ON ON OFF OFF Kept charged from the battery via Reg 1.

On
ON RF sections powered on as needed. ON ON ON ON ON ON ON ON ON ON ON Kept charged from the battery via Reg 1.

MiniMoe Functional Diagram

UVLO 1 Detector (2.6 volts)

BUB TR25

Battery and Power Supply
disable

backup

+3VILB
lcd_pwer_drv

2.85v Regulator 1

MiniMOE
HARD_PWR RG3VPWR
disable

ILB

lcd

cpu ram

UVLO 2 Detector (3 volts)

(not used)

+3VNELL
cpu flash prom

2.85v Regulator 2 eeprom backlight nell
2v85_ref

ILBRST SIMVSEL SIMPWR m_pwr_en
v_bat

Power on Reset

disable

2.85v Regulator 3 sc1

+3VSC
buzzer driver cct

disable

SIMVCC

2.85v or 4.75v Regulator 5

LiION Cells

sim

disable

battery_id
protection

Charge Pump

adc_ref

battery_thermistor_en

thermistor_io
disable

+5vRF
5.0v Regulator 6 5v RF (VCO)
disable These +3VAUDIO physicallyparts arewith the located transceiver

battery_temp_monitor

voltage divider network 2.85v Regulator 7

+

5VRFON VBAT at

audio h/w 2.85v Regulator 4a

sc1 audio

2v85_rf_a

MicroMOE
2.85v Regulator 4b

13 MHz TCXO + Drivers

rf_A
2v85_rf_b

2v85_rf_c

rf_B 2.85v Regulator 4c

TX_ON

rf_C

Figure 10c. Power Supplies MiniMoe (IC19) & MicroMoe (IC204)

6.4.5 Power Up
Power up of the mobile can be initiated by one of three ways:1. Power Key Press The Power key button is connected to the input KEY1 of NELL #H2. The input (KEY1) has an internal pull-up resistor, which is grounded, when the power key (SW20) is pressed. This then causes a failing edge on the input, which generates an interrupt to ILB notifying it that the power key has been pressed. 2. Power up through the I/O connector - SNSINT When an external accessory is connected to the HHP an interrupt is generated on the SNSINT input (#7) of the system I/O connector (P5). This interrupt is then received by ILB (#P3) of NELL (EXTSENSE). 3. Alarm Wake up If the alarm wake up has been set by the user and it activates, then an interrupt is generated internal to NELL and the HHP initiates its power up routine. When an interrupt is detected by NELL from one of the aforementioned inputs then the ILB circuit will commence its power up routine. The ILB will firstly output a high voltage on HARD_PWR (#P2), this is then fed to the input EN2 (#28) on MiniMoe which in-turn activates regulator 2 internally and this then powers up the +3VNELL line. The NELL, flash PROM, and EEPROM will now power up. The HARD_PWR signal also activates the power supply "MicrMoe" (IC204) which supplies the outputs:2V8_RF1, 2V8_RF2 and 2V8_RF3 to sections of the RF circuitry. The ILB then sets the RG3VPWR (NELL- #H1) line high, which enables regulator's 3 and 7 internally within MinMoe (EN3 - #21). Both the +3VSC and +3VAUDIO lines are now activated and so power up the CSP, DSP, SRAM (IC9) and Audio. Once the main control devices are active the ILB enables +5VRFON (#19) and SIMPWR (#20) to power up the 5VRF and SIMVCC lines.

6.4.6 Power Down
When the power key is pressed the interrupt is detected by KEY1 ( #H1) on NELL, which outputs a low voltage onto the HARD_PWR, RG3VPWRN, 5VORFON and SIMPWR control lines. This in-turn switches off the regulator's 2, 3, 5, 6, 7, and MicroMoe (IC204), thus powering down the HHP. The power down sequence is done in stages, so as to ensure that all data and control operations are accomplished in order and to prevent data corruption.

6.5

Keypad, Display and SIM Interface

6.5.1 Keypad and Display
The keypad and display forms part of the logic board and consists of the following: · · · · Key switches (4 [N1]x 5 Matrix) LCD module (72 x 32 Graphical based display module) Back-Light illumination (10 green LED's, six for keys and four for the LCD) Indicator LED (Red/Green bicolour LED, to indicate charging and call status)

All control and I/O interface to the keypad and display is performed by the Nell device. The Key switches, LCD module, Backlights, Call / charger LED's and SIM interface are shown in Figure 10d.

6.5.2 Keypad switches and Scanning
The key switches are metal domes which make contact between two concentric pads on the top layer of the PCB when pressed. There are 18 switches (SW1-18), connected in a matrix of 5 rows by four columns, as shown in fig 10d, except for the power switch (SW20) which is connected independently. Two additional momentary action push-button switches are mounted on a flexible PCB on the side of the handset and connected to the row/column matrix by three gold pads (SW21). These perform the volume "UP" and "DOWN" functions. The row and column lines of the keypad are connected to ports on the ILB section of Nell. The rows (KEYROW: 0-5) are inputs with 50k pull-up resistors, while the columns (KEYCOL: 0-3) are outputs. When a key is pressed, the corresponding row and column are connected together, causing the row input to go low and generate an interrupt. The columns/rows are then scanned by Nell to identify the pressed key.

6.5.3 Display and Interface
Power to the LCD is controlled by NELL #N3 and can be switched on and off via ILBPORT0 (LCDPWR). A high on this output powers the LCD; a low switches it off. There is also the control output LCDCS which is also derived from NELL #N3, this acts as the chip select enable for the LCD module. There is also a 20 way address bus, which carries the address coding information for displaying graphical text onto the LCD. In addition to the address bus there is also a 15-way data bus for relaying display data to the LCD. The connections DE (Data Enable) and WE (Write Enable) from NELL #H11/H14 perform data enable and write enable functions. See Figure.10d: KeyPad, Display and SIM Interface

SIMVCC

SIM Data (NELL#N5) SIM CLK (NELL#M5) SIM RST (NELL#P5) keycol(0:3)
(NELL#H4-J3) BOOK

SIM

backlight enable
(NELL#C3)

+3VNELL

backlight CLR 2 5 8 0 3 SEND 6 9 # up down Red Led
(NELL#D6)

Green Led
(NELL#B6)

PWR KEY (NELL#H2)

1 4 7 *

+3VNELL

GRN LED
+3VNELL

keyrow(0:5)

(NELL#J4-K4)

RED LED

LCD
LCD PWR (NELLl#N3) LCD_CS (NELL#N3) Address Bus (NELL#C6-C12) Data Bus (NELL#A4-G2) 96 x 32 Pixel Graphical Display Module

Figure.10d: KeyPad, Display and SIM Interface

6.5.4 SIM Interface
The SIM interface includes a voltage level shifting circuit, which allows the DB2000 to operate with both 3 and 5 volt SIMs.The SIM interface is managed by NELL via five control signals: 1. SIMPWR (NELL#L5) This output from NELL connects to MiniMoe (IC19) #20. A logic high switches the output SIMVCC (#1) to on, and supplies power to the SIM connector(#6). 2. SIMRST (NELL#P5) This output connects to the SIM connector (#2). It provides a reset function on the SIM card when performing data operations.

3. SIMCLK (NELL#M5) This output connects to the SIM connector (#3). It is used to clock data to and from the SIM card and can be switched off when not required in order to save power. 4. SIMDT (NELL#N5 - SIMDATA) This output connects to SIM connector (#6). All data to and from the SIM Card is transferred along this line. 5. SIMVSEL (NELL#L3) This control signal from NELL is used to select the operating voltage of the SIM card. Setting the SIMVSEL high switches regulator 5 in MiniMoe to 5v which in turn is output to the SIMVCC rail. A low switches the SIM supply to 3v.

6.6

Audio and Miscellaneous Interfaces

The audio and miscellaneous interfaces include the following: 1. Microphone 2. Ear-piece 3. Hands free Interface 4. Buzzer driver 5. Battery charging circuit 6. Vibrator 7. Simple Hands Free Interface (SHF) 6.6.1 Microphone The microphone is mounted in the handset front cover and connects to the logic board via two sprung contacts on the P5 connector. The audio signal is passed to the logic board and to pin D4 of the P6 Simple Hands Free (SHF) socket. Inside the socket there is a miniature switch which is closed when there is no SHF connected. With this switch closed this allows the audio signal through to the MIC IN (#4) pin of IC27. The voltage supply VREG is output from IC27 #3, and is a bias voltage for both the MIC Audio path (through R156) and +TXAF lines. See Figure:10E. Audio and Miscellaneous Interfaces The microphone or TXAF signal is then A/D converted by the CSP part of Superchip (IC27). The digitised speech is then passed to the DSP section of IC27 for processing (coding, interleaving etc.). The coded speech data returns to the CSP for GMSK modulation, D/A conversion and output as TXI and TXQ signals IC27 #86-89 - to the W2013 transceiver (IC100) for modulation onto the air interface.

6.6.2 Earpiece The earpiece is driven directly from IC27 AOUTP(#94) and AOUTN(#93) pins. The gain is controlled by the DSP software element within IC27. The earpiece is located in the handset front panel, and the signals are routed to it via two connection pads on the front of the logic board. RXI and RXQ signals from IC300 (PMB2410) are fed to IC27 #77-80 (Superchip) where they are amplified and then A/D converted. The I and Q samples are stored in lots of 32 before the DSP part of Superchip (IC27) is interrupted to process them. The DSP will carry out error detection and correction, and assemble the speech data into a form acceptable to the D/A converter in the CSP section. After D/A conversion the signal is output on IC27 #93/94) - earpiece - and / or #95/96) - RXAF. 6.6.3 Hands-Free Interface The audio out (RXAF+/-) to the hands-free kit consists of a pair of differential signals from IC27's auxiliary outputs (#95-96), which are tracked down the board to the system connector (P5) at the base of the handset. The audio in (TXAF+/-) from the hands-free is converted to a single signal using the op-amp (IC13). The bias voltage VREF from IC27 #3 is used as a reference voltage for this amplifier. The TXAF signal is then input to the AUXIN (#99) of IC27. The DC level of the signal is supplied to the AUXOUT pin. 6.6.4 Buzzer Driver The buzzer or alerter is a piezo-electric transducer which is driven by a pulse-width modulated square wave from the PWMOUT output of NELL (#M14). TR4 and TR11 amplify the signal in order to achieve the specified loudness of 100dBa. See Figure:6E. Audio and Miscellaneous Interfaces. 6.6.5 Battery Charging The battery is charged via a constant 850mA current source, which is plugged into the DC jack in the system connector P5 #2. Charge control is implemented in software using the analogue to digital converter in NELL. It then determines the type and capacity of the battery connected by reading the battery ID resistor (BATID), on an A/D converter port, from which it determines the charging algorithm. When an external charging source is connected via the P5 connector an interrupt signal EXTCHG is sent to NELL #N4. When NELL receives this interrupt it initiates the charger enable signal CHGEN, this action switches on TR28 which activates FET TR3. When TR3 is conducting it allows the battery to be charged. Battery charging current is measured by means of a fixed loop stripline or "shunt" which is mounted internally within the layers of the PCB. When

charging the stripline gives a voltage value directly proportional to the charging current of the battery, this voltage CHGSENSE is sent to NELL #P9 on a A/D converter port, from which it determines the charge current. See G4H Logic circuit diagram, page 1. 6.6.6 Vibrator The vibrator is located on the board to board shield and is connected to the logic board via a connector cable, which plugs into socket: P2-A1 & P2-B2. The vibrator is driven by the signal VIB, which is output from NELL (#F2). The signal is amplified by the transistors TR4-B and TR12 and is supplied from VBAT. See G4H Logic circuit diagram, page 2. 6.6.7 Simple Hands Free Interface The simple hands free (SHF) interface allows the user to communicate via a single earpiece, which fits into the ear and a mic, which is joined to the interface cable. The SHF lead is connected to the DB2000 via a small jack plug, which plugs into a socket mounted into the side of the mobile. When the SHF lead is plugged in, the mobiles mic and earpiece are disconnected. When the SHF lead is not connected, the mobiles internal microphone (connected across:P5- #17 & #18) output passes through a switch (normally closed) fitted inside the SHF socket (P6- #B2 & #D4) and onto IC27 #4 for processing. If the SHF lead is connected then the switch contact is opened, thus disconnecting the mobiles own internal mic. The SHF earpiece connects across contacts C3 and A1 of the P6 connector. The output RXAF+ of IC27-#96 provides the audio output for the SHF earpiece. The mobile detects that the SHF is connected by the monitoring the voltage level at the point:SHFREE (NELL # B7), which is biased by the supply +3VAUDIO. When the SHF earpeice is connected the voltage level at the point SHFREE is taken low by the earpeice, which connects it to ground by the contact: A1 of the P6 connector. NELL will then instruct IC27 to disable the mobiles audio outputs (#9394) and instead route the audio through the auxiliary output:RXAF+ (#96) to the SHF earpeice.

Figure.10E: Audio and Miscellaneous Interfaces

+3VAUDIO SHFREE NELL #B7 SHF P6 E/P C3 A1 B2 SHF MIC D4
18

GND

5 4
MIC IN GND

AOUT BP AOUT BN

94 93 96 95
GND

+ -

E/P

3

VREG

RXAF+ C/KIT AF OUT RXAFGND VBAT
+3VNELL

Superchip (IC27)

HHP MIC

17

P5
AGND

GND

100dB

TXAF+ C/KIT AF IN TXAF-

+3VAUDIO +

NELL (M14) 99 AUX IN

GND

+

-

IC13

GND

BUZZER

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Section 4

Servicing
Part 1 Part 2 Part 3a Part 3b Cables, Jigs and Fixtures Equipment Configuration Disassembly Assembly

Part 1: Cables, Jigs and Fixtures
Detailed below are a range of cables, jigs and fixtures available for use on repair and test/calibration stations.

1.1

Inter-board Connector Assembly

(M5-SP0104)

This provides the connection between the logic and the TRX boards, while the HHP is disassembled. It allows maximum access to both sides of the boards for fault finding and repair.

1.2

Repair Fixture

(M5-SP0109/A)

This provides a stable platform for both the logic and TRX boards, while undertaking repair and fault finding. It is designed to allow access to both sides of the boards and should be used in conjunction with the Inter-board Connector Assembly.

1.2a Repair Fixture

(M5-SP0109/B)

The upgraded repair fixture allows for a more comprehensive test. The fixture incorporates a microphone, earpiece and sim test facility. NOTE: The microphone, earpiece and sim test facility is also available as a separate upgrade, (M5-SP0109/C).

1.3

RF Measuring Cable

(M5-SP0100)

This provides a RF connection to the HHP for signal monitoring/injection or HHP call sequence testing. It is approx. 1metre in length and is terminated in a SMA connector.

1.4

Data Test Cable

(M5-SP0101)

The Data cable can be used on both repair and test/calibration systems to enable control of the HHP through the I/O port. The data cable will be terminated with a 25-way female D-type connector for compatibility with the test-box or PC.

1.5

Dummy Battery (M5-SP0102) )

The Dummy Battery will supply d.c. power to a fully assembled HHP. It can be connected to a d.c. power supply or to the GSM Test Jig.

1.6

GSM Test Jig

(M5-SP0110)

This unit enables Test Mode on the HHP and allows entry of commonly used test sequences via a menu system. It also provides remote operation of the HHP keypad. The LCD unit indicates the menu status and displays information from the HHP LCD. A 5v supply is required. This unit is for use on a repair bench in conjunction with: DC Power Leads, Dummy battery, RF and Data Test Cable

1.7

DB2000 Serial Level Converter (M5-SP0106)

The DB2000 Serial level converter acts as a 25 to 9 way interface between the PC controller and the HHP in the test/calibration system. The DB2000 Serial level converter requires an external 3.8V supply. The D.C socket and lead with banana plugs is used to supply the converter.

Part 2: Equipment configurations
The test equipment configurations for repair, test/calibration and simple functional testing are shown below. Where specific items of test equipment are required, make and model numbers are quoted.

2.1

Repair bench configuration
Spectrum Analyzer Oscilloscope Power Supply 5.0v dc

GSM/PCN test set

Dummy battery (optional)

DC Power Leads

Logic and TRX boards

RF Test Cable GSM/PCN Test Jig

DB2000 Repair Fixture Data Test Cable

This configuration is only an illustration of the types of equipment required. The requirement for a Spectrum Analyser in each set up will be dependent upon which GSM Test Set is chosen.

2.2

Test/calibration configuration

GP-IB Cable

HP E3631A
DC Power Supply

HP8922P or R RF cable

GSM Tester

P/C with GP-IB board
75MHz Pentium with National Instuments GPIB-TNT card

DB2000

Test Data

Dummy Battery

Test SIM
RF In/Out

RS-232C Interface Cable

GSM1800 UPGRADE

Serial Level Converter

System I/O cable - data to 25 way

Will be offered by NEC Tech UK

This configuration is essential for component level repair, as calibration of RX and TX circuits is required on every repair. The system will be controlled by software provided by NEC Technologies (UK) Ltd, which supports the equipment detailed in the illustration. This equipment is: · GSM Test Set · DC Power Supply · Controlling PC Hewlett Packard HP8922P or R Hewlett Packard HPE3631A A minimum specification of P133/16Mb RAM. Windows NT 3.5 A HP-IB board should be fitted. NEC Tech (UK) M5-SP0107 NEC Tech (UK) M5-SP0101 NEC Tech (UK) M5-SP0102 NEC Tech (UK) M5-SP0106 NEC Tech (UK) M5-SP0100 National Instruments ATGPIB/TNT Double shielded GPIB Cables

· · · · · · · · · ·

Flash down-loader System I/O cable Dummy battery Serial Level Converter RF Cable GPIB Card GPIB Cables N-Type to SMA Adapter GSM Test Sim Printer and Cable

Centronix Printer (Optional)

The calibration items are: · TX power vs. time template at GSM power levels 5 to 15 and PCN power levels 0 to 15 · Receiver signal path loss compensation

Part 3a: Disassembly
Caution: Ensure an Anti-Static strap is worn and connected to an earth bonded bench before handling any components.

Antenna Removal.

The Thread Antenna can be removed from the HHP assembly by hand. Simply grip the wide part of the antenna and turn it anti-clockwise until it is completely free and slide it out of the HHP assembly.

Removal of screws from the B - Cover
Two M1.6 countersunk screws

Using a T6 Torx Screwdriver Remove the two M1.6 countersunk screws located towards the bottom of the HHP assembly.

Removal of the HHP assembly from the A - cover
Grip the bottom of the HHP assembly and gently lift the B cover with Assembly away from the A - cover. This is made easier by gently easing the A - cover sidewalls out, since this will disengage the positioning clips on the B- cover.

B - Cover

Positioning Clip

A - Cover

Removal of keymat from A-Cover assembly

Remove Keymat from A-Cover, ensuring that the metal pads remain in the back of the keymat.

Removal of the Window assembly from the A-Cover.

By gently pressing against the Window assembly from the rear side of the A-Cover the Window will push out.

Disconnecting the Vibrator

Disconnect the vibrator by gently pulling the vibrator connector from the socket. NB: NB Ensure the vibrator wires are kept away from the Baseband Assembly when removing the Baseband board.

Removing the Baseband board Assembly screws
The two 1.8 x 12mm pan head screws need to be removed using a torx T6 screwdriver. This will allow access to the Baseband and TRX Assembly.

Removal of Baseband board from B-Cover Assembly
B B

A A Pull the retaining clips gently outwards and lift the baseband board
B slightly to release the SK500 socket from PL400. Raise the baseband board from the retaining clip side. This will make dis-assembly easier.

Locating Eyes Location tabs The next stage is to remove the baseband board away from the assembly. This should be done in order to dislocate the location tabs from the locating holes. The baseband board will then be free from the BCover assembly.

Removing the LCD from the Baseband board

buzzer LCD flexi Retaining clips

To remove the LCD, first unclip the retaining clips and then fold the LCD back over the buzzer. Then from under the LCD, remove the `mylar' tape fitted over the `Ziff' connector and flexi. The locking wedges on either side of the connector should then be unlocked to free the LCD from the board.

Removal of I/O Connector
This can be simply removed by carefully pulling the connector away from the baseband board.

Removing Board to Board shield.
Screw holes

clips Remove the three 1.8 x 8mm pan head screws from the board to board shield. Then lift the shield out at the angle shown. This will allow the shield to be pulled out from under the clips and out of the B-Cover assembly

Removing the RF board from the B-Cover
The RF board is removed in a similar way to the board to board shield. The screws that hold the RF board in position are removed with the board to board shield, so the RF board is simply lifted out at an angle from under the positioning clips.

Part 3b: Assembly
Fitting the Back-up battery
Ensure Anti-Static strap is worn and connected to the earth bonded table before handling any components. Inspect all components for any obvious damage.

GROUND CONTACT

MOUNT THE BATTERY IN THE ORIENTATION SHOWN.

CAREPOINT:
Check the ground contact, (sho