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PRELIMINARY DATA SHEET
SDA 9489X PIP IV Advanced SDA 9589X SOPHISTICUS Version B31 High-End Picture-In-Picture ICs
Edition Dec. 14, 2001 6251-562-2PD
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet
High-end Picture-In-Picture (PIP) ICs
Version 2.3 General Description SDA 9489X 'PIP IV Advanced' and SDA 9589X 'SOPHISTICUS' belong to a new generation of Picturein-Picture (PiP) processors that combine high-quality digital PIP signal processing, digital multistandard color decoding and AD/DA conversion on a single chip. Both devices are equipped with CVBS and Y/C input interfaces. In addition the SDA SDA 9589X is also able to process YUV input signals for displaying high quality video signals e.g. coming from a DVD source.
CMOS
SOIC28-1
Figure 0-1
Picture-In-Picture
The integrated digital color decoder is able to decode all analog TV standards (PAL, NTSC and SECAM) and detects the standard automatically. Therefore the IC is suited for world-wide use. A picture reduction from 1/4 to 1/81 of original size selectable in fine steps is possible. The transfer functions of the decimation filters are optimally matched to the selected picture size reduction and can furthermore be adjusted to the viewer's requirements by a selectable peaking. A maximum of 324 luminance and 2x81 chrominance pixels per line are stored in the memory. The PiP supports split-screen applications as well as multi-PiP display. Type SDA 9489X SDA 9589X Micronas Package SOIC28-1 SOIC28-1 -2
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet
1 2 3 4 4.1 4.1.1 4.1.2 4.1.3 4.1.4 4.2 4.3 4.4 4.5 4.6 4.6.1 4.6.2 4.6.3 4.6.4 4.6.5 4.6.6 4.7 4.7.1 4.7.2 4.7.3 4.7.4 4.7.5 4.8 4.8.1 4.8.2 4.8.3 4.8.4 4.8.5 4.8.6 4.8.7 4.9 4.9.1 4.9.2 4.9.3 4.10 4.10.1 4.10.2 Micronas
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Analog Frontend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 AD-Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Signal Magnitudes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Inset Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Chroma Decoding And Standard Identification . . . . . . . . . . . . . . . . . . . . . .13 Comb Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Luminance Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Single PIP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Continuos Zoom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Horizontal And Vertical Fine Positioning . . . . . . . . . . . . . . . . . . . . . . . . .19 Multi Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Split Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Multi-PiP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Display Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 100 Hz Frame Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Mixed Standard Applications And (S)VGA Support . . . . . . . . . . . . . . . . .26 Display standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Picture Positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Wipe In / Wipe Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Output Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Luminance Peaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 RGB Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Frame Generation And Colored Background . . . . . . . . . . . . . . . . . . . . .32 16:9 Inset Picture Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Parent Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Select Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Automatic Brightness Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 On Screen Display (OSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Display Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Character Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Character and Character Background Color . . . . . . . . . . . . . . . . . . . . . .36 DA-Conversion And RGB / YUV Switch . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Pedestal Level Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Contrast, Brightness and Peak Level Adjustment . . . . . . . . . . . . . . . . . .38 -3
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet
4.11 4.11.1 4.11.2 4.11.3 4.11.4 5 6 6.1 6.2 6.3 6.4 7 8 9 10 11 12
Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Closed Caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Widescreen Signalling (WSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Indication Of New Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Violence Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 I2C Bus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 I2C-Bus Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 I2C bus Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 I2C Bus Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Recommended Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Micronas
-4
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet Features
1
Features
· Single chip solution: AD-conversion for CVBS or Y/C or YUV1), multistandard color decoding, PLL for synchronization of inset channel, decimation filtering, embedded memory, RGBmatrix, DA-conversion, RGB/YUV switch, data-slicer and clock generation integrated on chip · Analog inputs: 3x CVBS or 1x CVBS and 1x Y/C or 1xYUV 1)alternatively Clamping of each input All ADCs with 8 bit amplitude resolution Automatic Gain Control (AGC) for Y and CVBS · Inset Synchronization: Multiple time constants for reliable synchronization Automatic recognition of 625 lines / 525 lines standard · Color Decoder: PAL-B/G, PAL-M, PAL-N(Argentina), PAL60, NTSC-M, NTSC4.4 and SECAM Adjustable color saturation Hue control for NTSC Automatic Chroma Control (-24 dB ... +6 dB) Automatic recognition of chroma standards: different search strategies selectable Single crystal for all standards IF-characteristic compensation filter · Decimation: PIP sizes between 1/81 and 1/4 adjustable with steps of 2 lines and 4 pixel Resolution up to 324 luminance and 2x81 chrominance pixels per inset line Horizontal and vertical filtering dependent on picture size Automatic zoom in/out possible with three speeds · Display Features: 7 bit per pixel stored in memory Field and joint-line free frame mode display (even at 100/120 Hz AABB with picture sizes<=1/9) Two 'split-screen' modes with horizontal decimation of 2 and vertical of 1.5 or 1.0 (1.0 with single-scan 50/60Hz display only) POP display Up to 12 pictures of 1/36th size (11 still and 1 moving) Up to 6 pictures of 1/16th size (5 still and 1 moving) Up to 3 pictures of 1/9th size (2 still and 1 moving) Display on VGA and SVGA screen (fH limited to 40kHz) 8 different read frequencies for 16:9 compatibility
1)
SDA 9589X only 1-5
Micronas
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet Features
·
·
·
· · · · · ·
Line doubling mode for progressive scan applications Freeze picture Coarse positioning at 4 corners of the parent picture Fine positioning at steps of 4 pixels and 2 lines Wipe in / out programmable with 3 time periods Output signal processing: 7 Bit DAC RGB or YUV switch: insertion of an external source without PIP processing Digital interpolation for anti-imaging Adjustable transient improvement for luma (peaking) Contrast, Brightness and Pedestal Level adjustable Analog outputs: Y, +(B-Y), +(R-Y), or Y, -(B-Y), -(R-Y) or RGB Three RGB matrices available: NTSC(Japan), NTSC(USA) or EBU 64 different background colors and 4096 different frame colors Plain or 3D frame with variable width and height Data Slicing: Slicing of closed-caption (CC) or wide-screen-signaling (WSS) data Violence blocking capability (V-chip) Several filter for XDS data extraction On-screen display: 64 characters programmable 5 characters displayed in every PIP picture or 3 rows of 20 characters each 4 different character luminance values or frame color 4 background luminance values or (semi-) transparent mode I2C-Bus control (400 kHz) High stability clock generation SOIC28-1 package (SMD) Full SDA 9488X and SDA 9588X backward compatibility SDA 9388X / SDA 9389X pinout compatibility 3.3V supply voltage (5V input capable)
Micronas
1-6
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet Pin Configuration
2
Pin Configuration
XIN XQ HSP VSP SDA SCL VDD VSS I2C INT IN1 IN2 IN3 FSW
1 2 3 4
28 27 26 25
CVBS1 VREFM CVBS2 VREFL CVBS3 VSSA1 VDDA1 VREFH VSSA2 VDDA2 OUT1 OUT2 OUT3 SEL
SOIC28 -1
5 6 7 8 9 10 11 12 13 14
24 23 22 21 20 19 18 17 16 15
Figure 2-1
Pinning
Figure 2-2
Package Outlines
Micronas
2-7
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet Pin Configuration
Numb er 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Name XIN XQ HSP VSP SDA SCL VDD VSS I2C INT IN1 IN2 IN3 FSW SEL OUT3 OUT2 OUT1 VDDA2 VSSA2 VREFH VDDA1 VSSA1 CVBS3 VREFL CVBS2 VREFM CVBS1
Type I O I/TTL I/TTL I/O I S S I O/TTL I/ana I/ana I/ana I O O/ana O/ana O/ana S S I/ana S S I/ana I/O I/ana I/O I/ana
Description crystal oscillator (input) or external clock input crystal oscillator (output) horizontal sync for parent channel vertical sync for parent channel I2C-bus data I2C-bus clock digital supply voltage digital ground I2C Address interrupt V/R input for external YUV/RGB source Y/G input for external YUV/RGB source U/B input for external YUV/RGB source fast switch input for YUV/RGB switch fast blanking output for PIP analog output: chrominance signal +(B-Y) or -(B-Y) or B analog output: luminance signal Y or G analog output: chrominance signal +(R-Y) or -(R-Y) or R analog supply voltage for DAC analog ground for DAC uppper reference voltage for ADC and DAC analog supply voltage for ADC analog ground for ADC CVBS3 or V (SDA 9589X) or C Input lower reference voltage for ADC CVBS2 or U (SDA 9589X) or Y (from Y/C) Input mid-level reference voltage for ADC CVBS1 or Y (from YUV, SDA 9589X) Input
I= Input / ana=analog / O= Output / TTL=Digital (TTL) / S=Supply voltage
Table 2-1 Micronas
Pin Description 2-8
3
SDA 9589X (B31)
SDA 9489X (B31)
Micronas
VDD
7 8 19 20
Figure 3-1
VSS VDDA2VSSA2
MUX DEMUX
VDDA1 VSSA1
22
23
VREFH Skewcomp. H/V Scaler Decimation RGB Matrix Triple DAC 3x7bit
27
VREFM
21
Block Diagram
Block Diagram
Peaking Oversampling Insertion
VREFL
25
Triple ADC 3x8bit 1)
eDRAM
Color Decoder
PAL/ SECAM/ NTSC
11
IN1
12 13
DUV/DCHR
DCVBS/DY
Frame Generation OSD
IN2
CVBS1
28
CVBS2 Memory Controller Display Controller
26
768kbit
CVBS3 Inset Sync Processing
24
Input Select Clamp Gain
IN3 14 Fast FSW RGB/YUV 18 OUT1 Switch 17 OUT2
16 15
Y/C and Sync Sep.
OUT3 SEL
I 2C Controller Data Slicer Acquisition
10 1 2
Clock Synthesizer
Parent Sync Processing
3 4
6
5
9
SCL
SDA
I2C
INTR
XIN
XQ
HSP
VSP
1) SDA 9589X, SDA 9489X: 2x8bit
XTAL 20.25 MHz
Preliminary Data Sheet
Block Diagram
3-9
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
4 4.1 4.1.1
System Description Analog Frontend Input Selection
An analog inset CVBS signal can be fed to the inputs CVBS1-3 of SDA 9589X/SDA 9489X. Each of these sources is selectable via I2C bus (CVBSEL). CVBS2 and CVBS3 can be used as separate Y/C inputs. At SDA 9589X YUV sources can be connected to CVBS1, CVBS2 and CVBS3 provided YUV operation being enabled (YUVSEL). Using an external switch SDA 9589X can operate in applications with both YUV and CVBS signals.
CVBSEL D1 D0 YUVSEL Input remark
CVBS1 0 0 0 0 1 Y (VBS) CVBS
CVBS2 CVBS Y (VBS) U (CB)
CVBS3
0 0 1 1 X
0 1 0 1 X
C CVBS V (CR)
Y/C mode YUV mode (only SDA 9589X)
Table 4-1 4.1.2
Input selection AD-Conversion
All signal are clamped and AD-converted with an amplitude resolution of 8bit. CVBS and Y signals are clamped to the sync bottom or backporch, selectable by CLMSTGY. U/V and C signals are always clamped to their mid-level during blanking.
Inset Video
HD
CLMPIST
CLAMPI
CLMPID
Figure 4-1 Micronas
Clamping timing 4-10
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
The clamping pulse can be shifted in position (CLMPIST) and length (CLMPID) to adjust to the specific application. The ADCs are driven by a 20.25 MHz free running crystal clock which is not related to the incoming CVBS signal. To avoid aliasing by subsampling the CVBS signal and the Y/C signals should be bandlimited to 10MHz. In the same manner the U/V signal frequency spectrum should not exceed 5 MHz. The digital filtering suppresses all frequencies above the usable spectrum. 4.1.3 Automatic Gain Control
To accommodate to different CVBS input voltages an automatic gain control has been implemented. The chip works correctly for input voltages in the range from 0.5 to 1.5Vpp. For best signal-to-noise ratio, the maximum CVBS amplitude is recommended if available. The AGC behavior can be chosen out of four possibilities (AGCMDE). The sync height serves as reference for the gain control in the typical application. When using overflow detection only, the gain is set to maximum and is reduced whenever an overflow occurs. This procedure will be executed again when a channel change is detected or the gain control is manually reset by AGCRES.
2
Automatic Gain Control Characteristic
1.5 Input Voltage [V]
1
0.5
0
0
2
4
6
8 AGCVAL
10
12
14
16
Figure 4-2 4.1.4
AGC characteristic Signal Magnitudes
The nominal CVBS signal with 75% color has a magnitude of 1 Vpp. The upper headroom is left to permit signals with 100% color resulting in 1.23 Vpp. The Y signal must always contain the sync part. Its levels correspond to the CVBS levels except for the missing color and burst. After A/D conversion the video part is clamped to its black value and is amplified to 224 digital steps. The nominal signal levels ensure correct brightness and saturation. The YUV signal levels conform to the ITU 601 recommendation.
Micronas
4-11
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
255 217
upper headroom
255 224 CRYC = 1.2 Vpp white SRY = 1 Vpp
upper headroom
SRC = 0.89 Vpp
SRUV = 0.7 Vpp
128
68 4 0
burst
black
32
lower headroom
0
lower headroom
Figure 4-3
CVBS/Y and chroma ADC input signal range
255 240 212 75% U 128
upper headroom
255 240 212 CRUV = 0.8 Vpp SRUV = 0.7 Vpp 75% V 128
upper headroom
44 16 0
lower headroom
44 16 0
lower headroom
Figure 4-4
UV input signal range
Conversion Range CRYC Signal Range SRY Signal Range SRC Conversion Range CRUV Signal Range SRUV
AGCVAL D3 D2 D1 D0
0 1 1
0 0 1
0 0 1
0 ... 0 ... 1
0.5Vpp ... 1.2Vpp ... 1.5Vpp
0.42Vpp ... 1.0Vpp ... 1.25Vpp 0.89Vpp 0.8Vpp 0.7Vpp
Table 4-2 Micronas
ADC conversion range and required input signal voltage 4-12
CRUV = 0.8 Vpp
CRYC = 1.2 Vpp
100% chroma
75% chroma
burst
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
4.2
Inset Synchronization
Horizontal and vertical sync pulses are separated after elimination of the high frequency components of the CVBS signal by a low pass filter. Horizontal sync pulses are generated by a digital phase-locked-loop (DPLL). Its time constant is adjustable between fast and slow behavior in four steps (PLLITC) to consider different input sources (e.g. VCR). Noisy input signals become more stable when a noise-reduction is enabled (NSRED). Additionally weak input signals from a satellite dish ('fishes') become more stable when SATNR is enabled. Both should be enabled to have best available performance. A vertical flywheel mode improves vertical sync separation for weak signals (VFLYWHL, VFLYWHLMD). Additionally, v-syncs may be gated by VTHRL50/ 60 and VTHRH50/60 to reject invalid v-syncs. Dependent on detected linestandard, the VTHRx50 or VTHRx60 setting is used. 50 Hz or 60 Hz operation for sync separation may be forced separately or selected to work automatically (FLNSTRD).When NOSIGB is enabled, a colored background is shown instead of the picture when PIP is out of (horizontal) synchronization. The detected line standard is indicated by SYNCSTAT. 4.3 Chroma Decoding And Standard Identification
The system is able to decode NTSC and PAL signals with a subcarrier of 3.58MHz and 4.43MHz (PAL B/M/N/60, NTSC M/4.4) as well as SECAM signals with 4.05/4.2MHz subcarrier. The system may be forced to a certain standard, or an automatic standard detection can be used (CSTAND). For automatic standard detection, some standards which are not likely to be received can be ignored to improve the detection process. Depending on the detected line standard (525 or 625 lines) the color standard detection circuit searches for 60 Hz signals (NTSC-M / PAL-M / PAL 60 / NTSC44) or 50 Hz signals (PAL-B / SECAM / PAL-N) respectively. Within each line standard, the standard is detected by consequently switching from one to another. This standard detection process can be set to slow or fast behavior (LOCKSP). In slow behavior, 25 fields are used to detect the standard, whereas 15 fields are used in fast behavior. If unsuccessful within this time period the system tries to detect another standard.For SECAM detection, a choice between different recognition levels is possible (SCMIDL, SECACCL, SECDIV) and the evaluated burst position is selectable (BGPOS).
Micronas
4-13
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
.
CSTANDEX D1 D0 NTSCM PAL60 PAL-N PAL-M PAL-B SECAM NTSC 44
0 0 1 1 Table 4-3
0 .1 0 1 Considered color standards for automatic standard detection
For getting the chrominance information the digitized video signal is multiplied with the regenerated color subcarrier once in-phase and once phase-shifted by 90°. After lowpass filtering digital UV is available for PAL and NTSC. The subcarrier is regenerated by a digital PLL. At SECAM operation the PLL runs free and generates the line-wise alternating subcarriers. A CORDIC structure demodulates the frequency-modulated UV signals. The following SECAM de-emphasis filter characteristic is adjustable (DEEMP). The chroma signal can be filtered before demodulation by means of a selectable IFprefilter (IFCOMP).
0 5 2.5 5 0 gain [dB] 10
3.58
4.4
IFCOMP = '00' IFCOMP = '01'
DEEMP = '00' DEEMP = '01'
gain [dB]
2.5 5 7.5
15
DEEMP = '10' DEEMP = '11'
IFCOMP = '10'
20
0
0.5
1
1.5
2
2.5
10
2
3
4 frequency [MHz]
5
6
frequency [MHz]
Figure 4-5
SECAM de-emphasis filter characteristic and IF-compensation filter characteristic
The Hue Control (HUE) influences the phase of the demodulation subcarrier between -44.8° and 43.4° in steps of 1.4°. This is provided for NTSC only and adjustment is ineffective for PAL and SECAM signals. The reference for the subcarrier generation is a crystal stable clock of 20.25000 MHz. In order to avoid color standard detection problems, the maximum deviation of this Micronas 4-14
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
frequency should not exceed 100ppm. For a good PLL locking behavior a maximum deviation of 40ppm is recommended. A small frequency adjustment (-150 ... +310 ppm) is possible for using a crystal with small frequency deviations (SCADJ). For test purposes, CPLL allows to open the loop of the chroma PLL. For deviations in the chroma signal up to 30dB, a stable output amplitude after chroma decoding is achieved due to the ACC (Automatic Chroma Control). If the chroma signal (color burst) is below a selectable threshold (CKILL), the color will be switched off. Alternatively the color-killer can be bypassed and the color can be switched on or off under all conditions (COLON). By setting ACCFIX, the automatic chroma control is disabled and set to a default value. CKILL D1 0 0 1 1 X Table 4-4 D0 0 1 1 1 X 0 0 0 0 1 30 dB 18 dB 24 dB color always off color always on COLON color killed at damping of
Color-killer adjustment
The bandwidth of the chroma filter is adjustable via CHRBW. The bandwidth depends on whether the decoder is in SECAM operation or not. A change in CHRBW does not result in a chrominance position shift on the screen. CKSTAT can be read out and gives information whether the color is switched on or off. STDET indicates the detected color standard. Additionally PALID and PALDET signal whether a PAL signal is applied. 4.4 Comb Filtering
Depending on the selected picture size and color standard, a comb filtering is performed for luminance and chrominance. A comb filter uses the spectral interleaving of the encoded luminance and chrominance to separate both without cross artifacts. Thus cross-color and cross-luminance are suppressed effectively. For NTSC sources, a comb filtering is performed for all picture sizes. Due to reduced bandwidth in horizontal and vertical direction a strong reduction of cross artifacts can be achieved for PAL signals. The same applies for the luminance signal of SECAM signals.
Micronas
4-15
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
4.5
Luminance Processing
The A/D-converted CVBS (or Y) signal is digitally clamped to back porch. Depending on the transmitted standard and operational area, an offset between black- and blanking level can be found in the incoming signal ('7.5 IRE'). As for some applications a black offset is not desired, controlling may be done using LMOFST. The positive or negative offset is added to the Y signal before scaling.
Received signal
BLACK value BLANK value
Processed signal
BLACK value BLANK value
M standard signals
LMOFST='00' (no additional offset)
LMOFST='10' (reduction of 16 LSB)
BLACK value BLANK value
BLACK value BLANK value
B/G/H/I/N standard signals
LMOFST='00' (no additional offset)
LMOFST='01' (addition of 16 LSB)
Figure 4-6
Black level correction of luminance signal
The color carrier is removed out of a CVBS signal by means of a notch filter. It is set to the corresponding color carrier (3.58 or 4.4 MHz) only if the standard is detected permanently. This prevents the luminance sharpness of being changed within the standard search process. For Y signals the notch is disabled. A special peaking can be applied to the notch-filter (NADJ) to make it steeper. For a fine adjustment of delaycompensation between luminance and chrominance, YCDEL allows a luminance shifting in 16 steps of 50ns. 4.6 4.6.1 Decimation Single PIP Mode
Luminance and chrominance signals are filtered in horizontal and vertical direction. The coarse horizontal and vertical picture size (1/2, 1/3, 1/4, 1/6) is independently programmable with SIZEHOR and SIZEVER. A fine adjustment in steps of 4 pixel and 2 lines is possible by HSHRINK and VSHRINK, which allows correct aspect ratio for multistandard applications (50/60 Hz mixed mode, (S)VGA). For main decimation factors, the stored number of pixel and lines are listed in the following tables. Micronas 4-16
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
SIZEHOR D1 0 0 1 1 Table 4-5 D0 0 1 0 1
horizontal scaling 2:1 3:1 4:1 6:1
PIP Pixel per line Y 324 216 160 108 (B-Y) 81 54 40 27 (R-Y) 81 54 40 27
Number of stored pixel per line dependent on SIZEHOR
SIZEVER D1 0 0 1 1 Table 4-6 4.6.2 D0 0 1 0 1
vertical scaling
PIP lines 625 lines source 525 lines source 108 72 54 36
2:1 3:1 4:1 6:1 Number of stored lines per field
132 88 66 44
Continuos Zoom
The continuos zoom feature changes the picture size rapidly in an animated manner. It is available in single-PIP mode for picture sizes smaller or equal 1/4 of the undecimated picture. There are three possibilities of using the zoom feature: · The PIP is zoomed via HSHRINK and VSHRINK manually. This requires an I C protocol each time the picture size should change. CZMEN should be used to synchronize the update of HSHRNK/VSHRNK with SIZEHOR/SIZEVER. · A different way is to make usage of the automatic zooming. The zoom speed can be controlled by CZMSP. When switching PIP on or off by using PIPON, the PIP zooms automatically to the selected picture size or disappears at size of 1/81. · A zooming between two picture sizes can be performed by changing the HSHRINK, VSHRINK, SIZEHOR, SIZEVER values when CZMEN is enabled. Then the new picture size is obtained by zooming and not taken immediately. Automatic zooming is only possible in frame mode. Being in field mode, the picture size remains stable until frame mode occurs or until the internal counter reaches the desired Micronas 4-17
2
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
picture size. Then the size changes immediately. Equal to the wipe process, the zooming direction depends on the coarse position (CPOS).
625 lines
525 lines
625 lines
525 lines
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 0 1 2 3 4 5 6 7 8 9 10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
2 2,03 2,06 2,09 2,13 2,16 2,2 2,23 2,28 2,31 2,36 2,41 2,44 2,48 2,53 2,59 2,64 2,69 2,75 2,81 2,88 2,94 3 3,07 3,14 3,21 3,3 3,38 3,47 3,56 3,66 3,77 3,89
132 130 128 126 124 122 120 118 116 114 112 110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68
2 2,03 2,08 2,13 2,16 2,2 2,25 2,3 2,34 2,41 2,45 2,52 2,58 2,64 2,7 2,77 2,84 2,92
108 106 104 102 100 98 96 94 92 90 88 86 84 82 80 78 76 74
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3
4 4,13 4,25 4,41 4,56 4,72 4,88 5,06 5,28 5,5 5,75 6 6,28 6,61 6,94 7,31 7,78 8,25 8,81 9,42 10,17 11,02
66 4,01 64 4,15 62 4,31 60 4,5 58 4,69 56 4,9 54 5,13 52 5,39 50 5,7 48 46 44 6 42 6,38 40 6,75 38 7,22 36 7,73 34 8,3 32 9 30 9,8 28 10,78 26 24
54 52 50 48 46 44 42 40 38
36 34 32 30 28 26 24 22 20
3 3,09 3,19 3,28 3,38 3,49 3,61 3,73 3,87
72 70 68 66 64 62 60 58 56
Table 4-7
Number of stored lines per field dependent on VSHRNK
Micronas
4-18
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2,00 2,02 2,05 2,08 2,10 2,13 2,16 2,19 2,22 2,25 2,28 2,31 2,35 2,38 2,41 2,45 2,49 2,53 2,57 2,61 2,66 2,70 2,74 2,80 2,84 2,89 2,95
324 320 316 312 308 304 300 296 292 288 284 280 276 272 268 264 260 256 252 248 244 240 236 232 228 224 220
0 1 2 3 4 5 6 7 8 9 10 11 12 13 0 1 2 3 4 5 6 7 8 9 10 11 12
1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2
3,00 3,04 3,11 3,17 3,23 3,29 3,37 3,44 3,51 3,60 3,67 3,76 3,84 3,94 4,05 4,16 4,27 4,38 4,50 4,63 4,77 4,91 5,06 5,22 5,41 5,59 5,78
216 212 208 204 200 196 192 188 184 180 176 172 168 164 160 156 152 148 144 140 136 132 128 124 120 116 112
0 1 2 3 4 5 6 7 8 9 10 11 12
3 3 3 3 3 3 3 3 3 3 3 3 3
6,00 6,23 6,48 6,75 7,04 7,35 7,70 8,10 8,52 8,99 9,51 10,12 10,64
108 104 100 96 92 88 84 80 76 72 68 64 60
Table 4-8 4.6.3
Number of stored pixel per line dependent on HSHRNK Horizontal And Vertical Fine Positioning
All picture sizes are pre-centered inside the frame. In addition, if necessary the vertical and horizontal acquisition area can be shifted by VFP for vertical and HFP for horizontal direction.
Micronas
4-19
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
4.6.4
Multi Display Mode
SDA 9589X and SDA 9489X offer the feature to display a sub-picture more than once. The picture size and arrangement depends on the display mode (DISPMOD) and not on SIZEHOR or SIZEVER. Hence variable scaling is not possible in these modes. Display Mode 1 DISPMOD D1 0 D0 0 SIZEHOR/ SIZEVER HSRHNK/ VSHRNK 3 X1/9 4 X 1/16 Size Picture configuration single PIP mode Pixel 324 60 216 156 Lines 625 132 24 264 264 525 108 20 216 216
2 3
0 1
1 0
one upon another (same content) one upon another (same content)
Table 4-9
Multi-display modes
The display modes are shown in the appendix. The sizes of the partial pictures are listed in table 4-11 . 4.6.5 Split Screen
For split screen applications two selectable 'double window' modes in which one half of the picture is generated by the 'Sophisticus'/'PIP IV Advanced' can be used. The split screen mode can be selected by two possible combinations of DISPMOD.
Figure 4-7 Micronas
Double window mode 1.5 (left picture) and mode 1 (right picture) 4-20
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
The D1.5 mode is suited for displaying split screen on 16:9 tubes keeping the aspect ratio. The DW1 format covers the full height of the screen. The DW1 format is only suited for 50/60Hz single-scan applications and is not suited for '100Hz' or 'progressive' displays. 4.6.6 Multi-PiP Mode
There is a great variety of multi-pip modes available. Up to 11 different still pictures and one moving picture can be shown. This is useful to give an overview over broadcasted programmes (e.g. tuner-scan) or for supervising purposes. For multi-PiP modes only three fixed picture sizes are available (1/9, 1/16 or 1/36). The picture size and arrangement depends on the display mode (DISPMOD) and not on SIZEHOR or SIZEVER. Variable scaling is thus not possible in these modes. Because of limited memory capacity, the number of frozen multi-pictures is limited dependent on picture size to the number shown in the table below: picture sizes 1/9 1/16 1/36 Table 4-10 maximum number of pictures (including one live picture) 3 6 12
Maximum number of pictures in multi-PIP mode
The partial picture that is written is addressed via WRPOS. With INFRM, a frame for separation of every PiP can be selected. This is adjustable to single or dual PIP mode (INFRMOD). The current updated picture can be highlighted with PIPHLT. To avoid garbage pictures after switching from one mode to another the selected picture can be blanked with PIPBLK. MPIPBG defines wether the picture will be blanked with black or with the adjusted background color. For compatibility reasons to other devices, the DISPMOD register is split into two segments. If a display mode is chosen that is not implemented, the PIP insertion is switched off automatically (PIPON = '0'). The sizes of the partial pictures correspond to the sizes of the inset pictures of the single PIP modes.
Micronas
4-21
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
Display DISPMOD Mode D6 D5 D4 D3 D2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
1)
Size 2 X 1/9, 2 X 1/9, 3 X 1/9, 3 X 1/9
Picture configuration one upon another side by side side by side one upon another
Pixel 216 432 648 216 624 624 624 312 156 216 648 324 432 648 540 324 324
Lines 625 525 176 144 88 88 66 72 72 54
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0
0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0
0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
264 216 132 108 132 108 132 108 264 216 264 216 88 72 132 108 132 108 264 216 220 180 176 144 264 216
4 X 1/16 side by side 6 X 1/16 inverted U shaped 6 X 1/16 U shaped 4 X 1/16 2 rows of 2 pictures 4 X 1/16 one upon another 12 X 1/36 6 rows of 2 pictures 12 X 1/36 2 rows of 6 pictures 9 X 1/36 3 rows of 3 pictures 12 X 1/36 3 rows of 4 pictures 11 X 1/36 angular of 11 pictures 9 X 1/36 angular of 9 pictures 1X1/3 1X1/2 Double Window (V=1.5) Double Window (V=1)1) OSD only PIP off (PIPON=0)
all other single-scan display only Display Modes Display Control
Table 4-11 4.7
The on-chip memory capacity is 768 kbits. Provided that the same standard (50 or 60 Hz) video sources are applied to inset and parent channel, joint-line free frame mode display is possible. This means that every incoming field is processed and displayed by the SDA 9589X/SDA 9489X processors. The result is a high vertical and time resolution. Micronas 4-22
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
For this purpose the standard is analyzed internally and frame mode display is blocked automatically, if the described restrictions are not fulfilled. Then only every second incoming field is shown (field mode). Field mode normally shows joint-lines. This is caused by an update of the memory during read out. The result is that one part of the picture contains new picture information and the other part contains one earlier written field. The switching from or to frame mode is free of artifacts. Activation of frame-mode display is blocked automatically if at least one of the following conditions is not fulfilled: · Inset and parent channel have the same field repetition frequency. This means that frame mode is possible only for 50Hz inset and parent sources or 60Hz inset and parent sources. · Interlace signal is detected for inset and parent channel. For progressive scan or (S)VGA display therefore only field mode is possible. For some VCRs in trick mode, often no interlace is detected also. · The number of lines is within a predefined range for inset (FMACTI) or parent (FMACTP) channel (assuming standard signals according to ITU) FMACTP 0 1 0 1 Table 4-12 parent standard 50 Hz 50 Hz 60 Hz 60 Hz number of lines per field 310...315 290...325 260...265 250...275 FMACTI 0 1 0 1 inset standard 50 Hz 50 Hz 60 Hz 60 Hz number of lines per field 310...315 290...325 260...265 250...275
Required number of lines for frame mode display
The system may be forced to field mode by means of FIESEL. Either first or second field is selectable. 'One of both' takes every second field independent of the field number. This is meant for sources generating only one field (e.g. video-games). For progressive scan conversion systems and HDTV / (S)VGA displays a line doubling mode is available (PROGEN). Every line of the inset picture is read twice. Memory writing is stopped by FREEZE bit. The field stored in the memory is then continuously read. As the picture decimation takes place before storing, the picture size of a frozen picture can not be changed. Synchronization of memory reading with the parent channel is achieved by processing the parent horizontal and vertical synchronization signals connected to the pin HSP for horizontal synchronization and pin VSP for vertical synchronization. HSPINV or VSPINV respectively allow an inversion of the expected signal polarity.
Micronas
4-23
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
HSP VSP
VSPDEL VSPDELmax=151 (75) µs field 1 window
VSPD
(internal)
field 0 window tH/2 = 32 (16) µs tH = 64 (32) µs
values in brackets () apply for 100Hz systems
Figure 4-8
Field detection and phase adjustment of vertical pulse (VSP)
Depending on the phase between inset and parent signals a correction of the display raster for the read out data is performed. As the external VSP and HSP signals may come from different devices with different delay paths, the phase between V-sync and H-sync is adjustable (VSPDEL). An incorrect setting of VSPDEL may result in wrong or unreliable field detection of parent channel. Normally a noise reduction of the incoming parent vertical pulse is performed. With this function missing vertical pulses are compensated. The circuit works for 50/60 Hz applications as well as progressive and 100/120Hz application. (S)VGA signals are supposed to be very stable and therefore not supported by the noise suppression. By means of VSPNSRQ, vertical noise suppression is switched off. A great variety of combinations of inset and parent frequencies are possible. The following table shows some constellations.
Micronas
4-24
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
Inset Parent frame correct aspect Frequency1) Frequency1) mode ratio (HSP/VSP) (single pip)
correct aspect vertical ratio noise (multi display) suppression selectable
50 50 60 60 50 50 60 60 50 50 60 60 50 60
1) 2) 3)
50i 60i 50i 60i 50p 60p 50p 60p 100i 120i 100i 120i (S)VGA (S)VGA
2) 3) 3) 2)
standard signals supposed AABB only and picture size smaller than 1/9 valid for some parent frequencies. Please refer to Chapter 4.7.2 Available Features with varying inset and parent standards 100 Hz Frame Mode
Table 4-13 4.7.1
If the picture size is smaller or equal than 1/9 PIP a true frame mode display for 100Hz parent standard with a double field repetition rate is possible (display raster only). The picture size is indicated by the horizontal and vertical decimation factors that must be equal or below 1/3 of undecimated picture size in both directions. This guarantees enough memory for a joint-line free picture with full vertical resolution. For bigger pictures only field mode is supported. The 100 Hz frame mode is activated if READD='1' for the above mentioned picture sizes. For an acceptable quality without line flicker or motion artifacts only the mode is supported for HSP and VSP. If the sequence is detected, the field mode will be activated again. Continous switching between these modes is possible, resulting in continous switching between field- and frame mode.
Micronas
4-25
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
4.7.2
Mixed Standard Applications And (S)VGA Support
fH (kHz) TH (µs) THact (µs) lines/ active fdot (MHz) scan correct aspect ratio
remark (Napel X Naline @ fV)
720X576@50Hz (TV) 702X488@60Hz (TV) 720X576@100Hz (TV 100 Hz) 702X488@120Hz (TV 120 Hz) 720X576@50Hz (TV progressive) 702X488@60Hz (TV progressive) 640X480@60Hz (VGA) 640X480@72Hz (VGA) 640X480@75Hz (VGA) 800X600@56Hz (SVGA) 800X600@60Hz (SVGA) 800X600@72Hz (SVGA) 800X600@75Hz (SVGA) 800X600@85Hz (SVGA) 1024X768@43Hz (SVGA) Table 4-14 Micronas
15.6 15.7 31.2 31.2 31.2 31.2 31.5 37.9 37.5 35.2 37.9 48.1 46.9 53.7 35.5
64.0 63.6 32.0 31.8 32.0 31.8 31.8 26.4 26.7 28.4 26.4 20.8 21.3 18.6 28.2
52.0 52.7 26.0 26.4 26.0 26.4 25.4 20.3 20.3 22.2 20.0 16.0 16.2 14.2 22.8
625/ 576 525/ 488 625/ 576 525/ 488 625/ 576 525/ 488 525/ 480 520/ 480 500/ 480 625/ 600 625/ 600 666/ 600 625/ 600 631/ 600 817/ 768
13.5 13.5 27 27 27 27 25.2 31.5 31.5 36.0 40.0 50.0 49.5 56.3 44.9
interlace interlace interlace interlace progressive progressive progressive progressive progressive progressive progressive progressive progressive progressive interlace
Examples of supported parent signals 4-26
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
SDA 9589X and SDA 9489X allow multiple scan rates for the use in desktop video applications, VGA compatible or 100Hz TV sets. All features are provided in 'normal' operating modes at auto detected 50Hz and 60 Hz parent and inset standards. 2fH modes (100/120Hz and progressive) are supported by line frequency- and pixel clock doubling and are not detected automatically. Even on a 16:9 picture tube correct aspect ratio can be displayed by selecting the suitable parent clock. The video synthesizer generates also a special pixel clock for VGA display (see chapter 5.5.9 for details). As (S)VGA consists of a variety of scan rates the correct aspect ratio is not adjustable for all modes with the parent clock (HZOOM) because of the limited count of frequencies. For single PIP only, correct aspect ratio is maintained by the vertical and horizontal scaler (HSHRINK and VSHRINK). It is possible to display (S)VGA sources for parent display, as long as the horizontal frequency is lower than 40 kHz and the signal does not contain more than 1023 lines. For progressive scan mode, PROGEN must be set. Additionally field-mode should be forced to prevent unallowed frame-mode displaying (FIESEL). As the (S)VGA normally does not fit to the display raster generated in the vertical noise suppression, VSPNSRQ should be disabled. (S)VGA signals for inset channel are not supported. PROGEN 0 0 1 1 Table 4-15 4.7.3 READD 0 1 0 1 Expected input signal 50 or 60 Hz signal interlace 100 or 120 Hz signals interlace (reserved) 50 or 60 Hz or (S)VGA signal progressive
Selection of display field repetition Display standard
For a single-PiP, the number of displayed lines depends on the selected picture size and on the signal standard. For multi picture display, the number of displayed lines depends on the selected picture size and on the signal standard of the parent signal. Additionally, a standard can be forced by DISPSTD.
Micronas
4-27
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
DISPSTD D1 0 0 0 1 1 D0 0 0 1 0 1
DISPMOD 0 >0 x x x
Display Standard PIP depends on detected inset standard (single pip) PIP depends on detected parent standard (multi display) PIP display is always in 625 lines mode PIP display is always in 525 lines mode freeze last detected display standard and size
Table 4-16
Display standard selection
If a 625 lines picture is shown with a 525 lines parent signal, some lines are missing on top and bottom of picture. If a 525 lines picture is shown with a 625 lines display standard, missing lines at top and bottom are filled with background color or black depending on MPIPBG.
625 lines / 50 Hz
525 lines / 60 Hz
Figure 4-9 4.7.4
50 and 60 Hz Multi PiP display on 50 Hz and 60 Hz display Picture Positioning
The display position of the inset picture is programmable to the 4 corners of the parent picture (CPOS). From there PIP can be moved to the middle of the TV Picture with POSHOR and POSVER. The corner positions can be centered coarsely on the screen with POSOFH and POSOFV. Depending on coarse position, one PIP corner remains stable when changing the picture size.
Micronas
4-28
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
CPOS D1 0 0 1 1 D0 0 1 0 1
Coarse Position upper left upper right lower left lower right
Reference corner of PiP upper left upper right lower left lower right
increasing POSVER down down up up
increasing POSHOR right left right left
Table 4-17
Coarse Positioning
There are 256 horizontal locations (4 pixel increments) and 256 vertical locations (2 line increments). The pixel width on the screen depends on the selected HZOOM factor. Even POP-positions (Picture Outside Picture) in 16:9 applications are possible.
POSHOR
CPOS='01' CPOS='00'
POSVER POSVER
CPOS='10'
POSHOR
CPOS='11'
Figure 4-10 Coarse Positioning 4.7.5 Wipe In / Wipe Out
With the wipe in / wipe out function it is possible to let appear or disappear the complete inset picture starting or ending at the corner of the inset picture position defined by CPOS. Thereby the size of the visible picture-part is continuously increased and decreased respectively. During this procedure the frame is shown with its chosen widths. 3 different wipe in / out time periods or 'no wipe' are programmable via WIPESP. The wipe algorithm always works in horizontal and vertical direction. Micronas 4-29
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
wipe out
CPOS='00'
CPOS='01'
CPOS='00'
CPOS='01'
CPOS='00'
CPOS='01'
CPOS='10'
CPOS='11'
CPOS='10'
CPOS='11'
CPOS='10'
CPOS='11'
wipe in
Figure 4-11 Wipe display If WIPESP is set accordingly, PIPON controls the wipe operation. When PIPON changes the wipe operation starts. During this period, the readable PIPSTAT indicates the ongoing wipe-process. A transition of PIPON from '0' to '1' triggers the wipe-in. The wipein process stops when the picture reaches its programmed size. When PIPON changes from '1' to '0' the wipe-out starts. The wipe-out is finished when the PiP picture vanishes. Even for multi-picture display wipe operation is possible. A change of PIPON or WIPESP during wipe operation has only an effect after the wipe operation has been finished. 4.8 4.8.1 Output Signal Processing Luminance Peaking
To improve picture sharpness, a peaking filter which amplifies higher frequencies of the input signal is implemented. The amount of peaking can be varied in seven steps by YPEAK. The setting '000' switches off the peaking. The value '011' is recommended as this value provides a good compromise between sharpness impression and annoying aliasing. The characteristic for all possible settings is shown in fig. (4-12). The emphasized frequency depends on the adjusted decimation. The gain maximum is always located before the band-limit ensuring optimal picture impression. Peaking can be additionally increased by PKBOOST.
Micronas
4-30
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
10 9 8 7 gain [dB] 6 5 4 3 2 1 0
YPEAK = '000' YPEAK = '001' YPEAK = '111' YPEAK = '110' YPEAK = '101' YPEAK = '100' YPEAK = '011' YPEAK = '010'
0
0.1
0.2
0.3
0.4
0.5
normed frequency
Figure 4-12 Characteristics of selectable peaking factors (0.5 = band limit) Coring should be switched on by YCOR to reduce noise, which is also amplified when peaking is enabled. As the coring stage is in front of the peaking filter, 1 LSB noise will not be peaked. 4.8.2 RGB Matrix
The chip contains three different matrices, one suited for EBU standards, one suited for NTSC-Japan and one suited for NTSC-USA, which are selected via MAT. The signal OUTFOR switches between YUV output or RGB output. The signal UVPOLAR inverts the U and V channels and results in Y-U-V output. The standard magnitudes and angles of the color-difference signals in the UV-plane are defined as follows: MAT D1 0 0 1 1 D0 0 1 0 1 RGB matrices characteristics (B-Y) 2.028 2.028 2.028 Magnitudes (R-Y) 1.14 1.582 2.028 (G-Y) 0.7 0.608 0.608 (B-Y) 0 0 0 Angles (R-Y) 90 95 105 (G-Y) 236 240 250 EBU NTSC (Japan) NTSC (USA) (reserved) Standard
Table 4-18
The color saturation can be adjusted with SATADJ register in 16 steps between 0 and 1.875. Values above 1.0 may clip the chrominance signals.
Micronas
4-31
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
4.8.3
Frame Generation And Colored Background
With FRSEL a colored frame is added to the inset picture. The chip can display two different types of frames, one simple monochrome frame and a more sophisticated frame giving a three dimensional impression.
Figure 4-13 Normal frame and 3D frame The frame elements are always placed outside the inset picture, except for the inner shade of three dimensional frame or inner frame in multi-pip mode. There is no shift of the inset picture position if the inset frame width is modified.
character · no · character luminance · frame color
character background · transparent · char. background luminance · semi-transparent
PiP Picture · background · picture
shades · no · dark/light
frame · no · frame color
background · no · background color · frame color
Figure 4-14 Selectable picture configurations
Micronas
4-32
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
4096 frame colors are programmable by FRY, FRU, and FRV, 4 bits for each component. Horizontal and vertical width of the frame are programmable independently by FRWIDH and FRWIDV. If desired, frame color is displayed over the whole PIP size or whole picture size of the main channel when PIPBG is set accordingly. 64 background colors are programmable by BGY, BGU, BGV, 2 bits for each component. Alternatively BGFRC sets the background to frame color. 4.8.4 16:9 Inset Picture Support
To remove dark stripes at 16:9 inset pictures the vertical display area is shrinkable with VPSRED. The number of omitted lines depends on the vertical decimation factor. vertical decimation factor 1 ... 6 Table 4-19 . 44 35 36 29 displayed lines (50Hz) 264 displayed lines (50Hz) with reduction 214 displayed lines (60Hz) 216 displayed lines (60Hz) with reduction 175
Number of lines without and with reduction of vertical picture size
Figure 4-15 16:9 inset picture without and with reduction of vertical picture size 4.8.5 Parent Clock Generation
The phase of the output signals is locked to the rising edge of the horizontal sync pulse. The frequency varies in a certain range to ensure correct aspect ratio for 16:9 applications depending on HZOOM. The horizontal and vertical scaling can be used for all display frequencies.
Micronas
4-33
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
display format 4:3 4:3 16:9 16:9 Table 4-20 4.8.6
inset picture format 4:3 4:3 4:3 16:9
desired PiP format 4:3 16:9 4:3 16:9
required parent frequency 27 20.25 36 36
value of HZOOM D2 0 0 0 0 D1 0 0 1 1 D0 0 1 0 0
Format conversion using HZOOM Select Signal
For controlling an external RGB or YUV switch a select signal is supplied. The delay of this signal is programmable for adaptation to different external output signal processing devices (SELDEL).
frame
PiP signal OUTx
picture
SEL
SELDEL
Figure 4-16 Select timing 4.8.7 Automatic Brightness Reduction
Displaying a bright PIP picture, the beamcurrent-limitation of the parent system may become active. This may cause the parent picture to be influenced by the inset picture. Therefore a detection circuit reduces the brightness of the inset picture when the average brightness is above a selectable threshold. After bright picture content has disappeared, the initial brightness reappears. The threshold is adjustable via ABRTHD and the speed via ABRSPD. Both settings have to be selected for parent system accordingly.
Micronas
4-34
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
4.9 4.9.1
On Screen Display (OSD) Display Format
The on screen display allows to insert a block of 5 characters into each of the PIP pictures. The characters are placed in a box (background) whose width is 64 pixels and height is 12 lines. This box is placed in the upper left corner of the PIP picture. 64 different characters are stored in a character ROM. Each character is defined by a pixel matrix consisting of 10 lines and 12 pixels per line. A doubling of the character's height and width is achieved by CHRDHW. The OSD starting position is not influenced. OSD display is also possible if PIP is switched off (DISPMOD ='100011'). Now 3 lines of 20 characters each are displayed at the PiP position.
Figure 4-17 Example of OSD-only mode
Figure 4-18 Example of transparent mode (normal and double size OSD) 4.9.2 Character Programming
The characters are programmed via I²C bus using a 7 bit code which is identical with the ASCII code except for some of the special characters. The codes are stored in a character RAM consisting of 60 cells. The character codes can be transmitted in two ways: each character position can be addressed separately by its 7 bit address or the characters can be written consecutively starting at an arbitrarily chosen position. In this case the address is increased automatically. The 7 bit address consists of two parts: the 4 MSBs are used to chose one of the partial pictures and the 3 LSBs to select one of the 5 characters per block. Micronas 4-35
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
4.9.3
Character and Character Background Color
The character's color is either same as frame color (CHRFRC) or the character appears with a grey value programmable with CHRY. The character's background box is influenced by CHRBGON and CHRBGY. It can be made transparent so that behind the characters the inset picture becomes visible. Alternatively the semi-transparent mode can be chosen. At this mode the background box contains the original picture content with reduced luminance value. This mode offers a good trade-off between reduction of visible display area and character readability. 4.10 DA-Conversion And RGB / YUV Switch
SDA 9589X and SDA 9489X include three 7bit DA-converters. Brightness BRTADJ, Contrast CONADJ and overall amplitude PKLR, PKLG, PKLB of the output signal are adjustable. External RGB or YUV signals can be connected to the inputs IN1...3. By forcing the FSW input to high-level these signals are switched to the outputs OUT1...3 while the internal signals are switched off. The FSW input signal is passed through to the SEL output. The setting of RGBINS determines wether an RGB insertion is possible and which source, the external picture or the PiP, gets priority.
RGBINS='10' PIPON='1' OSD
R/V G/Y B/U
RGBINS='11' PIPON='1' OSD
RGBINS='00' PIPON='1'
RGBIN='1X' PIPON='0' OSD OSD
OSD
OSD
SEL
VDDA1
VREFM
VDDA2
OUT1
OUT2 IN2
OUT3 IN3
VREFL
VSSA1
CVBS1
CVBS2
CVBS3
PiP IV
VDD VSS
VREFH
VSSA2
RGB/VYU
FSW
VSP
HSP
SDA
SCL
XIN
INT
IN1
I2C
XQ
SEL
FSW
OSD
OSD
Figure 4-19 Visualization of RGB/YUV insertion The external RGB or YUV signals are each clamped to the reference levels of the DACs to force uniform black levels in each channel. The clamping needs careful adjustment especially for VGA applications. The position and the length of the blanking pulse as well as the clamping pulse are adjustable (CLPPOS, CLPLEN). If READD is set to '1' (100Hz mode), all pulses are shortened by one half. HZOOM influences the adjustment range of Micronas 4-36
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
the clamping and blanking pulse because of the modified clock frequency, but the pulse length is kept nearly constant.
Parent Video
HSP
allowed HSP range 256 T
BLANKP
a
b
CLAMPP
c
d
Figure 4-20 PIP horizontal blanking timing
READD D2
CLPDEL D1 D0
CLPLEN D1 D0
a (µs) Blanking Start
b (µs) Blanking Duration
c (µs) Clamping Start
d (µs) Clamping Duration
0 0 0 0 1 1 1 1 Table 4-21 4.10.1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 0 0 0 0 0 0 0
0 0 1 1 0 0 1 1
-1.5 -11 -1.5 -11.0 -0.8 -5.5 -0.8 -5.5
10.5 10.5 7.9 7.9 5.3 5.3 4 4
3 -6.4 2.2 -7.3 1.5 -3.2 1.1 -3.6
5 5 3.8 3.8 2.5 2.5 1.9 1.9
PIP horizontal blanking timing Pedestal Level Adjustment
The pedestal level adjustment controlled by I2C signals BLKLR, BLKLG, BLKLB enables the correction of small offset errors, possibly appearing at the successive blanking stage of RGB processor. This adjustment has an effect on the setup level during the active line interval of each channel like the brightness adjustment but has an Micronas 4-37
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
enhanced resolution of 0.5 LSB. The maximum possible offset amounts to 7.5 LSBs. In YUV mode (OUTFOR = '1') the action depends on the setting of BLKINVR and BLKINVB. If BLKINVR (BLKINVB) is active the offset applies to the blank level of the RV (BU) channel during the clamping interval for shifting the setup level to the negative direction. In RGB mode (OUTFOR = '0') BLKINVR and BLKINVB have no effect. 4.10.2 Contrast, Brightness and Peak Level Adjustment
The peak level adjustment modifies the magnitude of each channel separately. It should be used to adapt once the signal levels to the following stage. The contrast adjustment influences all three channels and allows a further increase of 30% of the peak level magnitude. The effect of the brightness adjustment depends on the selected output mode (RGB/YUV). In YUV mode it changes the offset of the OUT2 (Y) signal only while in RGB mode it changes the offset of all three channels at the same time. The brightness increase is up to 20%.
OUTFOR = '1' (YUV Mode) BLKINVR = BLKINVB = '0' OUT1, 3
BLKLR = 15 BLKLB = 15
BLKINVR = BLKINVB = '1' OUT1, 3
BLKLR = 15 BLKLB = 15
64 BLKLR = 0 BLKLB = 0
64
BLKLR = 0 BLKLB = 0
OUTFOR = '0' (RGB Mode)
BLKLR = 15 BLKLB = 15 BLKLG = 15
OUT1 - 3
0
BLKLR = 0 BLKLB = 0 BLKLG = 0
Figure 4-21 Pedestal level adjustment
Micronas
4-38
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
4.11
Data Slicer
Depending on SERVICE, Closed Caption data ('Line 21') or WSS (Widescreen signalling) is sliced by the digital data slicer and can be read out from I2C interface. The line number of the sliced data is selectable with SELLNR. Therefore WSS and CC can be processed in different regions (e.g. CC with PAL M). The Closed Caption data is assumed to conform with the ITU standards EIA-608 and EIA-744-A. WSS data is assumed to conform with ETS 300 294 (2nd edition, May 1996). 4.11.1 Closed Caption
The closed caption data stream contains different data services. In field 1 (line 21) the captions CC1 and CC2 and the text pages T1 and T2 are transmitted whereas in field 2 (line 284) caption CC3, CC4, text T3, T4 and the XDS data are transmitted. For more information please refer to the above mentioned standards. Raw CC as well as prefiltered data is provided alternatively. With the built-in programmable XDS-Filter (XDSCLS), the program-rating information ('V-chip') as well 2 as others can be filtered out. The XDS filter reduce traffic on the I C bus and save calculation power of the main controller. If no class filter is selected, all incoming data 2 (both fields) is sliced and provided by the I C interface. When one or more class filters are chosen, only data in field 2 is sliced. Any combination of class filters is allowed. Each 'CLASS' is divided into 'TYPES' which can be sorted out by the XDS-secondary filter (XDSTPE). Any combination of type filter is allowed. Some type filter require an appropriate class filter. 4.11.2 Widescreen Signalling (WSS)
In WSS mode (SERVICE='1') no filtering is possible. All sliced data is passed to the output registers. In this case XDSTPE selects the field number of the data to be sliced. In Europe WSS carries for instance information about aspect ratio and movie mode. 4.11.3 Indication Of New Data
The sliced and possibly filtered data is available in DATAA and DATAB. The corresponding status bits are DATAV and SLFIELD. When new data were received, DATAV becomes '1' and the controller must read DATAA, DATAB and the status information. After both data bytes were read DATAV becomes '0' until new data arrives. It must be ensured that the data polling is activated once per field (16.7 or 20 ms) or every second field (33.3 or 40 ms), depending on the slicer configuration and inset field frequency. The field number of the data in DATAA and DATAB can be found in SLFIELD. If one or more XDS-class filter are activated, SLFIELD contains always '1'. Additionally pin 10 (INT) may flag that new data is received. Default this pin is in tri-state mode to be compatible with the Micronas SDA9388X/9389X PIP devices. It can also be configured by IRQCON to output a single short pulse when new data is available or behave equal to DATAV. In the last case the output remains active until the two data Micronas 4-39
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet System Description
registers DATAA/DATAB are read. Both modes are useful to avoid continous polling of the I2C bus. The micro-controller initiates I2C transfers only when required.
while (1){ i2c_read pip4_adr, status_reg_adr, status if (status & data_valid_mask) { i2c_read_inc pip4_adr, dataa_reg_adr, dataa, datab, status process_data dataa, datab, status } } Figure 4-22 Example in pseudo-code for reading the data 4.11.4 Violence Protection
The rating information is sent in the program rating packet of the current (sometimes future) class in the XDS data stream. If only this information is desired the corresponding XDS filter (class 01h, type 05h) should be used to suppress other data. The class/packet bytes (0105h) precede the 2 bytes rating information. Each sequence is closed by the end-of-packet byte (0fh) and a checksum. This checksum complements the byte truncated sum of all bytes to 00h. Except comparison of the received rating with the adjusted user rating threshold the micro-controller should check the parity of each byte and validate the checksum to avoid miss-interpretation of wrong received data. The SDA 9589X/SDA 9489X offer some alternatives to blocking the PIP channel completely by switching it off (fig. (4-23)).
"Warning Message"
THIS PROGRAM CONTAINS VIOLENT SCENES
"Blue Screen"
"Mosaic"
Figure 4-23 Possibilities of PiP blocking The Mosaic mode (MOSAIC) hides details of the picture by reduced sharpness and increased aliasing. The picture looks scrambled and is less perceptible.
Micronas
4-40
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet Application Examples
5
Application Examples
The following two figures show 100/120Hz applications with the Micronas Featurebox SDA 9400/01. As the chip supports two I2C addresses and owns a RGB switch dual-PiP applications are easy to implement. The arrangement for best possible performance is shown in the fig. (5-1).
additional 1fH source
IN1-3
SDA9589X
SDA9589X
CVBS (Y/C, YUV)
SDA9589X
HSP/VSP OUT1-3 I2C +3.3V SDA9589X SDA9589X
SDA 9400
IN1-3
CVBS (Y/C, YUV)
SDA9589X
HSP/VSP OUT1-3 I2C
additional 2fH sources
H/V1H
H/V2H
CVBS (Y/C)
analog / digital Frontend
YUV1H
Featurebox i.e.SDA 9400
YUV2H
Backend i.e. SDA9380
Figure 5-1
SDA 9589X application with insertion in front of the featurebox
The output of two 'SOPHISTICUS' are connected to the YUV (or RGB) input of the video processor of the main channel. Due to the 4:2:2 processing within the SDA 9400 the inset picture remains brilliant.
SDA9589X
CVBS (Y/C, YUV)
IN1-3
SDA9589X
HSP/VSP OUT1-3 I2C
SDA9400
SDA9589X
SDA 9400
additional 2fH sources
H/V1H
H/V2H
CVBS (Y/C)
analog / digital Frontend
YUV1H
Featurebox i.e. SDA 9400
YUV2H
Backend i.e. SDA9380
Figure 5-2
SDA 9589X application with insertion behind the featurebox
Connecting the SDA 9589X/SDA 9489X directly to the RGB input of the RGB processor is possible as well. One picture is generated from SDA 9589X/SDA 9489X device, the other one from the featurebox. This cheap implementation preserves the chroma of inset channel at its full bandwidth, although frame mode is only possible for PiP pictures smaller than 1/9. The output of an OSD/Text processor may be fed to the RGB switch of the SDA 9589X/SDA 9489X. Micronas 5-41
SDA 9489X (B31) SDA 9589X (B31)
Preliminary Data Sheet I2C Bus
6 6.1
I2C Bus I2C Bus Address Write Address1 Read Address1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 0 1 (D6h) (D7h)
Table 6-1
Primary Address (pin 9='low-level') 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 1 (DEh) (DFh)
Write Address2 Read Address2 Table 6-2 6.2 WRITE READ
Secondary Address (pin 9 = 'high-level') I2C-Bus Format S 1101x110 A Subaddress A Data Byte A **** A P
S 1101x110 A Subaddress A Sr 1101x111 A Data Byte n NA P
S: Start condition / Sr Repeated start condition / A: Acknowledge / P: Stop condition / NA: No Acknowledge
Write operation is possible at registers 00h-21h and 2Eh-37h only, read operation is possible at registers 28, 2Ah-2Ch only. An automatic address increment function is implemented.
Micronas
6-42
SDA 9489X (B31) SDA 9589X (B31