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L4923
5V1A VERY LOW DROP REGULATOR WITH RESET AND INHIBIT
. . . . . . . . .
VERY LOW DROP (max. 0.9V at 1A) OVER FULL OPERATING TEMPERATURE RANGE ( 40 / + 125 °C) LOW QUIESCENT CURRENT (max 70 mA at 1 A) OVER FULL T RANGE PRECISE OUTPUT VOLTAGE (5V ± 4%) OVER FULL T RANGE POWER ON-OFF INFORMATION WITH SETTABLE DELAY INHIBIT FOR REMOTE ON-OFF COMMAND (active high) LOAD STANDBY CURRENT LOAD DUMP AND REVERSE BATTERY PROTECTION SHORT CIRCUIT PROTECTION THERMAL SHUTDOWN
Heptaw att ORDERING NUMBER : L4923
The device is internally protected against load dumps transient of + 60 V, input overvoltage, reverse polarity, overheating and output short circuit : thanks to these features the L4923 is very suited for the automotive and industrial applications. The reset function is very useful for power off and power on information when supplying a microprocessor. The inhibit function reduces drastically the consumption when no load current is required : typically the standby current value is 300 µA.
DESCRIPTION The L4923 is a high current monolithic voltage regulator with very low voltage drop (0.70 V max at 1 A, TJ = 25 °C). BLOCK DIAGRAM
October 1991
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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ABSOLUTE MAXIMUM RATINGS
Symbol Vi Vr VD TJ Top Tstg DC Input Voltage DC Reverse Voltage Positive Load Dump Protection (t = 300ms) Junction Temperature range Operating Temperature Range Storage Temperature Range Parameter Value 35 18 60 40 to 150 40 to 125 55 to 150 Unit V V V °C °C °C
Note: The circuit is ESD protected according to MIL-STD-883C
THERMAL DATA
Symbol Rth j-case Parameter Thermal Resistance Junction Case Value 4 Unit °C/W
PIN CONNECTION
Figure 1 : Application Circuit.
(*) RECOMMENDED VALUE : C 0 = 47 µF, ESR < 10 , (Iout > 10 mA) OVER FULL Trange.
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ELECTRICAL CHARACTERISTICS (Vi = 14. 4V, 40°C TJ + 125°C unless otherwise specified)
Symbol Vi Vo VLine SVR Parameter Operating Input Voltage Output Voltage Line Regulation Supply Voltage Rejection Test Conditions (*) Note 1 Io = 0mA to 1A TJ = 25°C Vi = 6 to 26V; IO = 10mA Io = 700mA f = 120Hz; C o = 47µF Vi = 12Vdc + 5Vpp Io = 10mA to 1A TJ = 25°C, IO = 1A Over Full T, Io = 1A Iq Quiescent Current Io = 10mA Io = 1A Active High Inhibit Io = 350mA ; f = 120Hz Co = 100µF ; Vi = 12V ± 5Vpp 1.5V < VO < VRT (off), IR = 1.6mA 3V < VO < VRT (of f), IR = 8mA 1K Reset Pull-up to VO Vo in Regul. VR = 5V CD = 100nF Vo @ Reset out H to L Transition; TJ = 25°C 40°C TJ + 125°C V6 = 3V Vo @ Reset out L to H Transition Reset out = "1" H to L Transition Reset out = "0" L to H Transition V6H VInhL VInhH IInhL IInhH Delay Comparator Hysteresis Low Inhibit Voltage High Inhibit Voltage Low Level Inhibit Current High Level Inhibit Current VInh L = 0.4V VInh H = 2.4V 2.0 40 10 6 20 3.2 3.7 4 500 0.5 4.75 4.7 20 Vo 0.15 20 VrthOFF + 0.03V Vo 0.04V 3.8 4.4 0.65 50 7 25 0.30 1.8 60 0.40 0.40 1.0 50 Min. 6 4.8 4.9 5 55 Typ. Max. 26 5.2 5.1 25 Unit V V V mV dB
VLOAD Vi Vo
Load Regulation Dropout Voltage
15 0.45
50 0.70 0.90 12 70 0.65
mV V V mA mA mA A dB V V V µA ms V V µA V V V mV V V µA µA
ISC SVR VR VRT peak IR tD VRthOFF
Short Circuit Current Supply Volt. Rej. Rset Output Saturation Voltage Power On-Off Reset out Peak Voltage Reset Output Leakage Current (high level) Reset Pulse Delay Time Power OFF Vo Threshold
IC6 VRthON V6
Delay Capacitor Charging Current (current generator) Power ON Vo Threshold Delay Comparator Threshold
(*) Note 1 : The device is not operating within the range : 26 V < Vi < 37 V.
EXTERNAL COMPENSATION Since the purposeof a voltage regulator isto supply a fixed output voltage in spite of supply and load variations, the open loop gain of the regulator must be very high at low frequencies. This may cause instability as a result of the various poles present in the loop. To avoid this instability dominant pole compensation is used to reduce phase shifts due to other poles at the unity gain frequency.The lower the frequency of these other poles, the greater must be the capacitor used to create the dominant pole for the same DC gain.
Where the output transistor is a lateral PNP type there is a pole in the regulation loop at a frequency too low to be compensated by a capacitor wich can be integrated. An external compensation is therefore necessary so a very high value capacitor must be connected from the output to ground. The parassitic equivalent series resistance of the capacitor used adds a zero to the regulation loop. This zero may compromise the stability of the system since its effect tends to cancel the effect of the pole added.In regulators this ESR must be less than 3 and the minimum capacitor value is 47µF.
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FUNCTIONAL DESCRIPTION The operating principle of the voltage regulator is based on the reference, the error amplifier, the driver and the power PNP. This stage uses an Isolated Collector Vertical PNP transistor which allows to obtain very low dropout voltage (typ. 450 mV) and low quiescent current (IQ = 20 mA typically at IO = 1 A). Thanks to these features the device is particularly suited when the power dissipation must be limited as, for example, in automotive or industrial applications supplied by battery. The three gain stages (operational amplifier, driver and power PNP) require the external capacitor (COmin = 22 µF) to guarantee the global stability of the system. Theantisaturationcircuit allows to reduce drastically the current peak which takes place during the start up. Figure 2 : Typical Reset Output Waveform. The reset function is LOW active when the output voltage level is lower than the reset threshold voltage VRth (typ. value : VO - 150 mV). When the output voltage is higher than VRth the reset becomes HIGH after a delay time settablewith the external capacitor Cd. Typically td = 20 ms, Cd = 0.1 µF. The reset threshold hysteresis improves the noise immunity allowing to avoid false switchings. The typical reset output waveform is shown in fig. 2. The inhibit circuit accepts standard TTL input levels : this block switches off the voltage regulator when the input signal is HIGH and switches on it when the input signal is LOW. Thanks to inhibit function the consumption is drastically reduced (650 µA max) when no load current is required.
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HEPTAVATT PACKAGE MECHANICAL DATA
DIM. A C D D1 E F F1 G G1 G2 H2 H3 L L1 L2 L3 L5 L6 L7 M M1 Dia MIN. mm TYP. MAX. 4.8 1.37 2.8 1.35 0.55 0.8 0.9 2.67 5.21 7.8 10.4 10.4 MIN. inch TYP. MAX. 0.189 0.054 0.110 0.053 0.022 0.031 0.035 0.105 0.205 0.307 0.409 0.409
2.4 1.2 0.35 0.6 2.41 4.91 7.49 10.05 16.97 14.92 21.54 22.62 2.6 15.1 6 2.8 5.08 3.65 2.54 5.08 7.62
0.094 0.047 0.014 0.024 0.095 0.193 0.295 0.396 0.668 0.587 0.848 0.891 0.100 0.200 0.300
3 15.8 6.6
0.102 0.594 0.236 0.110 0.200
0.118 0.622 0.260
3.85
0.144
0.152
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Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. © 1994 SGS-THOMSON Microelectronics - All Rights Reserved HEPTAWATTTM is a Trademark of SGS-THOMSON Microelectronics SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A.
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