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August, 2001
Training Materials Prepared by: Daniel Newman
CONTENTS...
2001 DLP-1 Chassis Projection Television Information INSTRUCTOR... Alvie Rodgers C.E.T.
DLP-1 Chassis DLP Basics
DLP-1 Chassis DLP Basics
DMDTM Roadmap SVGA: 848x600; 508, 800 mirrors XGA: 1024x768 chip with black aperture; 786,432 mirrors SXGA: 1280x1024; 1,310,720 mirrors
(continued) Page 0-01
DLP-1 Chassis DLP Basics
Two Mirrors The illustration shows a blow up of two mirrors on the DMD, one on and one off. Light hitting the "on" mirror will reflect through the projection lens to the screen. Light hitting the off mirror will reflect to a light absorber. Each mirror is individually controlled and is totally independent of all other mirrors. Each frame of a movie is separated into its red, blue, and green components and digitized into 1,310,000 samples for each color. Each mirror in the system is controlled by one of these samples.
(continued) Page 0-02
DLP-1 Chassis DLP Basics
Two Mirrors With Lamp, Projection, Lens, and Light Absorber The "on" mirror reflects light into the lens and the "off" mirror reflects light into the light absorber.
(continued) Page 0-03
DLP-1 Chassis DLP Basics
1-Chip DLPTM Projection System White light is forced down onto a color wheel filter. This wheel spins in sequence with the red, green and blue video signal being sent to the DMDTM. Mirrors are turned on, depending on where and how much of each color is needed for each TV field. The human visual system integrates the sequential color and sees a full-color image.
(continued) Page 0-04
DLP-1 Chassis DLP Basics
DMDTM Architecture Exploded view of an individual mirror on a DMD. Each 16 µm2 mirror on a DMD consist of these three physical layers and two "airgap" layers. The airgap layers separate the three physical layers and allow the mirror to tilt +10 or -10 degrees.
(continued) Page 0-05
DLP-1 Chassis DLP Basics
DMDTM with Mirror Removal The top left view shows nine mirrors. The top right view shows the central mirror removed to expose the underlying, hidden-hinge structure. The bottom right shows a close-up view of the mirror substructure. The mirror post, which connects to the mirror, sits directly on the center of this underlying surface. Lastly the bottom left view shows several pixels with the mirror removed.
(continued) Page 0-06
DLP-1 Chassis DLP Basics
DMDTM Size Comparisons Micrographic photos of the tip of a pin, an ant's leg, and one granule of salt on the surface of a DMD. Each mirror is 16 µm2 with 1 µm separation between pixels.
Page 0-07
DLP-1 CHASSIS Front & Rear Panels
55DM X01W Front Panel
DLP-1 Chassis Controls and Connections
POW ER LAMP TEMP POW ER
HITACHI
DO L B Y D I G I T A L
TM
D LP
A T EX A S IN S TR U M E N TS TE C H N O LO G Y
PUSH
POW ER LAMP TEMP POW ER
HITACHI
DO L B Y D I G I T A L
D LP
TM
A T EX A S IN S TR U M E N TS TE C H N O LO G Y
AUDIO/ PC AUDIO S-VIDEO VIDEO L/(MO NO) R
INPUT 2 INPUT TV/PC EXIT MENU SELECT VOL- VOL+ CHCH+
INPUT 3
PC RG B INPUT 2
(continued)
Page i-01
DLP-1 Chassis Controls and Connections
55DM X01W Rear Panel
AN T A S-VIDEO S-VIDEO S-VIDEO
L
R
VIDEO Y VIDEO Y VIDEO
PC AUDIO INPUT 1
(MO NO) L SUB W OOFER + R Pr R AU DIO AU DIO Pb (MO NO) L Pr R Pb (MO NO) L
TO CON VER TER
PC RGB INP UT 1
AN T B
L
L
AU DIO
R
R AU DIO TO H IFI
COAXIAL OPTICAL INPUT INPUT
+ -
INPUT 1
INPUT 2
M ONITOR OUT
REAR SP EAKER 8 ONLY
(continued)
Page i-02
55DMX01W Rear View
DLP-1 Chassis Controls and Connections
AN T A S -V ID E O S -V ID E O S -V ID E O
L
R
V ID E O Y V ID E O Y V ID E O
PC AUDIO INPUT 1
(M O N O ) L SUB W OOFER Pb (M O N O ) L Pb (M O N O ) L
TO C ON VER T ER
PC RGB INPUT 1
+
R
Pr R AU D IO
Pr R AU D IO
AN T B
L
L
AU D IO
R
R AU D IO T O H IF I + -
C O AX I AL IN P U T
O P TIC A L IN P U T
INPUT 1
INPUT 2
MONITOR OUT
REAR SPEAKER 8 ONLY
Page i-03
55DMX01W PW B Layout
DLP-1 Chassis Controls and Connections
POW ER PW B SURROUND PW B M ICON PW B
DSP UNIT
SIGNAL PW B
2H PW B UY01 UF01 U201
Tuner PW B
U202
Page i-04
TERM INAL PW B
DLP-1 Chassis Power Distribution
DLP-1 Chassis Power Distribution
POWER PWB
When AC is applied, the Switched Mode Power Supply (A) circuit consisting of I901 and T901 (see Figure 1) will start producing the following DC voltages: +13V, +18V, -15V, and +42V. When the unit is turned on, the power relay contacts close, and AC will be applied to the Switched Mode Power Supply (B) circuit consisting of I902 and T902 (see Figure 2), which will then produce the following DC voltages: +370V, +28V, +12V, and +8V.
PO W ER PW B
2
FAN +12V
2
FAN +12V
2
FAN +12V
P Q F1
P Q F2
P Q F3
I9 54 F an +12 V
I9 55 F an +12 V I9 51 S tb y + 5V
I9 56 F an +12 V
5 1
S TB Y +5V S TB Y +13V
AC IN
I9 52 B S +2.5V +1 3V
PMQ
(T o M IC O N P W B )
3 1
S TB Y +13V AUD +12V B S + 2 .5 V + 18 V V T + 3 5V B S + 6 .5 V
+1 8V I9 53 B S +6.5V I9 57 A u d +1 2V -15 V
Q 9E 3 -12V
7 9 11 5
I901& T 901 S M P S (A)
PSQ1
(T o S IG N A L P W B )
5 6 1 3
B S + 6 .5 V B S + 6 .5 V AUD +12V A U D -1 2 V
PQU2
(T o A U D IO P W B )
+4 2V
T o S M P S (B )
Q 9F 0 + 35V
Figure 1 - Switched Mode Power Supply (A)
SMPS (A) (See Figure 1)
+13V The +13 volt supply is the source for several lower supply voltages: I954 Fan +12V Regulator IC I955 Fan +12V Regulator IC I956 Fan +12V Regulator IC I951 STBY +5V Regulator IC I952 BS +2.5V Regulator IC It is also sent directly out to the SIGNAL PWB via connector PSQ1[3], and to the MICON PWB via connector PMQ[1], where it is then called STBY +13V. +18V The +18 volt supply is the source for several lower supply voltages: I953 BS +6.5V Regulator IC I957 AUD +12V Regulator IC It is also sent directly out to the SIGNAL PWB via connector PSQ1[9]. -15V The 15 volt supply is the source for the AUD 12V supply regulated by Q9E3. +42V The +42 volt supply is the source for the VT+35V supply regulated by Q9F0. FAN +12V Supply (I954, I955, I956) The FAN +12V supplies are supplied by the +13V source from T901 and are regulated by I954, I955, and I956, and then sent out to the Fans via connectors PQF1[2], PQF2[2], and PQF3[2]. (continued) Page 1-01
DLP-1 Chassis Power Distribution
STBY +5V Supply (I951) The STBY +5V supply is supplied by the +13V source from T901 and is regulated by I951 and is sent out to the MICON PWB via connector PMQ[5]. BS +2.5V Supply (I952) The BS +2.5V supply is supplied by the +13V source from T901 and is regulated by I952 and is sent out to the SIGNAL PWB via connector PSQ1[7]. BS +6.5V Supply (I953) The BS +6.5V supply is supplied by the +18V source from T901 and is regulated by I953 and is sent out to the SIGNAL PWB via connector PSQ1[5] and the AUDIO PWB via connector PQU2[5,6]. AUD +12V Supply (I957) The AUD +12V supply is supplied by the +18V source from T901 and is regulated by I957 and is sent out to the SIGNAL PWB via connector PSQ1[1] and the AUDIO PWB via connector PQU2[1]. AUD -12V Supply (Q9E3) The AUD -12V supply is supplied by the -15V source from T901 and is regulated by Q9E3 and is sent out to the AUDIO PWB via connector PQU2[3]. VT +35V Supply (Q9F0) The VT +35V supply is supplied by the +42V source from T901 and is regulated by Q9F0 and is sent out to the SIGNAL PWB via connector PSQ1[11].
To S M P S (A)
+28V
IA0 1
Fron t A ud io Out
5 6
A +2 8 V A +2 8 V
PQU1
(T o A U D IO PW B )
+12V
13 15
+ 12 V B + 8V B
I902& T 90 2 S M P S (B )
I962 M SC +9V
Q 959 + 3.3V
PSQ1
(T o S IG N AL PW B )
8 7 6 6 9
D LP + 3 .3 V D LP + 3 .3 V D LP + 3 .3 V D LP + 1 2V D LP + 5 V
+8V I959 D L P +5V I960 M SC +3.3V I961 M SC +5V
PQD
(T o D LP PW B )
10 6 5 4 12 10
M S C + 9V M S C + 3.3V M S C + 3.3V M S C + 3.3V M S C + 5V M S C + 5V
1
La m p +3 7 0V
PQL
(T o L a m p B a lla s t PW B )
PBQ2
PO W ER PW B
(T o M S C PW B )
Figure 2 - Switched Mode Power Supply (B)
SMPS (B) (See Figure 2)
+28V The +28 volt supply is sent directly out to the AUDIO PWB via connector PQU1[5,6], where it is then called A+28V. It is also applied to IA01 which is the Front Audio Output IC. +12V The +12 volt supply is the source for several lower supply voltages: I962 MSC +9V Regulator IC Q959 3.3V Regulator Transistor It is also sent directly out to the SIGNAL PWB via connector PSQ1[13] where it is then called +12VB, and out to the DLP PWB via connector PQD[10] where it is then called DLP +12V. (continued) Page 1-02
DLP-1 Chassis Power Distribution
+8V The +8 volt supply is the source for several lower supply voltages: I959 DLP +5V Regulator IC I960 MSC +3.3V Regulator IC I961 MSC +5V Regulator IC It is also sent directly out to the SIGNAL PWB via connector PSQ1[15], where it is then called +8VB. +370 Volt Supply (Unregulated) The +370V supply is basically raw B+ and sent to the Lamp Ballast PWB via connector PQL[1]. MSC +9V Supply (I962) The MSC +9V supply is supplied by the +12V source from T902 and is regulated by I962 and is sent out to the MSC PWB via connector PBQ2[14]. DLP +3.3V Supply (Q959) The DLP +3.3V supply is supplied by the +12V source from T902 and is regulated by Q959 and is sent out to the DLP PWB via connector PQD[6,7,8]. DLP +5V Supply (I959) The DLP +5V supply is supplied by the +8V source from T902 and is regulated by I959 and is sent out to the DLP PWB via connector PQD[9]. MSC +3.3V Supply (I960) The MSC +3.3V supply is supplied by the +8V source from T902 and is regulated by I960 and is sent out to the MSC PWB via connector PBQ2[4,5,6]. MSC +5V Supply (I961) The MSC +5V supply is supplied by the +8V source from T902 and is regulated by I961 and is sent out to the MSC PWB via connector PBQ2[10,12].
A U D + 9V S T B Y + 5V S T B Y + 3.3V
1 3 5 4
S T B Y + 5V
PSM1
(T o S IG N A L P W B )
PMR1
(T o C O N T R O L P W B )
S T B Y + 5V S T B Y + 3.3V
1 3 3
S T B Y + 3.3V
PMJ
(T o R E M O T E P W B )
PME
(T o C .W . S E N S O R P W B )
S T B Y + 5V S T B Y + 13V
5 1
S T B Y + 13V
Q 029 +3.3V
6
A U D + 9V S E L + 9V + 5V 1H
S E L + 9V + 5V 1H
8 18
PMQ
(F ro m P O W E R P W B )
S T B Y + 5V S T B Y + 3.3V
PSM3
(F ro m S IG N A L P W B )
M ICO N PW B
Figure 3 - MICON PWB
MICON PWB (See Figure 3)
STBY +3.3V Supply (Q029) The STBY +3.3V supply is supplied by the STBY +5V source on the POWER PWB and is regulated by Q029 and is used on the MICON PWB. It is also sent out to the REMOTE PWB via connector PMJ[3], the CONTROL PWB via connector PMR1[5], and the C.W. SENSOR PWB via connector PME[3].
(continued) Page 1-03
DLP-1 Chassis Power Distribution
AU D +12V 1 S TB Y +13V 3 B S +6.5V 5 B S +2.5V 7 +18V 9 V T +35V 1 1 +12V B 1 3 +8V B 1 5 P SQ 1
(F ro m P O W E R P W B )
B S + 2.5V V T + 35V + 12V B + 8V B
IP 0 6 AUD+9V IP 0 7 SE L+9V IP 0 8 9VFC1H IP 0 9 9VFC2H IP 1 0 12V2H IP 1 1 5VFC
AU D +9V
S E L +9V
2 4 6 8
IP 0 1 5V1H IP 0 2 5V2H IP 0 3 5V3D IP 0 4 9V1H IP 0 5 9V2H
5V 1H
9V F C 1H
5V 2H
9V F C 2H
P SB 1
(T o T U N E R P W B )
5V 3D
12V 2H
9V 1H
5V F C
9V 2H
IP 1 2 3 .3 V F C
3.3V F C
SIG NAL PW B Figure 4 - SIGNAL PWB
SIGNAL PWB (See Figure 4)
5V1H Supply (IP01) The 5V1H is a +5 volt supply which is supplied by the +8VB supply on the POWER PWB, which is then regulated by IP01. It is made available to the 1H video circuitry on the SIGNAL PWB. 5V2H Supply (IP02) The 5V2H is a +5 volt supply which is supplied by the +8VB supply on the POWER PWB, which is then regulated by IP02. It is made available to the 2H video circuitry on the SIGNAL PWB. 5V3D Supply (IP03) The 5V3D is a +5 volt supply which is supplied by the +8VB supply on the POWER PWB, which is then regulated by IP03. It is made available to the 3DYC comb filter circuitry on the SIGNAL PWB. 9V1H Supply (IP04) The 9V1H is a +9 volt supply which is supplied by the +12VB supply on the POWER PWB, which is then regulated by IP04. It is made available to the 1H video circuitry on the SIGNAL PWB. 9V2H Supply (IP05) The 9V2H is a +9 volt supply which is supplied by the +12VB supply on the POWER PWB, which is then regulated by IP05. It is made available to the 2H video circuitry on the SIGNAL PWB. AUD+9V Supply (IP06) The AUD+9V is a +9 volt supply which is supplied by the AUD+12V supply on the POWER PWB, which is then regulated by IP06. It is made available to the audio circuitry on the SIGNAL PWB. SEL+9V Supply (IP07) The SEL+9V is a +9 volt supply which is supplied by the STBY+13V supply on the POWER PWB, which is then regulated by IP07. It is made available to various circuitry on the SIGNAL PWB. (continued) Page 1-04
DLP-1 Chassis Power Distribution
9VFC1H Supply (IP08) The 9VFC1H is a +9 volt supply which is supplied by the STBY+13V supply on the POWER PWB, which is then regulated by IP08. It is made available to the Flex Converter (1H portion) on the SIGNAL PWB. 9VFC2H Supply (IP09) The 9VFC2H is a +9 volt supply which is supplied by the STBY+13V supply on the POWER PWB, which is then regulated by IP09. It is made available to the Flex Converter (2H portion) on the SIGNAL PWB. 12V2H Supply (IP10) The 12V2H is a +12 volt supply which is supplied by the +18V supply on the POWER PWB, which is then regulated by IP10. It is made available to the 2H video circuitry on the SIGNAL PWB. 5VFC Supply (IP11) The 5VFC is a +5 volt supply which is supplied by the BS+6.5V supply on the POWER PWB, which is then regulated by IP11. It is made available to the Flex Converter circuitry on the SIGNAL PWB. 3.3VFC Supply (IP12) The 3.3VFC is a +3.3 volt supply which is supplied by the 5VFC supply on the SIGNAL PWB, which is then regulated by IP12. It is made available to the Flex Converter circuitry on the SIGNAL PWB.
V T+35V +12V B +12V B +8V B
(F ro m S IG N A L P W B )
2 4 6 8
I201 +9V R eg I202 +9V R eg I203 +5V R eg
3
1 9 2 3
PSB1
U 201 M ain T u n er U 202 Sub T u n er
10 7 11
TUNER PW B
Figure 5 - TUNER PWB
EBA
(T o A n t S w B o x )
TUNER PWB (See Figure 5)
+9V Supply (I201) This +9V is a +9 volt supply which is supplied by the +12VB supply on the POWER PWB, which is then regulated by I201. It is made available to the two tuners on the TUNER PWB. +9V Supply (I202) This +9V is a +9 volt supply which is supplied by the +12VB supply on the POWER PWB, which is then regulated by I202. It is made available to the Antenna Switch Box via connector EBA [3]. +5V Supply (I203) This +5V is a +5 volt supply which is supplied by the +8VB supply on the POWER PWB, which is then regulated by I203. It is made available to the two tuners on the TUNER PWB.
(continued) Page 1-05
DLP-1 Chassis Power Distribution
AUDIO PWB (See Figure 6)
AUD+5V Supply (IS13) The AUD+5V is a +5 volt supply which is supplied by the BS +6.5V supply on the POWER PWB, which is then regulated by IS13. It is made available to the audio circuitry on the AUDIO PWB and also to the DSP (Digital Surround Processor) Module via connector PMU1[1].
AU D +9V
(F ro m S IG N A L P W B )
1
AU D +9V
9 8
PSU1
AU D +12V AU D -12V B S +6.5V B S +6.5V
(F ro m P O W E R P W B )
1 3 5 6
AU D +12V AU D -12V
PMU3
(T o D S P M o d u le )
IS 13 AU D +5V IS 15 C en ter O u t IS 16 R ear O u t
AU D +5V
1
PQU2
PMU1
(T o D S P M o d u le ) 5 6
A+28V A+28V
(F ro m P O W E R P W B )
PQU1
AUDIO PW B
Figure 6 - AUDIO PWB
Page 1-06
DLP 55DMX01W POWER ON/OFF CIRCUIT DIAGRAM (Microprocessor Side)
MICON PWB STBY 13V Q050
OFF
STBY 3.3V
ON
OFF
PWR
8 PMR1
Q014
7
KEY IN PWR On/Off 53
ON OFF
Q049
Q052
ON
Power1
7
ON OFF OFF ON
CONTROL PWB
To POWER PWB
8
45 DATA
Q051 Q020
Power2 9 Power2
PMQ
STBY 5V HR01
5 PMJ 1
IR IN
µprocessor
REMOTE PWB
I001
Temp Alarm Fan Alarm Lamp Cover CDBRK
PAGE 01-07
DLP 55DMX01W POWER ON/OFF CIRCUIT DIAGRAM (Microprocessor Side)
S901 AF 29V STBY 18V 5 STBY 5V TV S Power 1 OFF Q9F7 ON 8 TV V Power1 BS Power Q9F6 9 Power2 PMQ STBY 5V S902 STBY 5V AC Q9E3 AC to SMPS-B STBY 18V 1 5 I953 BS 6.5V 3 2 4 BS +6.5V 2 Q9E4 I957 Aud +12V 1 STBY 13V 5 2 I955 Fan +12V 1 STBY 13V 5 2 I954 Fan +12V 1 3 4 FAN1 +12V 3 4 3 4 Audio +12V PSQ1 1 To Surround PWB 1 Audio (Front) 29V To Signal PWB
PQU2 FAN2 +12V
Power 1 From MICON PWB Power2
7
STBY 13V 1 5 Q9E2 I952 BS 2.5V 3 2 4
BS +2.5V
PAGE 01-08
DLP-1 Chassis Video Circuit Explanation
DLP-1 Chassis Video Circuit Explanation
(See Figure 1 on Page 2-04) TERMINAL PWB
The TERMINAL PWB is where most of the video inputs come into and go out of. The main components on this PWB are I301 (A/V Select IC) and IT01 (PiP 3-Line Comb Filter). I301 (A/V Select) This IC receives the following video inputs: TV1 Main Tuner video (NTSC) TV2 Sub Tuner video (NTSC) V1 Composite video from AUX VIDEO INPUT 1 V1(Y) Luminance portion of S-Video from AUX VIDEO INPUT 1 V1(C) Chrominance portion of S-Video from AUX VIDEO INPUT 1 Comp 1 Y Luminance portion of Component Video from AUX VIDEO INPUT 1 V2 Composite video from AUX VIDEO INPUT 2 V2(Y) Luminance portion of S-Video from AUX VIDEO INPUT 2 V2(C) Chrominance portion of S-Video from AUX VIDEO INPUT 2 Comp 2 Y Luminance portion of Component Video from AUX VIDEO INPUT 2 V3 Composite video from AUX VIDEO INPUT 3 via the front panel connector PTR V3(Y) Luminance portion of S-Video from AUX VIDEO INPUT 3 via the front panel connector PTR V3(C) Chrominance portion of S-Video from AUX VIDEO INPUT 3 via the front panel connector PTR Y In1 Luminance portion of Sub Video from IT01 PiP Comb Filter C In1 Chrominance portion of Sub Video from IT01 PiP Comb Filter This IC also provides the following outputs: V Out1 Sub Video out which is sent to IT01 PiP Comb Filter V/Y Out2 Main Video out or Luminance portion of main S-video which is sent to the SIGNAL PWB C Out2 Chrominance portion of main S-video which is sent to the SIGNAL PWB Mon Out V Composite video sent to MONITOR OUTPUT Mon Out (Y) Luminance portion of S-Video sent to MONITOR OUT Mon Out (C) Chrominance portion of S-Video sent to MONITOR OUT IT01 (PiP 3-Line Comb Filter) This IC receives Sub Video from I301 on pin 3. It outputs Sub Y on pin 25 and Sub C on pin 23.
TUNER PWB
The TUNER PWB is where the two tuners are located. The main components on this PWB are U101 (Main Tuner) and U102 (Sub Tuner). U101 (Main Tuner) This non-repairable unit outputs Main Tuner NTSC Video to connector PSB5[4], where it goes to the SIGNAL PWB, then to the TERMINAL PWB on connector PST1[4]. U102 (Sub Tuner) This non-repairable unit outputs Sub Tuner NTSC Video to connector PSB5[10], where it goes to the SIGNAL PWB, then to the TERMINAL PWB on connector PST1[10].
SIGNAL PWB
The SIGNAL PWB receives and processes the following signals: Sub (Y / C) Main (V or Y / C) Component 1 (Y/Cr/Cb or Y/Pr/Pb) Component 2 (Y/Cr/Cb or Y/Pr/Pb)
(continued) Page 2-01
DLP-1 Chassis Video Circuit Explanation
Sub Video The Sub Y and Sub C signals are applied to IY02, which basically converts the Sub C (chrominance) signal into two color difference signals, which are called Sub R-Y or Sub Cr and Sub B-Y or Sub Cb. It then outputs all three signals to IX01, which is the Y/CR/CB Select IC. Main Video The Main video signal, whether it's V or Y / C, is applied to UY01 3DYC Comb Filter. If the Main video wasn't Y / C when it came in, it will be when it comes out. Main Y and Main C signals are applied to IY01 which basically converts the Main C (chrominance) signal into two color difference signals, which are called Main R-Y or Main Cr and Main B-Y or Main Cb. It then outputs all three signals to IX01 which is the Y/CR/CB Select IC. Component 1 The component 1 video signal can be any of the approved ATSC or NTSC formats; 480i, 480p, 1080i, etc. This signal is inserted directly into IX01 which is the Y/CR/CB Select IC. Component 2 The component 2 video signal can be any of the approved ATSC or NTSC formats; 480i, 480p, 1080i, etc. This signal is inserted directly into IX01 which is the Y/CR/CB Select IC. IX01 (Y/CR/CB Select IC) This IC receives four different inputs, Sub (Y/Cr/Cb), Main (Y/Cr/Cb), Component 1 (Y/Cr/Cb or Y/Pr/Pb), and Component 2 (Y/Cr/Cb or Y/Pr/Pb). Note that since both the Sub and Main signals ultimately come from NTSC sources, it is not possible for them to be Y/Pr/Pb. IX01 provides two outputs; Main and Sub, which are then applied to UF01, which is the Picture in Picture / Flex Converter Unit. UF01 (Picture in Picture / Flex Converter Unit) The Picture in Picture / Flex Converter Unit receives two inputs, Main and Sub, and provides one combined or processed output. If any PiP request is made by the customer, it will combine/split the two signals into one signal as long as both of the input signals contain the same original format; i.e. 480i, 480p, etc. It will also up-convert the frequency (base H) of incoming 15.734 KHz to approximately 2.86H or 45 KHz or 720p.
2H VIDEO PWB
The 2H VIDEO PWB receives and processes the following signals: PiP/Flex Converter Output (2H Y/Cr/Cb) Main Output from IX01 Rear PC RGB Front PC RGB PiP/Flex Converter Output As previously mentioned, the PiP/Flex Converter output sends out a processed signal (PiP information added) that is (possibly) as high as 45 KHz located on connector PSH1[9,11,13]. Also found on that same connector [2,4,6] is a set of signals that mirror the main input to the PiP/Flex Converter. This set of signals will be used in the case of a non-480i (480p, 1080i, etc.) input via the component 1 or component 2 inputs, and is applied to I501. 2H Y/Cr/Cb The Y portion of the 2H Y/Cr/Cb is sent directly to I501. The 2H Cr/Cb is sent to two places; I502 and the YCBCR/YIQ converter circuitry. YCRCB/YIQ Converter The purpose of the YCRCB/YIQ Converter circuitry is to phase shift the color information contained in the YCRCB signal by 33 degrees. This is done so that the auto-flesh tone or auto-color circuitry in IK01 RGB processor can function properly. The auto-color function only works with YIQ signals, so the output from the Flex Converter must be converted (phase shifted) if the original signal was NTSC. The Cr/Cb signal can also be termed U/V. The phase shifted signal is then applied to I502. (continued) Page 2-02
DLP-1 Chassis Video Circuit Explanation
I502 (NTSC/Other Select IC) I502 receives two sets of red and blue color difference information; one in the form of Cr/Cb or U/V and the other in the form of I/Q. Selection is made by the sensing of NTSC or non-NTSC. If NTSC is sensed, then the I/Q input would be selected. The output is sent to I501. I501 (15.75 KHz / Other Select IC) This IC receives two sets of signals; one directly from the output of IX01 (main out) via connector PSH1[2,4,6] and the other from I502 NTSC/Other Select IC. In the case of an input signal other than 480i, or 15.75 KHz, the Flex Converter does not need to up-convert the signal, so this signal is sent directly to I501 as this will typically be a high(er) definition source such as 1080i. The other signal available to I501 will be the processed signal from I502 via the Flex Converter and phase shifted if necessary. Selection is made by the sensing of a non-15.75 KHz input signal. The output is sent to IK01 RGB Processor in the form of Y/I/Q or Y/U/V. IK01 (RGB Processor) This IC receives two sets of inputs; one from the output of I501 which would be video, and the other from the MICOM PWB in the form of OSD R, OSD G, and OSD B. It processes and combines the two signals (when applicable) and outputs main RGB to IC02, which is the TV / PC Select IC. IC01 (Front / Rear PC Select) This IC receives two sets of PC RGB signals; one from the front panel via connector PHR[1,3,5] and the other from the TERMINAL PWB via connector PHT[1,3,5]. The IC then selects whichever one the customer selects via the main control menu. The output is sent to IC02, which is the TV / PC Select IC. IC02 (TV / PC Select IC) This IC receives two sets of signals; one which is main video from the RGB processor IC IK01, and the other from the Front / Rear PC Select IC IC01. The output is sent to the MSC PWB in the form of RGB. MSC PWB This PWB is located physically on the Optical Engine Assembly. Nothing is known about what goes on inside this module, although there appears to be an output which consists of a flat 50 pin cable which includes signals called A0-LVTTL, A1-LVTTL, B2-LVTTL, C3-LVTTL, etc., which may possibly stand for Low-Voltage-TransistorTransistor-Logic, since there is a 3.3 volt power source sent to this PWB. DLP PWB This PWB is also located physically on the Optical Engine Assembly. Nothing is known about what goes on inside this module either, although this is where the actual Micro-Mirror-Device is located.
(continued) Page 2-03
V O ut1 Y In1 60 T V1 C In1 51 23 49 25
53
3
U101 Tuner M ain
4
4
IT01 PiP 3-Line
DLP-1 Chassis Video Block Diagram
Sub Y Sub C 6 37 SUB Y (NT SC) 5 40 47 7 SUB Cb (NT SC) 48 9 SUB Cr (NT SC)
Figure 1
U102 Tuner PiP
63 T V2 Y O ut1 C O ut1 58 8 56 6
10
10
SIG NAL PW B IX01 Y/CB/CR Select
PSB5
PST1
TUNER PW B
UY01 3DYC
V/Y O ut2 15 V1 V1(Y) 7 37 63 61 59 CO MP 1 (Y) CO MP 2 (Cr/Pr) CO MP 2 (Cb/Pb) CO MP 2 (Y) (Cr/Pr) MAIN O UT (Cb/Pb) MAIN O UT (Y) MAIN O UT 46 48 50 57 55 53 CO MP 1 (Cb/Pb) CO MP 1 (Cr/Pr) 15 MAIN Y (NT SC) CO MP 1 (Cr/Pr) CO MP 1 (Cb/Pb) CO MP 1 (Y) CO MP 2 (Cr/Pr) CO MP 2 (Cb/Pb) CO MP 2 (Y) 6 V1(C) 30 28 30 23 21 19 Com p 1 Y 26 17 19 C O ut2 47 4 13 9 Main C 47 MAIN Cb (NT SC) 17 Main Y 40 48 19 MAIN Cr (NT SC) (Cr/Pr) SUB O UT (Cb/Pb) SUB O UT (Y) SUB O UT 34 36 38 44 2 11
IY02 SUB NTSC
Video 1
UF01 PiP/FC Unit
19 18 17
S-Video 1 (Y)
PST2
S-Video 1 (C)
IY01 M AIN NTSC
Com p Video 1 (Cr/Pr)
Com p Video 1 (Y)
Com p Video 1 (Cb/Pb)
5 4 3
I301 A/V Select
PST1
8 10 V2(Y) V2(C) 1 5 3 6 3 11 Com p 2 Y 16 9 3 5 1 14 12 8 V2
PFC1
Video 2
S-Video 2 (Y)
(Y) MAIN O UT (Cb/Pb) MAIN O UT (Cr/Pr) MAIN O UT 2H Y 2H CB 2H CR
S-Video 2 (C)
2 4 6 9 11 13 I 16 Q 16 18 20
Com p Video 2 (Cr/Pr)
I501 15.75 Khz/Other Select
Com p Video 2 (Y)
Com p Video 2 (Cb/Pb) 53 Y U/Q V/I O SDR O SDG O SDB 52 22 39 38 37 V3 51
I502 14 NTSC/Other 11 Select
YCBCR/YIQ CONVERTER
PSH1
PFC2
Video 3
10
IK01 RGB Processor
R O UT G O UT B O UT 43 42 41
S-Video 3 (Y) 24 26 V3(C) V3(Y)
S-Video 3 (C)
5
3
From MICO N PW B
PTR
1 3 5 G B R 1 2 4 R 3 8 1 G 12 5 7 41 39 Mon O ut (Y) Mon O ut (C) 37 Mon O ut V 1 3 5 R G B 8 6 5 29 R 1 G 23
1 to 50 3
1 to 50
PC Front
1
R
3
G
5
B
FRO NT PANEL
PHR
PHT
M SC - DLP 50 Pin LVTTL
9 B 10 3 26 B 5
Monitor O ut (Video)
PHC
Monitor O ut (S-Video) (Y)
Page 2-04
Page 2-04
Monitor O ut (S-Video) (C)
IC01 Front/Rear PC Select
PHR
IC02 TV/PC Select
MSC PW B 2H VIDEO PW B
DLP PW B O PTICAL ENG INE A SSY
PC Rear
TERMINAL PW B
DLP-1 Chassis Audio Circuit Explanation
DLP-1 Chassis Audio Circuit Explanation
(See Figure 1 on Page 3-04) TERMINAL PWB
The TERMINAL PWB is where the analog audio inputs come into. The main components on this PWB are I301 (A/V Select IC) and I302 (Audio Switch IC). I301 (A/V Select) This IC receives the following audio inputs: TV1(L) Main Tuner audio (Left) TV1(R) Main Tuner audio (Right) V1(L) Left Channel audio from AUX VIDEO INPUT 1 V1(R) Right Channel audio from AUX VIDEO INPUT 1 V2(L) Left Channel audio from AUX VIDEO INPUT 2 V2(R) Right Channel audio from AUX VIDEO INPUT 2 V3(L) Left Channel audio from AUX VIDEO INPUT 3 via Audio Switch IC I302 V3(R) Right Channel audio from AUX VIDEO INPUT 3 via Audio Switch IC I302 This IC also provides the following outputs: SEL (L) Selected Left Channel Audio which is sent to the SURROUND PWB SEL (R) Selected Right Channel Audio which is sent to the SURROUND PWB Mon Out (L) Selected Left Channel Audio which is sent to MONITOR OUTPUT Mon Out (R) Selected Right Channel Audio which is sent to MONITOR OUTPUT I302 (Audio Switch IC) This IC receives two sets of left and right audio input; one set from the front panel which is Aux Video 3 / PC, and one set from the rear PC audio input. It has one set of left and right audio output which is sent to the V3(L) and (R) inputs on I301. It is controlled by the PC F/R signal.
SURROUND PWB
The SURROUND PWB receives and processes the following signals: SEL (L) and (R) Digital Audio via Optical Input Digital Audio via Coaxial Input The SURROUND PWB processes and outputs the following signals: Front Audio (L) and (R) Rear Audio (L) and (R) Center Channel Subwoofer (LFE) HiFi Outputs (L) and (R)
SURROUND PWB INPUTS
SEL (L) and (R) The SEL (L) and (R) signals are the selected output from I301 (A/V Select IC) and are input to IS19 (Perfect Volume IC) via connector PSU1[12,13]. The output of IS19 is then divided and sent to two places; IS03 (Front Audio Control IC), and to the DSP (Digital Signal Processor) module via connector PMU2[1,3]. Digital Audio Input (Optical) The Digital Audio Input (optical) is a fiber optic connection which is coupled to a transducer which converts the digital audio data via light pulses to an electrical signal, in fact very similar in operation to an Infra-Red remote receiver. It is widely regarded as inferior to coaxial digital connections. Also known as an "optical" or "Toslink" connection. After this signal has been converted, it is sent to IS17 (Digital Audio Selector IC).
(continued) Page 3-01
DLP-1 Chassis Audio Circuit Explanation
Digital Audio Input (Coaxial) An RCA type cable with a central conductor surrounded by an insulating material, around which is another tubular conductor (known as the screen or shield). In digital audio, the coaxial cable yields better results than Toslink (optical) due to its higher quality connection and wider signal bandwidth. This signal is sent through a buffer stage IS18 (Coaxial Buffer IC) before going into IS17 (Digital Audio Selector IC). IS17 (Digital Audio Selector IC) This IC receives both the optical and coaxial sources of digital audio and selects which one is sent to the DSP (Digital Signal Processor) module as an input. DSP (Digital Signal Processor) Module This module is a separate PWB that is mounted piggyback on the SURROUND PWB. It receives Left and Right audio in from the Perfect Volume IC and creates the following outputs; Front Right, Front Left, Rear Right, Rear Left, Center Channel, and Subwoofer. It also is capable of receiving and processing a digital audio input signal, via either coaxial or optical inputs.
SURROUND PWB OUTPUTS
Front Audio (L) and (R) The Front Audio left and right consist of the following components; IS03 (Front Audio Control IC), IS05 (Front Audio Graphic Equalizer IC), and IA01 (Front Audio Output IC). IS03 (Front Audio Control IC) This IC receives two sets of left and right audio; one set is the non-DSP processed left and right input from I301 (A/V Select IC) via IS19 (Perfect Volume IC), and the other set which has been processed by the DSP module. The output of IS03 is sent to IS05 (Front Audio Graphic Equalizer IC). IS05 (Front Audio Graphic Equalizer IC) This IC receives the Front Audio left and right from IS03 (Front Audio Control IC) and provides the user with five frequency ranges or bands which he can manipulate by approximately 12db in both the plus and minus directions. The frequency bands are 60 Hz, 125 Hz, 1 KHz, 3 KHz, and 10 KHz. The outputs from this IC are sent to two places; IA01 (Front Audio Output IC) via connector PQU3[2,4], and also to the HiFi Output jacks located on the rear of the SURROUND PWB. IA01 (Front Audio Output IC) This IC is not located on the SURROUND PWB but on the POWER PWB as previously discussed on page 1-02. It is a standard TA8200AH audio output IC. The outputs from this IC are sent to the two front speakers via connectors PL[2] and PR[2]. Rear Audio (L) and (R) The Rear Audio left and right consist of the following components; IS11 (Rear Audio Control IC), and IS16 (Rear Audio Output IC). IS11 (Rear Audio Control IC) This IC receives Rear Audio left and right which has been processed by the DSP module. The outputs of IS11 are sent to IS16 (Rear Audio Graphic Equalizer IC). IS16 (Rear Audio Output IC) This IC is also a standard TA8200AH audio output IC. It outputs speaker level audio to the Rear Speaker jacks located on the rear of the SURROUND PWB.
(continued) Page 3-02
DLP-1 Chassis Audio Circuit Explanation
Center Channel Audio (Monaural) The Center Channel Audio consists of the following components; IS08 (Center/Subwoofer Audio Control IC), IS10 (Center Channel Audio Graphic Equalizer IC), and IS15 (Center Channel Audio Output IC). IS08 (Center Channel / Subwoofer Audio Control IC) This IC receives Center Channel Audio which has been processed by the DSP module. The Center Channel Audio output of IS08 is sent to IS10 (Center Channel Audio Graphic Equalizer IC). IS10 (Center Channel Audio Graphic Equalizer IC) This IC receives the Center Channel Audio from IS08 (Center Channel / Subwoofer Audio Control IC) and provides the user with five frequency ranges or bands which he can manipulate by approximately 12db in both the plus and minus directions. The frequency bands are 60 Hz, 125 Hz, 1 KHz, 3 KHz, and 10 KHz. The Center Channel Audio output from this IC is sent to IS15 (Center Channel Audio Output IC). IS15 (Center Channel Audio Output IC) This IC is also a standard TA8200AH audio output IC. It outputs speaker level audio to the center speaker via connector PCL[2]. Subwoofer Audio (LFE) The Subwoofer Audio (Low Frequency Effects) consists of IS08 (Center/Subwoofer Audio Control IC). IS08 (Center Channel / Subwoofer Audio Control IC) This IC receives Subwoofer (LFE) Audio which has been processed by the DSP module. The Subwoofer (LFE) audio output of IS08 is sent to the Subwoofer connector on the rear of the SURROUND PWB.
(continued) Page 3-03
DLP-1 Chassis Audio Block Diagram
Figure 1
T V1(L) T V1(R) SEL (L) SEL (R) PST2 In(FL) In(FR) PQU3 V1(L) PSU1 28 In(R) In(R) O ut(FR) 2 O ut(FR) In(FR) O ut(FR) In(FR) 12 O ut(R) O ut(FL) 4 In(FL) 27 13 In(L) O ut(L) In(L) O ut(FL) In(FL) O ut(FL) 2
1
1
SURROUND PWB
POWER PW B
U101 Tuner M ain
PL
2
2
2
PSB5
PST1
L R
PR
TUNER PW B IS19
Perfect Volume
Video 1 (Left)
Video 1 (Right) V1(R) 2 BUSY DIR ERR ERR MUT E ZRNSSN SO SI SCK RESET N V2(L) 4 6 8 10 V3(L) 14 PUM1 V3(R) 12 V2(R) 1
IS03
Front Audio Control Front Graphic EQ
IS05
IA01
Front Audio Out
Video 2 (Left)
Video 2 (Right)
Video 3 / PC (Left)
15
Video 3 / PC (Right)
16
I001
µ Processor
In(C) In(SW ) In(L) 1 3 PMU2 O ut(SW ) O ut(C) In(C) O ut(C) In(C) O ut(C) 2
Front Panel MICON PWB I301
A/V Select
13 BUSY DIR ERR ERR MUT E ZRNSSN SO SI SCK RESET N CSI REQ UEST 6 PMU1 O ut(FL) 1 2 5 6 3 4 PMU3 In(SL) In(SR) O ut(SL) O ut(SR) O ut(FR) O ut(C) O ut(SW ) O ut(SL) O ut(SR) 5 12 Mon Out (L) 10 Mon Out(R) 8 7 3 PMU1 9 11 In(R)
PST2
C
PCL
Rear PC (Left)
IS08
Rear PC (Right)
IS10
Center Graphic EQ
IS15
Center Audio Out
Monitor Out (Left)
Center/SW Audio Control
Monitor Out (Right)
I302
Audio SW
O ut(L) O ut(R) In1(L) In1(R) In2(L) In2(R)
IS01
DAC4
TERMINAL PWB
3 PMU4 In(Digital)
In(SL) In(SR)
O ut(SL) O ut(SR)
O ptical Input
Digital Audio In
IS17
Digital Audio Selector
IS11
Rear Audio Control
IS16
Rear Audio Out
IS18
CoAxial Input
CoAx Buffer
DSP MODULE
Surround Left Speaker O ut
Surround Right Speaker O ut
Page 3-04
SURROUND PWB
Page 3-04
Sub W oofer O ut
HiFi O ut (Left)
HiFi O ut (Right)
DLP-1 Chassis System Control Explanation
DLP-1 Chassis System Control Explanation
In the DLP-1 Chassis (Figure 10), as in many other Hitachi products, System Control starts at the microprocessor IC, I001. The following signals are generated by the microprocessor IC; (see Figure 1)
C lock
Clock/Data 0Clock/0Data 1Clock/1Data (also called SCL1 and SDA1) 2Clock/2Data (also called SCL2 and SDA2) M Enable - Main Tuner Enable P Enable - PiP Tuner Enable FC Enable - Flex Converter Enable MSC Enable - MultiScan Converter Enable
M E nable
D ata
0C lock P E nable 0D ata
I001 M icroP rocesso r
FC Enable
1C lock (SC L1) 1D ata (SD A 1)
2C lock (SC L2) M S C Enable 2D ata (SD A 2)
Figure 1 - System Control signals
Clock/Data Clock and data are fed to the following circuits: Main tuner, PiP tuner, Flex Converter, and the MSC (MultiScan Converter) PWB. Additionally, each of these circuits also requires an Enable signal whenever that circuit activates. (see Figures 2, 3, 4, and 5) Also, note that 0Clock/0Data is only sent to the MSC PWB.
M ain Tuner
C lo c k M E na ble D a ta M E na b le
C lo c k D a ta
0C lo ck P E n ab le 0D ata
I001 M icro P ro cesso r
F C E n ab le
P iP Tuner
0C lo ck P E n ab le 0D ata
1C lo ck (S C L 1) 1D ata (S D A 1) F C E n ab le
I001 M icro P ro cesso r
1C lo ck (S C L 1) 1D ata (S D A 1 )
2C lo ck (S C L 2) M S C E n ab le 2D ata (S D A 2) M S C E n ab le
2C lo ck (S C L 2) 2D ata (S D A 2 )
Figure 2 - Clock, Data, and Main Enable
Figure 3 - Clock, Data, and PiP Enable
C lo c k M E na ble D a ta
C lock M E nab le D ata
0C lo ck P E n ab le 0D ata
FC U nit
I001 M icro P ro cesso r
F C E n ab le
0C loc k P E na ble 0D ata
1C lo ck (S C L 1) 1D ata (S D A 1)
I0 01 M ic ro P ro ce sso r
1C loc k (SC L1 ) 1D ata (SD A1)
2C lo ck (S C L 2) M S C E n ab le 2D ata (S D A 2)
MSC U nit
FC En ab le
2C loc k (SC L2 ) M S C E nab le 2D ata (SD A2)
Figure 4 - Clock, Data, and Flex Converter Enable
Figure 5 - Clock, Data, 0Clock, 0Data, and MultiScan Converter Enable (continued) Page 4-01
DLP-1 Chassis System Control Explanation
1Clock/1Data (SCL1/SDA1) The clock and data 1 lines are fed to the following: I002 E2PROM, I004 DAC1, I003 DAC2, I017 DAC3, IS11 Rear Audio Control, and I301 A/V Select. (see Figure 6). The use of DAC's (Digital to Analog Converter) are basically configured as fan-out IC's for the microprocessor. (see Figure 7). This allows the microprocessor IC to remain as a standard dual inline 64 pin configuration as far as the actual IC manufacturing process is concerned. Each DAC can communicate up to nine (9) separate functions back to the main microprocessor. Including the three DAC's, the clock/data 1 line communicates to 30 different devices.
I0 0 2 EEPROM
Clock M E nable Data
I0 0 4 D AC 1
0Clock P E nable 0Data
I001 M icroP rocessor
FC Enable
I0 0 3 D AC 2
1Clock (SC L1) 1Data (S DA1)
I0 1 7 D AC 3
2Clock (SC L2) MSC Enable 2Data (S DA2)
IS 1 1 R e a r A u d io
I3 0 1 A/V S e le c t
Figure 6 - 1Clock, 1Data, (SCL1, SDA1)
YUV 1 DET YUV 2 DET CO MP SEL CHECK 2
IR D E T YV DET 0R E S MTS
L AM P M IS S F AN A L AR M 15 K /O T H E R P C /O T H E R
I0 0 4 D AC 1
L E D F AN L E D L AM P LED PW R L AM P E N A CDBRK
I0 0 3 D AC 2
F MONO AN T PW RG S AP D E T ST DET
I0 1 7 D AC 3
L AM P C T R L AM P L IT F AN O N T E M P AL AR M F IL T E R C O V E R
Figure 7 - DAC 1, DAC 2, and DAC 3 pin outs
(continued) Page 4-02
DLP-1 Chassis System Control Explanation
2Clock/2Data (SCL2/SDA2) The clock and data 2 lines are fed to the following: UY01 3DYC Comb Filter, IT01 PiP 3Line Comb Filter, IX01 Y/Cb/Cr Select, I018 DAC5, IS05 Front Graphic EQ, IY01 Main NTSC processor, IL01 Main Sync processor, IK01 RGB processor, IS01 DAC4, IS08 Center/Subwoofer Control, IY02 Sub NTSC processor, IL02 Sub Sync processor, DLP PWB, IS03 Front Audio control, and IS10 Center Graphic EQ. (see Figure 8). The use of DAC's (Digital to Analog Converter) are again configured as fan-out IC's for the microprocessor. (see Figure 9). Although it appears to be more loaded down than the SCL1/SDA1 line, the clock/data 2 line communicates to 31 different devices.
U Y01 3D YC IY01 M ain N TS C IY02 S ub N TS C
IT01 P iP 3Line
C lock M En ab le D ata
IL01 M ain S ync
IL02 S ub S ync
IX 01 Y/C b/C r
IK 01 R G B P roc.
D LP P W B
0C lock P Enable 0D ata
I001 M icro P rocessor
FC E nable
I018 D AC 5
IS 01 D AC 4
IS 03 Fr Audio
1C lock (SC L 1) 1D ata (S D A 1)
IS 05 Fr G raphic
IS 08 C /S W
IS 10 C G raphic
2C lock (SC L 2) M SC E nable 2D ata (S D A 2)
Figure 8 - 2Clock, 2Data, (SCL2, SDA2)
SW SEL 1 DSP CSI O P T I/C O AX S E L R SP O F
COLOR W H T EST 2 COMP 1 CHK COMP 2 CHK
IS 01 D AC 4
C S P O FF F SP O FF SW SEL 2 P VOL DSP REQ
I0 18 D AC 5
PO W MASK PO W + T EST 9 T EST 3 T EST 4
Figure 9 - DAC 4 and DAC 5 pin outs
(continued) Page 4-03
DLP-1 Chassis System Control Block Diagram
SCL1
U201 M ain Tuner
16
SDA1
1Clock (SCL1) 1Data (SDA1)
19 18 IS11 Rear Aud io Co nt. IS10 Cntr Graphic EQ IS08 C/SW Aud io Co nt. IS05 Frnt G raphic EQ
14 12 19 PMB1 PUM1
U202 PiP Tuner I004 DAC1 I003 DAC2
Clock Data M Enable P Enable
I002 EEPROM
Tuner PW B
1 3 2 PSM4
I001 MicroProcessor
FC Enable
UF01 Flex Converter I017 DAC3
IS03 Frnt Audio Cont. 2 IS01 DAC4 1
SCL2 SDA2
(part of) Signal PW B
2 7 6 4 3 PMC 12 14 PMD1
SDA2 SCL2
PSU1
M SC Enable 0Clock 0Data 2Clock (SCL2) 2Data (SDA2)
I018 DAC5
SCL1 SDA1 SCL2 SDA2
Surround PW B
11 10 8 6 PSM1 UY01 3DYC IX01 Y/Cb /Cr
SCL2 SDA2
Micon PW B
SCL1
22 23 24 IT 01 PiP 3Line 25
IY01 Main NT SC I301 A/V Select
SDA1 SCL2 SDA2
SDA2
14 12 PMD1
SCL2
IY02 Sub NT SC
DLP PW B
Term inal PW B
IK01 RG B Processor
PST 2
IL 01 Main Sync
Data
3 4 6 7 2 PMC
Clock 0Data 0Clock MSC Enable
Optical Engine Assem bly
8 9
SCL2 SDA2
DLP-1 Chassis System Control Explanation
IL 02 Sub Sync
PSH2
2H Video PW B MSC PW B
Figure 10 - System Control Block Diagram
Signal PW B
Page 4-04
DLP-1 Chassis Troubleshooting
19.0 TROUBLE SHOOTING FLOW CHARTS
NO PICTURE 1
OK/PC NG
Is TV picture OK?
Check the waveform at pin 1,3,5 of IC02
OK
Check the waveform at pin 3,6 of IC03
OK
IC02, IC03
NG
(*1) From INCORRECT COLOR
NG
NG
Check the waveform at pin 3,6,9 of IC01
OK
QC08, QC09, QC10
Check the waveform at pin16,21, <15,20> of IC01
OK
IC01
NG
NG
Check the waveform at pin 1,4,7 <2,5,8> of IC01
OK
IC01
Check the waveform at pin 7,8 of PHR
OK
DC01, DC02
NG
NG
Check the waveform at pin 1,3,5 of PHR
EHR, JM02
OK
DC03, DC04, DC05
< > :PC in rear NG JM02: Control PWB J304: Terminal PWB
EHR, JM02
Check the waveform at pin 1,3,5 of PHC
OK
Check the waveform at pin 7,9 of PHC
OK
MSC unit DLP unit Optical Engine
NG
NG
2H PWB
2H PWB (A)
2H PWB (B) TV; H,V sync
118
19.0 TROUBLE SHOOTING FLOW CHARTS
NO PICTURE 2
2H PWB (A)
Is waveform at pin 8,10,12 of IC02 normal?
YES
IC02
NO
Is waveform at pin 41,42,43 of IK01 normal?
YES
QK12, QK13, QK14
NO
Does on-screen display appear?
NO
IK01, Q524, Q525, Q526 I001 (MICON PWB)
YES
Is waveform at pin 53 of IK04 normal?
YES
Is waveform at pin 24 of IK04 normal?
YES
IK01
NO
NO
Is waveform at pin 6 of I501 normal?
YES
Q506
Is waveform at pin 16,17 of PSH1 normal?
YES
Q522, D501
NO
NO
2H PWB (C)
NO
Is input signal RF, composite, or 480i component?
UF01
YES
Is waveform at pin 9 of I501 normal?
YES
I501
NO
SIGNAL PWB (A)
NO
Is waveform at pin 9 of PSH1 normal?
YES
Q507
2H PWB
119
19.0 TROUBLE SHOOTING FLOW CHARTS
NO PICTURE 3
SIGNAL PWB (A)
Is waveform at pin 3,[17] of PFC1 normal?
YES
UF01
NO
Is waveform at pin E of QX08 normal?
YES
QX35, QX36, QX37, QX38 [QX45, QX46, QX47,QX48]
[ ]: SUB PICTURE NO
Is input signal RF or Composite?
NO
SIGNAL PWB (C)
YES
Is waveform at pin 15,[5] of IX01 normal?
YES
Is waveform at pin E of QY15 [QY13] normal?
YES
Is waveform at pin 5,[3] of I005 normal?
NO
Q017-Q019, D026 [Q0F1-Q0F3, D0F1]
NO
NO
YES
Is waveform at pin 40 of IY01 [IY02] normal?
YES
IY01,QY12 [IY02, QY09]
Is waveform at pin E of QY16 [QY14] normal?
YES
QY15, [QY13]
Is waveform at pin 24 of I001 normal?
NO
I005
NO
(*2) From INCORRECT COLOR
NO
YES
Is waveform at pin 2 of I003 normal? Is waveform at pin 11 of UY01 [7 of PST2] normal?
NO
Q016, D038
YES
UY01, QY02, QY20 [QY17, QY19]
YES
IX01, QX08, [QX22] I003, I001
NO
SIGNAL PWB
MICON PWB
SIGNAL PWB (B)
Is waveform at pin 60, [63] of I301 normal?
YES
I301,Q304,QY16 [Q302,IT01,QY14,QT05-QT07,QT08-QT11]
NO
U201,Q201 [U202,Q206]
TERMINAL PWB
TUNER PWB 120
19.0 TROUBLE SHOOTING FLOW CHARTS
NO PICTURE 4
2H PWB (C)
Is waveform at pin 8 of I501 normal?
YES
I501
NO
Is waveform at pin 2 of PSH1 normal?
YES
Q501
NO
2H PWB
[ ] : SUB PICTURE << >>: COMPONENT 2
Is waveform at pin E of QX08 normal?
YES
QX09-QX12,QX59 [QX23,QX24,QX60]
NO SIGNAL PWB (C)
Is waveform at pin 55,<<53>> of IX01 normal?
YES
Is waveform at pin E of QY25 <> normal?
YES
Is waveform at pin 2 of I015 <> normal?
NO
I015 <>
NO
NO
YES
Is waveform at pin E of QY22 <> normal?
YES
QY25, <>
Is waveform at pin 22 of I001 normal?
NO
I005, Q046
NO
QX01,QX56,QY22 <>
YES
SIGNAL PWB
Is waveform at pin 1,<<2>> of I004 normal?
NO
Q036,Q037 <>
YES
IX01,QX08,[QX22] I004,I001
MICON PWB
121
19.0 TROUBLE SHOOTING FLOW CHARTS
2H PWB (B) TV; H,V sync
NO PICTURE 5
Is waveform at pin 2,5 of IC03 normal?
YES
IC03
NO
2H PWB
Is waveform at pin15,23 of IL01 normal?
YES
IL03
[ ]: SUB PICTURE
NO
Is input signal RF, composite, or 480i component?
NO
Is waveform at pin 21 of IL01, [IL02] normal?
YES
IL01,[IL02]
YES
NO
Is waveform at pin 1,2 of IL01,[IL02] normal?
YES
Is waveform at pin 3,4,10,11 of IL01 normal?
YES
IL01
Is waveform at pin E of QX10, [QX24] normal?
YES
QL01-QL03 [QL04-QL06]
NO
NO
NO
Is waveform at pin 8 of IY01,[IY02] normal?
YES
IL01,[IL02]
Is waveform at pin 6,7 of PFC2 normal?
YES
IL03
Is waveform at pin E of QX08, [QX22] normal?
YES
QX09,QX10 [QX23,QX24]
NO
NO
NO
Is waveform at pin 3 of IY03,[IY04] normal?
YES
IY01,[IY02]
Is waveform at pin 7,8,14,15 of PFC1 normal?
YES
UF01
NO
NO
Is input signal RF or Composite?
NO
Is waveform at pin 5 of IY03 [IY04] normal?
YES
IY03 [IY04]
Is waveform at pin 13,22 of IL01, [IL02] normal?
YES
IL01 [IL02]
YES
NO NO
Is waveform at pin 7 of IY03,[IY04] normal?
YES
IY03,[IY04] Is waveform at pin E of QX08 [QX22] normal?
IL03
YES
QX09,QX10,QX59 [QX23,QX24,QX60]
NO
SIGNAL PWB
NO
Is waveform at pin 11 of UY01 [pin 7 of PST2] normal?
YES
UY01,QY02,QY03 [QY18,QY19]
SIGNAL PWB (C)
NO
SIGNAL PWB (B)
122
19.0 TROUBLE SHOOTING FLOW CHARTS
INCORRECT COLOR
Is waveform at pin 1,3,5 of PHC normal?
YES
MSC Unit DLP Unit Optical Engine
NO
Is input signal PC SIGNAL?
YES
(*1) To NO PICTURE
NO
Is waveform at pin 52,53 of IK01 normal?
YES
QK12-QK14, IC02
NO [ ] : SUB PICTURE << >>: COMPONENT 2
Q504,Q505, IK01
Is waveform at pin 3,5 of I501 normal?
YES
NO
2H PWB
Is input signal RF, composite, or 480i component?
YES
Is waveform at pin 18,20 of PFC2 normal?
YES
Is waveform at pin 3,5 of I502 normal?
YES
I501,Q520, Q521
NO
NO
NO
Is waveform at pin 46,48,[34,36] of IX01 normal?
YES
Q502,Q503, QX14-QX16, QX18-QX20
Is waveform at pin 4,5,[18,19] of PFC1 normal?
YES
UF01
Is input signal RF or Composite?
YES
Is waveform at pin 11,16 of I502 normal?
YES
I502
NO
IX01,QX02,QX03, <>
NO
NO
NO
Q508-Q513, Q518,Q519
Is waveform at pin 46,48,[34,36] of IX01 normal?
YES
QX14,QX18, QX39-QX44, [QX28,QX32], [QX49-QX54] Is waveform at pin 1,14 of I502 normal?
NO
YES
I502
Is waveform at pin 6 of IY01 [IY02] normal?
YES
IX01,QY10,QY11 [QY07,QY08]
NO
Q508,Q509
NO
2H PWB
(*2) To NO PICTURE
NO
Is waveform at pin 7 of UY01 normal?
YES
IY01,QY01,QY04, QY05,QY06,DY01
SIGNAL PWB 123
19.0 TROUBLE SHOOTING FLOW CHARTS
SNOW NOISE
MAIN PICTURE
Reception Impossible with Snow Noise
Is there output of PLL (clock,data, enable) of I001?
YES
Is there voltage applied (9V,5V,33V) to U201?
YES
U201
NO
NO
I001
I201,I203,D201, Q9F1,Q9F2
SUB PICTURE
Reception Impossible with Snow Noise
Is there output of PLL (clock,data, enable) of I001?
YES
Is there voltage applied (9V,5V,33V) to U202?
YES
U202
NO
NO
I001
I201,I203,D201, Q9F1,Q9F2
124
19.0 TROUBLE SHOOTING FLOW CHARTS
No OSD
Is there LC oscilation at pin(47) and (48) of I001 ?
No check L003, I001
Yes Is there OSD R, G, B sibnals at pin (37), (38), (39) of I001 ?
Yes check Q0F5, Q007 Q013
No check Q005, Q006
125
19.0 TROUBLE SHOOTING FLOW CHARTS
No CCD
Is there Video Y signal at pin(28) and (30) of I001 ?
No check Q021, Q031
Yes check I001
Picture is not blocked by TV Rating/Movie Rating Main Picture is not blocked
Is there Video Y signal at pin(28) of I001 ?
No check Q021
Yes check I001
Sub Picture is not blocked
Is there Video Y signal at pin(30) of I001 ?
No check Q031
Yes check I001
126