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54 Low Level Scan Generation Scan Generator Overview The MM101 is capable of more scan modes than any previous TCE chassis. To accomplish deflection changes and scan signal generation necessary to facilitate all modes, a low level scan generator module is utilized. The scan control generator supplies all Low Level Control Signals (LLCS) to the horizontal and vertical scan generation circuits. It also generates all switching information for the different scan rates and is capable of shutting down scan during scan rate switching or in the event of deflection problems. The horizontal output circuits, after receiving the scan signals, then generate the high current for the horizontal yoke. The vertical output circuits, similiarly generate high current for the vertical yoke. In order to better follow signal paths, some definitions must be understood by the technician. The following list shows abbreviations used to identify the various sync, scan, protection and error signals in this manual and in TCE Electronic Service Data for the MM101. Technical Training will many times spell the abbreviation out rather than use the short form. Other times it is more convenient, or makes a particular diagram less busy to use the abbreviations. VOUT A: One side of the vertical output waveform. Controller IC, U14350-11. VOUT B: One side of the vertical output waveform. Controller IC, U14350-10. DSC: Originates on Deflection Originates on Deflection
Digital SandCastle Signal. Contains a digital representation of the composite horizontal and vertical sync signals at about 2.5Vp-p and a clamping key signal at about 5Vp-p. The clamping key is not used.
SCAN LOSS INT: Scan Loss interupt digital signal warning Micro of some sort of scan loss error in the deflection circuitry. NORMAL: High SCAN LOSS: Low DR TRF HI: Horizontal Driver output signal the Horizontal Driver Transformer, T14300-1. DR TRF LO: Horizontal Driver output signal the Horizontal Driver Transformer, T14300-3. SCAP SW: Switching signal used to change S-Capacitors to correct horizontal frequency compensation. 1H: 0V 2H: +5V >2H: +10V
Low Level Scan Generation 55 LIN SW: Linearity Switch. Digital signal from Deflection DAC, U24800-16, used to switch in and out proper linearity coils to match scan rate. 1H: 2.xH: 0V +10V
FREQ OFFSET: Frequency Offset. Digital signal used to shift the frequency of the Horizontal Deflection Processor, U14711-7. 1H: 2.xH: 0V +10V
1H VCC: Switch voltage indicating when chassis is operating in 1H mode. 1H: 2.xH: High Low
WIDTH REF: Analog width reference voltage used to correct scan for E/W distortions. E/W correction originates from Deflection Controller, U14350-6 and modulates the Scan B+. H SYNC: V SYNC: Horizontal Sync Pulse from Microprocessor, U13101-35. Vertical Sync Pulse from Microprocessor, U13101-34.
H PULSE (H PULSE_A): Horizontal Flyback Pulse derived from a secondary winding of the Horizontal Output transormer, T14451-14. Pulse is originally about 80Vp-p at the horizontal frequency. It is then clipped to about 24Vp-p and used to sync U14350-1. A similar waveform, SCAN H is used to sync oscillator U14711-3 of the HV Generator to Scan. SCAN H (SCAN H_A): Horizontal Flyback Pulse derived from a secondary winding of the Horizontal Output transformer, T14451-8. Pulse is about 24Vp-p at the horizontal frequency. Used to set clock, syncing U14733-9, Dynamic Focus Blanking. Also used to sync the OSD. Waveform similiar to the H PULSE. 80V PULSE: H PULSE passed through LPF. Used by Parallelogram correction circuitry.
56 Low Level Scan Generation
10 E/W Vertical Outputs 11 Line Lock 14 Clock Reference 6 From Deflection DAC U24800-11 2 3 + U14352 1 Width Reference
Vertical Sync Horizontal Output H Flyback (H PULSE)
12
U14350 DEFLECTION PROCESSOR
2
Digital SandCastle +5Vs
16 3 IN
20
Off Center 19 Shift Line Clock 5 Select 18 17
2 6
U14351 PLL
OUT 13 6
+
U14352
7
1
+8Vr 2.xH Select U24100 LATCH 2H Enable
1 8 3
Horizontal SYNC SIG from U13101-35 14 IN
PHASE COMP 5 8
13.6 MHz VCO
+12Vr
Reference
6 U14354 DEFLECTION EEPROM 5
7
1H: HI 2.xH: LO Q24100
+12Vr
4
3 16
R24807 1K
LINEARITY SWITCH VERTICAL OFFSET 2H VCC R24806 100K R24805 1K 1H SWITCH WIDTH ALIGN FREQ OFFSET S CAP SWITCH
To Q14452-B To U14350-10
1 R24814 220 3
U24801 Voltage Ref
U24800 DEFLECTION DAC
15 14 13 R24103 10K
2 R24811 9760 R24812 3320
VCO FREQ
V Ref 12 11
1
To U24100--2 To U14352-2 To H Processor, U14711-7 To S-Cap Switching Circuits
2
5 7 8
10 9
R24803 1K
R24802 1K
Figure 5-1, Low Level Scan Generation Deflection SIP All low level scan driver waveforms are generated from the Deflection SIP (Single In-Line Package). This is a single circuit board that plugs onto the main board using a 20 pin connector block. It contains all IC's necessary to generate and align scan signals in the MM101. It also contains its own EEPROM where the scan related adjustments are stored. These adjustments are downloaded to the various IC's during chassis start up, and also prior to each scan rate change. The EEPROM (U14354), Deflection Controller IC (U14350), and Deflection DAC (Digital-to-Analog Converter) IC (U24800) are IIC bus controlled. Commands from the micro and communication between the scan devices are all carried out via the IIC bus. Various control signals from these devices also manipulate or communicate with other deflection components.
Low Level Scan Generation 57 Figure 5-1 is a block diagram of the Deflection SIP board. There are four sections to the board; Deflection Signal Generation (U14350) Deflection Adjustments and Corrections (U24800) Horizontal PLL (U14351) Horizontal Deflection Signal Output (Discrete) A complete pin out of the Deflection Processor, U14350, and the Deflection DAC, U24800, with explanations, descriptions and expected signals at the individual pins is included at the end of this chapter. Deflection Controller/Processor (U14350) U14350 is a programmable Deflection Controller/Processor in a 20 pin DIP package. It is meant for specific use in both digital and analog high performance TV/Computer Monitor applications, such as the MM101. It serves horizontal and vertical deflection functions for most TV standards. The IC uses a line locked clock capable of running at 6.75, 13.5 or 27 MHz, depending upon the line frequency and scan rate. In the MM101 it operates at 13.5 MHz. This line locked clock is used internally by the Deflection Processor to time all output waveforms. Internal pre-scaler or dividers modify the clock for the required scan mode. All low level scan waveforms are generated from the Deflection Processor, U14350. Horizontal and Vertical Sync from the I/O board sync selector are required to lock the deflection processor to the desired scan rate. The Horizontal Sync signal from the I/O board sync selector is not used directly by the deflection processor. It is first passed to a PLL IC, that compares it to a correction signal from the deflection processor (OFCS). It then fine tunes the line-lock frequency oscillator to force OFCS to match the leading edge phase of Horizontal Sync. Only then is it used as a reference to generate the Off Center Digital horizontal scan waveform. Shift SandCastle
2 19
HORIZ RESET
Horizontal Sync Vertical Sync
13
12
HORIZONTAL AND VERTICAL DETECTOR
VAP
1 HORIZONTAL COUNTER : 432 HORIZONTAL PLACE CONTROL
Horiz Phase OFCS Clamp Shift
PHASE 2 LOOP 20
FBL
H Flyback (H PULSE) Horizontal Output
VERT RESET
Line Lock Clock In Line Clock Select
14 PRESCALER 1: /1 0: /2 5
STSC GBS SLOPE MS WAIT WS Amplitude S-Correction Shift
10 VERTICAL PLACE CONTROL VERTICAL PLACE GENERATOR VERTICAL GEOMETRY 11
Vertical Output B Vertical Output A
OverVoltage Protect Flash Detect
3 9
PROTECTION AND START/STOP CONTROL
LFSS
PARABOLA GENERATOR
EAST/WEST GEOMETRY
Width Parabola Trap Corner
6
E/W
REFERENCE GENERATOR
PON PROT
SIZE COMPENSATION
EHT BLDS
7
EHT
SCL SDA
18 17 IIC INTERFACE
INTERNAL IIC BUS
U14350 DEFLECTION PROCESSOR
8 4 16
15
Digital Ground
Resistive Conversion
Analog Ground
Vcc
Figure 5-2, Deflection Processor Internal Block Diagram
58 Low Level Scan Generation Vertical Processing begins with vertical sync from the I/O board sync selector. It is compared to the incoming line-lock clock and positioned by the Place Control. Correction waveforms are derived and sent to the Horizontal Place Control, the Vertical Place Generator, and the correction Parabola Output. After all corrections are made via the IIC bus, the final vertical output waveform appears on pins 10 and 11. The only further correction is the DC bias added by the deflecion DAC for vertical position offset. The line-lock prescaler sets the proper line clock, depending upon the LL Clock Select signal on pin 14. A high selects the incoming line-lock clock. A low reduces the clock to half the incoming frequency. A digital sandcastle signal is generated from the deflection processor. It is derived from the horizontal and vertical sync after proper raster placement is accomplished. This is a 2.5Vp-p signal output from pin 2, containing both sync and a blanking signal. Several inputs/outputs are not used. These are;
Pin 3 7 9
Digital SandCastle 2 19
Function Over Volt Protect EHT Flash
Off Center Shift
Horizontal Sync Vertical Sync
13
12
HORIZONTAL AND VERTICAL DETECTOR
VAP
HORIZ RESET
1 HORIZONTAL COUNTER : 432 HORIZONTAL PLACE CONTROL
Horiz Phase OFCS Clamp Shift
PHASE 2 LOOP 20
FBL
H Flyback (H PULSE) Horizontal Output
VERT RESET
Line Lock Clock In Line Clock Select
14 PRESCALER 1: /1 0: /2 5
STSC GBS SLOPE MS WAIT WS Amplitude S-Correction Shift
10 VERTICAL PLACE CONTROL VERTICAL PLACE GENERATOR VERTICAL GEOMETRY 11
Vertical Output B Vertical Output A
OverVoltage Protect Flash Detect
3 9
PROTECTION AND START/STOP CONTROL
LFSS
PARABOLA GENERATOR
EAST/WEST GEOMETRY
Width Parabola Trap Corner
6
E/W
REFERENCE GENERATOR
PON PROT
SIZE COMPENSATION
EHT BLDS
7
EHT
SCL SDA
18 17 IIC INTERFACE
INTERNAL IIC BUS
U14350 DEFLECTION PROCESSOR
8 4 16
15
Digital Ground
Resistive Conversion
Analog Ground
Vcc
Figure 5-3, Deflection Processor Internal Block Diagram (Repeated)
Low Level Scan Generation 59 All internal adjustments are communicated over the IIC bus. The internal block shows which section the adjustments affect. Adjustment values are stored in the Deflection EEPROM, U14354. Several abbreviations of the IIC signals are noted on the internal block diagram. They are further explained below. VAP: LFSS: 1 bit selection of positive or negative edge detection of the incoming vertical sync signal. Line Frequency Start/Stop. 1 bit selection used by the main micro to start or stop scan. E/W output current stops and vertical is set to 20% output when LFSS=0. Status bit for Power On Reset. Over Voltage Protect bit. Normal: logic 0 Extra High Tension Select. High Voltage Bleeder mode selection. Flyback Slicing Level.
PON: PROT: EHT: BLDS: FBL:
All other abbreviations should be considered standard TCE nomenclature for the various circuits.
60 Low Level Scan Generation
10 E/W Vertical Outputs 11 Line Lock 14 Clock Reference 6 From Deflection DAC U24800-11 2 3 + U14352 1 Width Reference
Vertical Sync Horizontal Output H Flyback (H PULSE)
12
U14350 DEFLECTION PROCESSOR
2
Digital SandCastle +5Vs
16 3 IN
20
Off Center 19 Shift Line Clock 5 Select 18 17
2 6
U14351 PLL
OUT 13 6
+
U14352
7
1
+8Vr 2.xH Select U24100 LATCH 2H Enable
1 8 3
Horizontal SYNC SIG from U13101-35 14 IN
PHASE COMP 5 8
13.6 MHz VCO
+12Vr
Reference
6 U14354 DEFLECTION EEPROM 5
7
1H: HI 2.xH: LO Q24100
+12Vr
4
3 16
R24807 1K
LINEARITY SWITCH VERTICAL OFFSET 2H VCC R24806 100K R24805 1K 1H SWITCH WIDTH ALIGN FREQ OFFSET S CAP SWITCH
To Q14452-B To U14350-10
1 R24814 220 3
U24801 Voltage Ref
U24800 DEFLECTION DAC
15 14 13 R24103 10K
2 R24811 9760 R24812 3320
VCO FREQ
V Ref 12 11
1
To U24100--2 To U14352-2 To H Processor, U14711-7 To S-Cap Switching Circuits
2
5 7 8
10 9
R24803 1K
R24802 1K
Figure 5-4, Low Level Scan Generation and Adjustments Deflection DAC (U24800) The Deflection DAC converts IIC commands to analog voltages. A complete pinout of the IC is included at the end of this chapter. Pins 9 thru 16 are the eight DAC outputs. The output range is between +0.1 to +9.8 volts. Several of the DAC's are used for switching. The S-Cap Switch, pin 9, is used as a tri-state switcher. Pin 1 is the power supply (+12Vr) and pins 5, 7 and 8 are grounds. Pin 2 is a voltage reference for the DAC maximum output voltage. Nominally +9.8V.
Low Level Scan Generation 61 Pins 3 and 4 are the IIC bus clock and data lines. Pin 6 is not used and not connected. Pin 9 is the S-Cap switching signal used to change the appropriate S-Caps in and out of the horizontal yoke circuit. Refer to the "Horizontal Deflection" section for detailed information. The logic states are: 0V 1H 5V 2H 10V >2H Pin 10 is a digital output used to fine tune the horizontal frequency processor, U14711. The horizontal frequency processor generates a 2H signal used to drive the high voltage generator outputs. Refer to the "High Voltage Power Supply" section for detailed information. Pin 11 is an analog output for horizontal width alignment. Refer to the "Horizontal Deflection" section for detailed information. Pin 12 is a two state output used to set the 2H inhibit latch, U24100. 8 volts is 1H and 0V is 2.xH. Pin 13 is the line locked clock VCO adjustment voltage, normally at or around +2.5V. It may be adjusted via the IIC bus to fine tune the line locked clock frequency. Pin 14 is a two state 2H Vcc switch used as an input to the 1H Vcc Enable switch, Q24100. At 1H pin 14 is low. >2H is high or about +10V. Pin 15 is an analog voltage output used to adjust the Vertical Offset. It provides a DC offset voltage on one side of the vertical output waveform from U14350-10. This allows vertical positioning of the raster. Refer to the "Vertical Deflection" section for detailed information. Pin 16 is a two state switching voltage used to control which linearity coils are placed in series with the horizontal yoke. It is 0V during 1H scan and +10V at scan rates >2H. Refer to the "Horizontal Deflection" section for detailed information.
62 Low Level Scan Generation Horizontal Deflection PLL The Line Locked Clock (LLC) is an extremely important signal. It is used to lock the horizontal and vertical rates at the precise frequencies required to provide acceptable scan. The line locked clock circuit consists of a PLL IC (U14351), filter and VCO. Nominal frequency is 13.6MHz. The Deflection Processor, U14350, uses the 13.6MHz VCO LLC to generate the proper horizontal frequency. At 1H, the Line Clock Select signal is low, causing the LLC to pass through a divider (prescaler), dividing it in half. The resulting signal then passes through the horizontal counter, which again divides it, this time by 432. The resulting frequency is about 15.7 kHz or 1H.
U14350 Deflection Processor
PHASE 2 LOOP PRESCALER 2H, 1: 1 1H, 0: 2
6.8 MHz U14352 BUFFER
H SYNC IN
14 U14351 PLL 13 ERROR SIGNAL OUT
3
Off Center 19 Shift
20 1
Horizontal Output
Horizontal Drivers
Horizontal Deflection
2H: ~31.5kHz 1H: ~15.7kHz
H Flyback (H PULSE)
2H LPF
13.6 MHz VCO
Line Lock Clock In 14
13.6 MHz
HORIZONTAL COUNTER : 432
5 1H: LO 2H: HI U14356 SWITCH Line Locked Clock Select
Scan Loss Detector Q24103/05
SCAN_LOSS_INTERUPT
SCAN PRESENT 2 Inhibit 2H Select 3 Q2 Q24100 U24100 Latch Data 6 13 VCO FREQ U24800 DEFLECTION DAC 12 1H SW 1H SW 14 2H VCC Q1
2H Enable
7
1H: HI 2.xH: LO
Figure 5-5, Horizontal Frequency PLL Block Diagram At 2.xH, the LLCS signal is high, activating the internal switch. This time, the LLC does not pass through the prescaler. However, it still passes through the horizontal counter, which divides it by 432. The resulting frequency is around 31.5 kHz or 2.xH. To keep the frequency as close to the exact as possible, a Phase-Locked Loop (PLL) is used. A sample of the horizontal frequency (OFCS) is passed to the PLL IC, U14351. It is compared with the horizontal sync (H SYNC) from the microprocessor and an error signal generated. In 1H mode, the error signal is passed directly to a buffer, U14352. The amplified signal then goes to the VCO where it varies the frequency depending upon the amplitude of the signal. At 2H, the rapid changes in frequency of the error signal may cause jitter in the raster. The error signal is first run through a low pass filter to remove the higher frequency corrections. At 1H it is desirable to continuously correct the frequency to compensate for unstable incoming signals from VCR's or other devices.
Low Level Scan Generation 63
U24800 DEFLECTION DAC U24801 9.8V Reference
VCO FREQ 13
R24806 100K
R14541 150K C14536 1000
Q14540/41
C14539 8.2
13.6MHz LLC to U14350-14
CR14541 VCO
+5Vr R14561 10K Error Correction From U14351-13 6 5 R14562 10K
L14550
U14352 BUFFER
R14555 1200 7
+ R14565 1000
Figure 5-6, Line Locked Clock VCO Line Locked Clock VCO Course adjustment of the VCO is accomplished by the tuning inductor, L14550. Fine adjustment of the VCO is accomplished by two methods. First, a control voltage from pin 13 of the Deflection DAC, U24800 is connected to the top of the VCO, CR14541. By varying the DC voltage on the VCO, its frequency may be adjusted. The VCO is normally biased with its cathode more positive than its anode voltage. Capacitance of a varicap diode changes with applied reverse bias. The IIC bus controls this voltage depending upon the scan mode. 1H and 2H are normally around +0.5V at U24800-13. The voltage increases for higher (2.1H and 2.4H) scan rates. Automatic adjustment via the PLL signal is implemented by connecting the output of the buffer, U14352 to the bottom side of the VCO loop. If the DAC voltage is held constant, varying the voltage on the output of the buffer changes the voltage across the VCO loop. If the DAC output is constant, lowering the buffer output would increase the voltage across the VCO and it would vary upward in frequency. Increasing the buffer output would decrease the voltage drop across the VCO and it would vary downward. Since one side of the buffer is held relatively constant at +2.5V, the error correction at pin 6 will ride on that level. A nominal +1.26V should be measured at U14352-7 because VCO FREQ is aligned for that voltage. The same effect would be realized by varying the DAC output while holding the buffer output constant. If the DAC output increases, the voltage drop across the VCO would increase and the frequency would go up. If the DAC output decreases, the voltage drop across the VCO would decrease and the frequency would go down.
64 Low Level Scan Generation Line Locked Clock Select The 2H Select signal changes the internal prescaler circuit of the Deflection Processor, U14350 between 1H and 2H modes. It also switches the Low Pass Filter components of the PLL circuitry. The origin of this signal is called 1H SW and originates from the Deflection DAC, U24800-12. The switch is activated via IIC bus control from the main microprocessor. There is also an associated 2H switch called 2H Vcc. 2H Vcc switches the Scan B+ supplies between 2H ZVS (up to +167V in 2.4H, SVGA mode) and 1H series pass (+67V). These two work together to insure positive scan mode switching. When 1H scan mode is selected, the 1H SW at U24800-12 is switched high (app +10V). This switches the latch, U24100 off, placing a low on the line locked 2H Select line at U14350-5. When U14350-5 is low, the Deflection Processor is in 1H mode. At the same time U24800-14 (2H Vcc) is switched low (<+0.5V) turning off the inverter, Q24100. When Q24100 is off, 1H Vcc is high and the lower series pass Scan B+ supply is selected by turning the higher output voltage ZVS supply off. During 2H, the two signals are reversed. 1H SW at U24800-12 is switched low (app +0.5V). This toggles the latch, U24100 on, placing a high on the 2H Select on U14350-5, switching the Deflection Processor (U14350) and Low Pass Filter to 2H mode. At the same time U24800-14 (2H Vcc) is switched high (>+8V) turning on the inverter, Q24100. Q24100 now switches the Scan B+ supply from the lower voltage series pass supply to the higher ZVS supply.
U24800 DEFLECTION DAC
2H Vcc 1H: Low 2H: High
1H Vcc R24102 10K
1H: Off 2.xH: On
2H 14 VCC 1H SW SCAN H_A PULSE FROM HORIZONTAL OUTPUT TRANSFORMER T14451-8 CR24100 R14354 18K R24112 100K R24109 4.7K R24118 47K +8Vr
1H SW 12 1H: High 2.xH: Low R24106
R24103 10K
2H Enable 1H: Low 2H: Open
Q24100
Inverter
C14102 1500
CR24101 R24111 10K Q24103
Q24101 ON: SCAN OFF: SCAN LOSS
180K
7 DISCHARGE OUTPUT 3
2H Select
1H: Low 2H: High
6 2 R24107 4.7K R24105 4.7K 4
Q24101 R24104 68K Q24102
1/2 Vcc
THRESHOLD TRIGGER
RESET
5
LLCS U14350 DEFLECTION CONTROL
U24100 Latch
Vcc 8 R14100 220 +8Vr GND 1
To LPF Switch U14356-6
Figure 5-7, Line Locked Clock, 1H and 2H Select Mode Switch Latch The mode switch latching circuit, U24100, is used to prevent scan mode switching during power transients, system spikes such as kine arcs and during active scan. This means scan mode switching can only occur when no (or very little) yoke current is present. U24100 is a 555 timer used as a latch (See the Tech Tip "Control Latch" on the following pages). It has some unique properties making it more desirable than a standard TTL RS Latch in this application.
Low Level Scan Generation 65
Figure 5-8, SCAN H_A Pulse The SCAN H_A pulse (Figure 5-8) derived from the flyback pulse of the horizontal output transformer (T14451-8) is first rectified by CR24100 resulting in a positive supply voltage on Q24103-B. If horizontal scan is present, SCAN H_A is also present. If horizontal scan stops, so will SCAN H_A. C14102 charges between the rectified SCAN H_A voltage and +8Vr. (When SCAN H_A stops, C14102 will maintain a reverse bias on Q24103 for a short time.) The PNP transistor is reversed biased, turning it off, and turning Q24102 off. Q24101 is turned on by the +8Vr supply via R24104. It's emitter is held constant at 1/2 Vcc by the resistor divider network, R24105 and R24107. While Q24101 is on, U24100-2 and U24100-6 are held at about 1/2 Vcc. According to the truth table in Figure 5-9, pin 3 is active and whatever state the latch was in will be held regardless of any change in the 1H SW. NOTE: The RESET line will always be in a NOT RESET state when power is supplied. This means the last three lines of the truth table are the only allowable states when the MM101 is on and main power is running. If scan stops, the SCAN H_A pulse from the horizontal output transformer will also stop. C14102 will maintain the positive bias on Q24103-B for a short while to prevent false triggering, but will slowly discharge, decreasing the voltage. When it decreases far enough, Q24103 turns on, turning on Q24102. Q24102 removes bias from Q24101-B turning it off. The latch, U24100 may now be controlled by the voltage from the Deflection DAC, U24800-12. REMEMBER: Whichever state is active, 1H or 2H, will be held when the SCAN H_A pulse, indicating active scan, returns. The latch prevents the 2H Select from changing LLCS during active scan. It also prevents 1H Vcc from going low while 2H Select is high.
TECH TIP
66 Low Level Scan Generation Control Latch U24100 is actually a 555 timer IC configured to be used as an RS Latch with inhibit. In the MM101 configuration pin 5, a control voltage normally used to shift the two trip voltages for the THRESHOLD and TRIGGER equal amounts, is not used. It is not connected on the board.
TECH TIP
In this application, the 555 is used as a latch to prevent false switching of scan modes or switching of the scan circuits during active scan. The outputs of the IC are pin 3, called the output and pin 7, called the Discharge. In timer applications, the discharge pin is used to control the timing capacitor that sets the frequency of the timer. In the MM101 the discharge pin is used to switch external circuitry. Internally, it is an open drain FET, connected to pin 1, which is normally ground. The relationship between the threshold voltage on pin 6 and trigger voltage on pin 2 is essential. Note the truth table. If pin 4, RESET, is low, the output will remain low and the discharge switch will stay on indefinitely. No matter how the input lines change, pin 3 will remain low and pin 7 will be connected to ground (ON). When the RESET line goes high, the timer is activated. If the THRESHOLD voltage is greater than 2/3 of the supply voltage (Vcc), the TRIGGER input is active. If the TRIGGER voltage is greater than 1/3 Vcc, the OUTPUT will stay low and DISCHARGE will remain ON. If TRIGGER decreases to less than 1/3 Vcc, the OUTPUT will toggle high, and the DISCHARGE switch will open. If the THRESHOLD voltage decreases to less than 2/3 Vcc, but the TRIGGER voltage remains greater than 1/3 Vcc, the OUTPUT and DISCHARGE pins will be locked at whatever state they were in prior to the change in trigger voltage. As long as THRESHOLD is <2/3 Vcc and TRIGGER is greater than 1/3 Vcc the last OUTPUT/ DISCHARGE state will remain locked unless a the RESET signal goes low.
Vcc
8
RESET
4
THRESHOLD CONTROL 5
6
+ _
3
OUTPUT
7 + N
DISCHARGE
TRIGGER
2
_
1
STATE
THRESHOLD VOLTAGE Pin 6
TRIGGER VOLTAGE Pin 2
RESET Pin 4
OUTPUT Pin 3
DISCHARGE SWITCH Pin 7
1 2 3 4 > 2/3 Vcc < 2/3 Vcc > 1/3 Vcc > 1/3 Vcc < 1/3 Vcc
0 1 1 1
0 0
NO CHANGE
ON ON
NO CHANGE
1
OFF
Figure 5-9, 555 Timer and Truth Table
Low Level Scan Generation 67 Digital SandCastle A Digital SandCastle (DSC) signal is generated by the Deflection Processor, U14350-2. The output is a composite blanking signal containing horizontal and vertical blanking plus a clamping pulse. The clamping pulse is not used in the MM101.
Digital SandCastle 2 19 Off Center Shift
Horizontal Sync Vertical Sync
13
12
HORIZONTAL AND VERTICAL DETECTOR
VAP
HORIZ RESET
1 HORIZONTAL COUNTER : 432 HORIZONTAL PLACE CONTROL
Horiz Phase OFCS Clamp Shift
PHASE 2 LOOP 20
FBL
H Flyback (H PULSE) Horizontal Output
VERT RESET
Line Lock Clock In Line Clock Select
14 PRESCALER 1: /1 0: /2 5
STSC GBS SLOPE MS WAIT WS Amplitude S-Correction Shift
10 VERTICAL PLACE CONTROL VERTICAL PLACE GENERATOR VERTICAL GEOMETRY 11
Vertical Output B Vertical Output A
OverVoltage Protect Flash Detect
3 9
PROTECTION AND START/STOP CONTROL
LFSS
PARABOLA GENERATOR
EAST/WEST GEOMETRY
Width Parabola Trap Corner
6
E/W
Figure 5-10, Deflection Processor, U14350 (Partial) During a short duration at the beginning of the vertical blanking pulse, beginning at the second horizontal line and lasting about three horizontal lines, pin 2 is switched to act as an input. During this time, it looks for feedback from a sample of the vertical flyback pulse to determine if vertical scan is present. This guards against loss of vertical scan and is called the Guard Pulse. The duration may be seen in Figure 5-11 as a "hole" in the vertical blanking pulse. If this "hole" is not filled in by the vertical flyback pulse, blanking goes high keeping video shut off. This prevents CRT damage if vertical scan ceases. NOTE: Figure 5-11 shows the vertical blanking portion of the DSC from U14350-2 if the path between pin 2 and the vertical deflection circuit were open. There are no conditions where this specific waveform would normally be seen. It is used here for explanation.
Figure 5-11, DSC Pulse
68 Low Level Scan Generation During normal operation, the DSC appears at U14350-2 as the bottom trace of Figure 5-12. The positive (high) portion of the waveform is blanking. The spikes riding through the waveform are the 2.5V horizontal blanking and 5V clamp key pulses. Now note the top waveform. The vertical flyback signal is not present and blanking has gone high. It stays high until the Guard Pulse is present. During this time the Deflection Processor again looks for a vertical flyback pulse. If it is present, the normal DSC would return. If it is not, the Deflection Processor continues to blank video.
Vertical Flyback Missing
Normal DSC
Figure 5-12,
DSC Signal
The vertical flyback pulse is placed on the DSC by Q14501 in this manner. Q14501-B is held at +12V. When the vertical flyback voltage is active (during vertical retrace), it is coupled to Q14501-E, biasing it on. The flyback pulse, normally about +40Vp, causes a current of (40V-12V/R14502 to flow thru diode CR14508 and R14501. to U14350-2.
+12Vr
Q14501-C
R14320 1200 CR14301 5.1V 4 6
RESET
C14302 0.1
R14322 10K
8 Vcc OUTPUT 3 COMPOSITE BLANKING
Q14501-E
+15Vr CR14505 C14303 1200 CR14509 CR14510 CR14501 +12Vr 5
THRESHOLD
+12Vr 7 R14751 10K Q14733 R14301 10K R14302 10K C14301 1200 1H Vcc BUFFER
U14301
CONTROL DISCHARGE TRIGGER 2 Q14301 CR14502 GND 1
1H Vcc 1H: LOW 2H: HIGH
R14501 1000 [CR14508]
Q14501
[R14502] 16K
[R14515] 10K CR14504 +12Vr
Q14502
C14503 220UF 35V +12Vr
R14517 220 [R14518] 10K [R14518] 1000
SCAN V To Micro U13101-34
DSC From U14350-2
2
6
3 CR14507 FLYBACK GEN
1 7 POWER AMP 4 Vertical Output U14501
-15Vr
Figure 5-13, DSC and Blanking Stripper
Low Level Scan Generation 69 Blanking Stripper The DSC contains a video clamping pulse at the horizontal rate that is unused in the MM101. However, if not removed, it might fool the video circuits and cause unwanted blanking to occur blocking what should be visible picture. U14301 is a 555 timer used to control the timing of the blanking pulse and ignore the clamping signal. Figure 5-14 shows an incoming DSC signal at the horizontal rate. The clamping pulse is visible as a second pulse, larger in amplitude and occuring after blanking. Pin 3 is the output signal. Note the blanking waveform is inverted by U14301.
U14301-3
U14301-2
Figure 5-14, Normal DSC and Blanking Output at 1H At 1H, the rising leading edge of the DSC pulse on pin 2 triggers the end of the output pulse on pin 3 and it goes low. Vcc for the IC is set by zener diode CR14301 at 5.1V. The RESET and CONTROL lines are fixed for constant operation. Once operation of the timer has begun, THRESHOLD quickly reaches a point just below Vcc, but as long as the DSC is low, state 4 is active. When the DSC pulse rises above 1/3 Vcc, the DISCHARGE switch is on and THRESHOLD is switched to ground. The OUTPUT now switches low and the timer is in state 2. When the falling edge of the DSC goes below 1/3 Vcc, the DISCHARGE switch shuts off and the output goes high (state 4). With the DISCHARGE switch now off, C14301 and R14322 now form a time constant circuit whose intial voltage is close to ground. With THRESHOLD now less than 2/3 Vcc, state 3 is active and no change to the OUTPUT or DISHARGE switch is allowed. The OUTPUT remains high. During this period the clamp pulse comes and goes without changing the timer output. According to the time constant, THRESHOLD eventually rises to >2/3 Vcc. If the DSC is less than 1/3 Vcc, the OUTPUT will switch high. If it is greater than 1/3 Vcc the OUTPUT goes low and the cycle repeats.
STATE THRESHOLD VOLTAGE Pin 6 TRIGGER VOLTAGE Pin 2 RESET Pin 4 OUTPUT Pin 3 DISCHARGE SWITCH Pin 7
1 2 3 4 > 2/3 Vcc < 2/3 Vcc > 1/3 Vcc > 1/3 Vcc < 1/3 Vcc
0 1 1 1
0 0
NO CHANGE
ON ON
NO CHANGE
1
OFF
Figure 5-15, U14301 Truth Table
70 Low Level Scan Generation Vertical Guard If vertical scan stops for any reason, the vertical flyback pulse will also stop. Figure 5-16 on the left shows a normal DSC signal (U14301-2) and resulting blanking signal from U14301-3. The right waveform shows what happens to those signals when vertical flyback is removed.
U14301-3
U14301-2
Figure 5-16, Left: Normal DSC and Blanking Output Right: Loss of Vertical Flyback Pulse If the vertical flyback feedback pulse is lost for any reason, the resulting loss of the NOT BLANKING signal means blanking will always be present. All video information is removed from the CRT drivers. However, since the Vertical Guard pulse is actually stopping the blanking pulse for a short duration, a thin horizontal line of average brightness may appear on screen. Placement on the screen may be random but will be constant once it appears. This assumes all other circuits are working correctly. Horizontal Scan Loss The Deflection Processor, U14350, monitors horizontal scan for proper operation by looking at the horizontal flyback pulse on pin 1. If it disappears, indicating missing horizontal scan, all scan outputs will be stopped and an error message logged to the microprocessor.
TECH TIP
Low Level Scan Generation 71 Geometry Correction Most normal geometry correction is done internally by the Deflection Processor. These include, E/W Pincushion correction, symmetry (trapezoidal), DC offset (width) and corner correction. The correction waveform is output from pin 6 and modulates the Scan B+ ZVS and Series Pass supplies depending upon which scan mode the chassis is in. Again, this takes advantage of the premise that raster width has a direct relationship to Scan B+. By varying Scan B+ at the precise time, the raster may be made wider or narrower.
10 E/W Vertical Outputs 11 Line Lock 14 Clock Reference 6 From Deflection DAC U24800-11 2 3 + U14352 1 Width Reference
Vertical Sync Horizontal Output H Flyback (H PULSE)
12
U14350 DEFLECTION PROCESSOR
2
Digital SandCastle +5Vs
16 3 IN
20
Off Center 19 Shift Line Clock 5 Select 18 17
2
U14351 PLL
OUT 13 6
+
U14352
7
1
+8Vr
8
Horizontal SYNC SIG from U13101-35 14 IN
PHASE COMP 5 8
13.6 MHz VCO
2.xH
3
+12Vr
Reference
Figure 5-17, EW Geometry Correction
72 Low Level Scan Generation Figure 5-18 is a pinout of the Deflection Processor, U14350. The following list includes individual descriptions of the pins. Some pins are not used in the MM101 chassis. Those are identified as either not used and grounded, or not used and tied to a supply voltage. 1. HPULSE (Horizontal Flyback): ANALOG INPUT; 20Vp-p at the horizontal scan rate. Derived from the flyback portion of horizontal output transformer. DSC (Digital Sandcastle): A/D OUTPUT; Two level signal. Digital H&V blanking signal at 2.5Vp-p. Video clamping signal at 4.5Vp-p. D/A INPUT; >0.5V derived from Vertical Flyback indicating presence of vertical scan.
1 2 3 4 5 6 7 8 9 10 H Flyback (H PULSE) Digital SandCastle OverVoltage Protect Analog Ground Horizontal Output Off Center Shift SCL 20 19 18 17 16 15 14 13 12 11
Line Clock Select E/W EHT
U14350 DEFLECTION SDA PROCESSOR
Vcc Digital Ground Line Lock Clock In Horizontal Sync Vertical Sync Vertical Output A
2.
Resistive Conversion Flash Detect Vertical Output B
Figure 5-18, Deflection Processor Pinout
3. 4. 5.
OVP (OverVoltage Protect): Not used, grounded. Analog Ground: Ground for IC analog components. LLCS (Line Locked Clock Select): LOGIC INPUT; Selects line frequency of Deflection Processor. LOW: Low Frequency (1H) Select HIGH: High Frequency (>2H) Select E/W (East/West Geometry): width reference. 0-5Vdc ANALOG OUTPUT; Geometry correction waveform for
6. 7.
EHT: Extra High Tension used to allow compensation of raster size vs high voltage supply. Not used, grounded. However, the EEPROM bit for this setting should be zero. If it is not, the raster will shrink. Initialization of the EEPROM would be indicated. External Resistive Conversion: Resistor sets the reference current. Scales the amplitudes of the various geometry correction signals from the E/W output, VOUT A and VOUT B. FLASH: Reset soft start initiation. Not used, grounded.
8. 9.
10. VOUTB (Vertical Output B): ANALOG OUTPUT; Vertical Output waveform. 11. VOUTA (Vertical Output A): ANALOG OUTPUT; Vertical Output waveform. 12. VERT IN (Vertical Sync In): microprocessor. 5Vp-p ANALOG INPUT; Vertical Sync signal from main
13. HORIZ IN (Horizontal Sync In): Not used, grounded. 14. LLC (Line Locked Clock In): DIGITAL INPUT; Line Locked Clock input locked at 432 or 864 times the horizontal frequency. 15. DIG GND (Digital Ground): Ground for IC digital components.
Low Level Scan Generation 73 16. Vcc: Supply Voltage, +8Vr 17. SDA (DATA IN/OUT): DIGITAL INPUT/OUTPUT; IIC data I/O line. 0-5Vp-p 18. SCL (Clock IN): DIGITAL INPUT; IIC clock input. 0-5Vp-p. 19. OFCS (Off Center Shift Out): ANALOG OUTPUT; Horizontal Rate output locked to incoming Horizontal Sync by the PLL. 04.5Vp-p 20. HORIZ OUT (Horizontal Output): Output waveform. Horizontal
1 Vcc Voltage Reference SDA LIN SW Vertical Offset 2H Vcc 16
2
15
Figure 5-19 is a pinout of the Deflection DAC, U24800. It has eight channels of Digital to Analog converters, individually programmable via the IIC bus. Maximum output voltage range is from +0.1 to +10VDC. The following list includes individual descriptions of the pins. Some pins are not used in the MM101 chassis. Those are identified as either not used and grounded, or not used and tied to a supply voltage. 1. 2. 3. 4. 5. 6. 7. 8. 9. Vcc: Supply Voltage, +12Vr
3
14
4
SCL Digital Ground Not Used Digital Ground Analog Ground
U24800 DEFLECTION DAC
VCO Freq 1H SW
13
5
12
6
Width Alignment 2H PLL Offset S CAP SW
11
7
10
Voltage Reference: ANALOG INPUT; Reference for the DAC's. +10V
8
9
SDA (DATA IN/OUT): DIGITAL INPUT/ Figure 5-19, Deflection DAC Pinout OUTPUT; IIC data I/O line. 0-5Vp-p SCL (Clock IN): DIGITAL INPUT; IIC clock input. 0-5Vp-p. DIG GND (Digital Ground): Ground for IC digital components. NC: Not Used, no connections. DIG GND (Digital Ground): Ground for IC digital components. Analog Ground: Ground for IC analog components. S CAP SW: DAC 0 ANALOG OUTPUT; Tri-State output for S Cap switching.
10. 2H PLL Offset: DAC 1 ANALOG OUTPUT; Two state output used to shift the VCO frequency for the High voltage generator. 11. Width Alignment: DAC 2 ANALOG OUTPUT; Width signal. 12. 1H SW: DAC 3 ANALOG OUTPUT; 1H Switch to 1H/2H Latch 13. VCO Freq: DAC 4 ANALOG OUTPUT; DC voltage used to fine tune the VCO for the Line Locked Clock PLL. 14. 2H Vcc: DAC 5 ANALOG OUTPUT; Switch for High Voltage frequency generator.
15. Vertical Offset: DAC 6 ANALOG OUTPUT; Vertical DC offset voltage. 16. LIN SW: DAC 7 ANALOG OUTPUT; Dual State output for Linearity Coil Switching.