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Sync Processing and Scan Generation
23
Sync Processing Overview
Sync processing was not covered in the original MM101 Manual due to time constraints. This discussion will begin with sync switching in the MM101, then progress to sync switching in the MMC101G/MMC102(G). There have been many refinements in this area from the early MM101. The MMC101G now incorporates 15 scan modes including one that can "adapt" itself to nearby frequencies both horizontally or vertically. Three of the programmed modes are currently not used leaving a total of 12 available scan modes. Horizontal scan rates for 1H (15.734kHz) may vary between 14.5kHz and 16.3kHz. For 2.xH they may vary from 29kHz to 39.3kHz. Horizontal sync may be either positive or negative at TTL levels. Vertical scan rates may vary from 48Hz to 89Hz for the MMC101 but are limited to 60Hz for the projection instrument MMC102(G). Vertical sync may be either positive or negative at TTL levels.
Adaptive Scan Mode
The adaptive scan mode allows the MMC101G to vary horizontal and vertical scan modes in order to capture non-standard incoming video modes. The MMC102(G) varies horizontal only. This is particularly useful for some power up display modes on specific computers that do not conform to normal video modes. If the microprocessor does not recognize the incoming sync as a supported mode, the deflection VCO frequency is calculated based on a sample of the incoming signal. The deflection processor adjusts to the vertical rate and the signal is displayed at whatever overscan or underscan results. This allows scan to lock to unsupported computer formats during a boot up process and display synced video allowing the user to see a display long enough to adjust the video adapter to a supported format.
24
Sync Processing and Scan Generation
D e flection M o de 0 1 2 3 4 4 5 6 7 8 9 10 11 12 13 14 14 15
Forma t NTSC/YUV VGA VGA2 (Adaptive ) VGA3 DTC100 (SDTV) DTC100 (HD) SVGA-s td SVGA VESA 480 Not us e d XGA Not us e d Movie 1 Movie 2 Not us e d EIA 770.1 DVD EIA 770.2 DVD EIA 770.3
Horiz Scan Rate (KHz) 14.5 - 16.3 31.46 29 - 39.3 29 - 32.6 32.6 - 33.75 32.6 - 33.75 32.6 - 36.5 36.5 - 39.3 36.5 - 39.3
Ve rt Scan Rate (Hz) 59.94 69.93 69.93 58.1 - 62 58.1 - 62 58.1 - 62 53 - 58.1 54.3 - 66.6 66.6 - 75.6
Inte rlace H-Re s V- R e s /Proge s s ive H-Sync V-Sync (dots ) (dots ) Scan 726 640 640 640 1920 1920 800 800 640 484 350 400 480 540 1080 600 600 480 Int Pro g Pro g Pro g Pro g Int Pro g Pro g Pro g Neg Pos Neg Pos Neg Pos Pos Pos Pos Neg Neg Neg Pos Neg Neg Pos Pos Pos Pos Neg
32.6 - 36.5
85 - 89
1024
768
Int
Pos
Pos
15.72 15.72
48 48
640 640
483 575
Int Int
Neg Neg
Neg Neg
29.0 - 32.6 29.0 - 32.6 32.6 - 36.5
58.1 - 62 58.1 - 62 58.1 - 62
720 720 1920
480 480 1080
Pro g Int/Prog Int
Neg Neg Neg
Neg Neg Neg
Figure 4-1, MMC101G/MMC102(G) Scan Mode Chart
Note: MMC102(G) has vertical scan locked to 60Hz. The supported formats for the MMC102 are 0, 3, 4, 6, 14, and 15.
XGA not compatable with all video cards.
Sync Processing and Scan Generation
25
Scan Generator Mode Review
The MMC101G/MMC102(G) has 15 different scan modes plus one scan mode that can "adapt" itself to nearby scan rates. There may be some misunderstanding of horizontal vs vertical scan rates in the computer modes and how incorrect settings can distort the display or render it unviewable.
Figure 4-2,
Standard 800x600 Computer Display
For this initial discussion a standard 800x600 progressive scan display is used. Since computer displays are typically not overscanned, all 800 lines in the horizontal direction are visible as are all 600 lines in the vertical direction. In this illustration each block represents 100 lines. The following discussion will also ignore horizontal and vertical retrace. The principles of operation remain the same, but scan times will lengthen with the addition of retrace time. Normally computer video rates are set by the "Refresh" rate, which is actually vertical scan rate. Using the 800x600 resolution mode, first consider how long it takes to scan the 600 lines down the screen. If a typical refresh or vertical scan rate (Vf) of 60Hz is used, all 600 lines must be drawn every 1/60th of a second (1/Vf) or once every 16.67 milliseconds (msec). To find the horizontal time to draw each line, divide the total vertical scan time by 600 (the number of horizontal lines drawn in each vertical interval). This means each horizontal line must be drawn by horizontal scan in 16.67 msec/600 or every 27.8 microseconds (usec). The horizontal frequency required to complete the line draw in the given amount of time is calculated by taking the reciprocal of the time, 1/27.8 usec or 35.971KHz. So to present a standard 800x600 display at a refresh rate of 60Hz vertical scan must run at 60Hz and horizontal scan must run at 35.971KHz. Referring to the mode chart in Figure 4-1, both frequencies are within the ability of the MMC101G scan system allowing a proper display.
26
Sync Processing and Scan Generation
Figure 4-3, 800x600 Display Timing But what if a user decides 60Hz has too much flicker to be useful and attempts to set the video card to 75Hz? Returning to the formulas for deciding what horizontal and vertical frequencies the MMC101G can accommodate will reveal whether this would generate a usable display. First, vertical scan must occur in 1/Vf (1/75) seconds or 13.3 msecs. Dividing the total vertical scan time by 600 tells us how long each horizontal line must take. In this case 13.3 msec/600 equals 22.2 usec. The reciprocal of time gives frequency so 1/22.2 usec equals 45 kHz. Since the upper end of the MMC101G horizontal frequency is about 39.3 kHz, the display will not appear correctly. In this case, there is only information for the first 22.2 microseconds of each line. Horizontal scan at 39.3 kHz is about 25.4 microseconds for each line, therefore all lines would be cut short by about 3.2 (25.4-22.2) microseconds. The result is a display not filled out in width and since the start of chassis scan would not coincide with the start of the video output scan, the familiar "sharks tooth" (torn) display would be seen.
Figure 4-4,
800x600 Timing @ 75 Hz Refresh Rate
Sync Processing and Scan Generation
27
Higher Resolutions (Not supported by all video cards)
When switching to higher resolutions if the scan system cannot provide the higher scan rates required, the display will never present an acceptable picture.
Figure 4-5,
1024x768 Display
The next example is a common computer display resolution of 1024x768 set at 60 Hz refresh. The vertical timing is 16.7 milliseconds (1/60) however now 768 lines must be drawn in that amount of time. 16.7 msec/768 equals 21.7 microseconds. Taking the reciprocal of the time gives a frequency or 46.08kHz which is the frequency horizontal scan must run at in order to display information properly. Since the upper end of the horizontal scan circuits of the MMC101G is about 39.3kHz, it will not be able to display this video setting.
Figure 4-6,
1024x768 Timing @ 60 Hz Refresh Rate
28
Sync Processing and Scan Generation But that is not necessarily the end of the problem. One standard for 1024x768 displays uses a 43 Hz interlace refresh rate. To run at 43 Hz interlaced, the vertical frequency must run at 86 Hz, which is within the MMC101G's effective vertical scan rate. But horizontal rate is still dependant on the number of lines that must be drawn on the screen during one frame. In this case because the display is interlaced, half the lines are drawn during each frame, giving us 384 (768/2) lines. Using the same math as in previous examples, 384 lines must be drawn in 11.6 milliseconds (1/86Hz). Therefore each horizontal line must be drawn in 30.2 microseconds (11.6mSec/ 384). This means horizontal scan must operate at 33.1KHz (1/30.2 microseconds) well within the capabilities of the MMC101G horizontal scan rate. The monitor would support this video setting.
Video Card Settings
In computer applications either horizontal scan rate or vertical scan rate (refresh) may be changed. Typically refresh is selected by the user and the horizontal rate is adjusted by the computer video adapter to present a full display. This is because horizontal scan runs at such a high rate, flicker in the horizontal direction is rarely a problem. However the vertical rate can be set slow enough the eyes are incapable of blending the repainted
Figure 4-7,
Typical Screen Resolution Selections
graphics together without a "flickering" effect. Therefore, most video cards allow the setting of screen resolution based on a vertical refresh rate comfortable to the user and according to the information being displayed. But also notice the video adapter allows many modes the MMC101G/MMC102(G) may not be capable of displaying. The user must have some knowledge of the scan capabilities of the monitor to make an educated decision on proper settings. Note color depth is dependent upon the video card, not the monitor. Most analog monitors, including the MMC101G/MMC102(G) are capable of infinite color depth.
Sync Processing and Scan Generation Conclusions from this exercise are two-fold. First, in computer deflection modes, for every change in vertical refresh, there must be a corresponding change in horizontal deflection rate. The monitor deflection system must be capable of changing both horizontal and vertical scan rates to adjust for each change. The final consideration is sync. It was previously stated that for the purpose of this discussion, sync timing would be ignored. And for the most part, the exercise works well without sync discussion. However, there are many standards for sync signals for computer monitors and if the MMC101G/MMC102(G) can not process sync, no matter what scan frequencies are available, it will not be able to present a normal picture.
Separate Horizontal: TTL Positive/Negative Separate Vertical: TTL
29
Sync Voltage Levels Polarity
Composite: TTL
Sync on Green: Analog level Video (Positive) 0.7 Vp-p Sync (Negative) 0.3 Vp-p
Positive/Negative Positive/Negative
Figure 4-8,
Computer Mode Sync Levels
Figure 4-8 lists the sync modes normally expected with standard computer video adapters. There are three standard sync modes depending upon the manufacturer of the video adapter. These are: l Separate, l Composite, l Sync on Green. Computer video normally consist of five signals. These are the three video signals (RGB) and two sync signals (HV) plus associated ground return paths. There are many variations of these five signals including all digital RGB signals rather than analog. The MMC101G/MMC102(G) is only capable of processing RGB analog signals. Sync signals are also not very "standard". Separate sync is as simple as the name implies. The horizontal and vertical sync signals are output on different connections. They are TTL levels (0-5Vp-p) but can be either positive or negative going. In addition the H&V sync signals do not have to be the same polarity. Horizontal may be positive going and vertical may be negative or vice-versa. Composite sync contains both H&V sync on the same connection. The monitor must be capable of separating the sync into its H&V components. Both signals must be either positive going or negative going. Sync on Green has a composite sync signal riding on the G portion of the RGB video signal. It is analogous to the YUV or YIQ broadcast format where all the sync rides on the Y signal. Currently, the MMC101G/MMC102(G) will accept only separate sync at TTL levels and at any polarity.
30
Sync Processing and Scan Generation
MM101 Sync Processing
Sync processing for the early MM101 was not covered in the original MM101 Technical Training Material. Following is a brief synopsis and overview of those circuits. If a computer input fails to lock in a proper display, always begin by confirming the (S)VGA mode output from the video adapter. Compare the output with the scan and sync modes compatible with the MM101 input circuits. If either horizontal, vertical or sync is not compatible, improper video display will result. Also remember color definition is dependant upon the video adapter. Computer video is input as RGB. If there is no color, the video adapter is not outputting a color signal. Also if there appears to be a single color missing always input a standard NTSC or SDTV signal. If the MM101 displays proper color under those conditions, the RGB processing circuitry of the MM101 is working properly.
Logic Nomenclature
TECH TIP
The MM101/MMC101G/MMC102(G) increasingly use digital logic for signal processing, switching and moving data back and forth between devices. Logic IC's and TTL have been used for a number of years in all consumer electronic devices however it is increasingly difficult to label all available information for an instrument on a simple diagram or piece of service data. Shorthand methods of describing and designating signals have become the norm. The initial MM101 Technical Training Manual included a brief tutorial on simple logic circuits and associated voltage levels. This discussion will center on nomenclature currently used in TCE Service Data whether paper or CDROM based. In troubleshooting scenarios it is important to know whether signal switching is selected on high or low logic levels. Service data provides the information using logic nomenclature. For instance, VCR/TV is terminology seen in many TCE documents. It indicates a logic switch where one level selects VCR and the other TV. It is commonly read and spoken as "VCR or TV NOT" and indicates the VCR selection is the default and when it is active the logic signal is high. Input "TV" is selected when the logic level switches to LOW and is referred to as an "active low" selection. Although a truth table is not generally used to convey the information, Figure 4-9 shows how one might look.
To Select: Use Logic: VCR 1 TV 0
Figure 4-9, VCR/TV Truth Table The normal indication might be VCR/TV. VCR would still be the default selection but TV would be selected with a logic HIGH.
To Select: Use Logic: VCR 0 TV 1
Figure 4-10, Normal VCR/TV Truth Table It is usually important for troubleshooting to indicate the default selection and this method allows schematics, whose print and screen space is very limited to show a technician what logic levels to expect for each input or output selection.
Sync Processing and Scan Generation
+5Vs 16 Vcc A 0 1 0 1 B 0 0 1 1
INPUT SELECT
31
+5Vs Part of U38303 6 Blanking
5 4 13 VERT Part of U38303 8 SEL_V 9 Part of U38303 3 SEL_H
OUTPUT NTSC NTSC VGA1 VGA2
NTSC V NTSC H
12 1 14 5 1 0 10 9
0 1 2 3
Part of U13103 13 Divider
54
Part of U13101 System Control
V Freq H Freq
VGA1 V VGA1 H VGA2 V VGA2 H 4Bh U38300 TCE2AU BUS Expander
15 2 11 4 3 2 3 HORZ 1 2
1
6
53
A U38304 CD4052 12 1 14 5 1 16 0 13 0 1 0 1
B 0 0 1 1
INPUT SELECT
OUTPUT 1H No SYNC 1H w/SYNC 2H No SYNC 2H w/SYNC
0 1 2 3
4 Run IIC Clock 3 Run IIC Data In 2 Run IIC Data Out
10 VGA2/VGA1 10 11 VGA/TV 9
CTRL A CTRL B U38301 CD4052
7 8
Sw_H +5Vs To Black Stretch Detect
15 13 14 NTSC/1HYPrPb To Black Stretch and YUV Blanking 12 16
VERT POLARITY HORZ POLARITY
+5Vs Q38304
15 2 11 4 3 CTRL A CTRL B 7 8 2 3
SYNC ENABLE 1H/2H CR38301 R38321 1MEG
10 9
Figure 4-11,
Sync Switching
Sync Processing Overview
Although at first glance, sync switching may seem intimidating remember it reduces to simple path switching and application of logic diagrams. All sync inputs are routed to U38301. Note there is no provision for composite sync at this point. All sync must be separated prior to switching. For the MMC101G/MMC102(G) there is no sync separation for the VGA inputs whether from a computer source or a set top decoder device. This means the MM(G) series is not compatible with composite sync from sources other than NTSC baseband or RF inputs. There are minor differences between the original MM101 and the MMC101G/MMC102(G) sync processing circuits. All sync switching is powered in standby mode to facilitate quicker sync detection at start-up. The actual input switching is done by commands from the microprocessor dependant upon the user selection. U38300 interprets the IIC data and converts it to logic output levels for three different functions. These are:
l Input switching, l Sync Polarity conversion and, l Sync enabling (black stretch defeat).
32
Sync Processing and Scan Generation
Sync Switching
U38300 receives IIC data commands from System Control and outputs a logic low or high to input switch U38301. Separate horizontal and vertical sync is available on the various input pins and switched to the dedicated horizontal (U38301-13) and vertical (U38301-3) output pins. The truth table for input switching is shown in Figure 4-12.
A 0 1 0 1 B 0 0 1 1
INPUT SELECT
OUTPUT NTSC NTSC VGA1 VGA2
0 1 2 3
Figure 4-12, U38301 Logic The A/B inputs are logic level on pins 9 and 10 and come from U38300-10 and U3830011.
Sync Polarity
The MM101 can process negative or positive going polarity, but requires positive polarity to function properly. All incoming sync is converted to positive going polarity for later use. This is accomplished using exclusive OR (XOR) logic gates. The microprocessor decides whether incoming sync is positive or negative going based upon the video input selection. A logic 0 or 1, depending upon the scan rate is placed on one of the XOR gate inputs via U38300-13 (Horizontal Polarity) and U38300-15 (Vertical Polarity). First understand that positive polarity means a high signal indicates the presence of the sync pulse. In negative polarity, the negative going pulse indicates the presence of sync. In both cases, 0 or no voltage is the reference level and the signals switch between 0 and +5V. In positive polarity, video is allowed during the time when the sync is zero. Sync would be at +5V. With negative polarity sync is indicated by 0V. Video is allowed when the waveform is at +5V. Figure 4-13 shows an example of the waveforms.
+5V 0V
Positive Sync
+5V 0V
Negative Sync Sync Pulse
Figure 4-13, Sync Polarity Waveforms
Sync Processing and Scan Generation For instance, if System Control expects to see negative polarity a logic 0 (LO) is placed on input A of the gate. Now only the top of the logic table is active. When the incoming sync signal is low (0V), there will be 0V output from the gate. When sync goes high (in this case indicating the presence of video), so does the output of the gate. If System Control selects positive polarity a logic 1 (HI) is placed on input A of the gate. Now only the bottom of the logic table is active. When the incoming sync signal is high (+5V), there will be no output from the gate. When sync goes low, the output of the gate goes high, effectively inverting the sync pulse. Since the concept may be difficult to visualize, Figure 4-14 includes a waveform logic table with the traditional logic table. The waveforms on input B are both 0-5V with the upper waveform normally high, going low to indicate sync (negative polarity) and the lower waveform normally low, going high to indicate sync (positive polarity).
A 0 0 1 1 B OUTPUT 0 1 0 1 0 1 1 0 Polarity Negative Negative Positive Positive
B A Part of U38303 C
A 0 +5V B OUTPUT
33
Figure 4-14, XOR Gate and Logic Table The positive polarity sync is then fed back to System Control through a divider network, U13103, where it is "counted" to place scan in the correct mode.
MMC101G/MMC102(G) Sync Switching
There have been several changes for the MMC101G/MMC102(G) from the original MM101. There may be minor component changes as field experience has warranted but there are several other changes due to the inclusion of a dedicated sync processor. Figure 4-15 is a block diagram of the sync switching circuitry. Input switching remains the same although incoming signals are placed on different pins. In the MM101 YPrPb sync was handled by the NTSC inputs. The MMC101G/MMC102(G) will be able to process 1H or 2.xH YPrPb and requires a separate sync signal path to provide the capability. The truth table for sync input switching is included. Switching is accomplished via IIC commands from System Control using a bus expander, U38300.
34
Sync Processing and Scan Generation
INPUT SELECT
A 0 1 0 1
B 0 0 1 1
OUTPUT 2H YPrPb VGA2 NTSC VGA1 12 1 14 5 15 2 11 2 3 HORZ 3 4 10 VGA1/NTSC 10 11 VGA2/Y PrPb 9 CTRL A CTRL B U38301 CD4052 7 8 5 1 2 1 0 13 VERT 10 9 +5Vs 16 Vcc 13 12
R38314 15K 1 Part of U38303 11 2 Part of U22407 TA1300AN Sync Processor
0 1 2 3
YPrPb V YPrPb H VGA2 V VGA2 H NTSC V NTSC H VGA1 V
Part of U38303 8 SEL_V
Part of U38303 3 SEL_H
4 VGA1 H 4 Run IIC Clock 3 Run IIC Data In 2 Run IIC Data Out 15 13 4Bh U38300 TCE2AU BUS Expander
Part of U38303 6 34 35
Part of U13101 System Control
V Freq H Freq
R38300 7.5K
VERT POLARITY HORZ POLARITY
Figure 4-15, MM101X/MM102 Sync Switching
MMC101 Sync Processing
Sync switching and processing has been simplified with the inclusion of a new sync processor IC, U22407. This is a TA1300AN IC first used in the MMC101G/ MMC102(G). It is a sync processor for multi-frequency scanning of video signals. It provides sync and deflection signals for horizontal and vertical scan circuits in multi-media monitor applications such as the MMC101G/MMC102(G). It is IIC bus compatible. Currently the sync outputs on pins 15 and 22 with pin 15 being horizontal and pin 22 vertical.
Sync Processing and Scan Generation
35
HD2 IN
1
H IN SWITCH
U22407
H FREQ DETECT SW
IIC MUTE
24
VIDEO MUTE
VD2 IN
2
23
H SYNC OUT (DAC2) VERT PULSE OUT SYNC 1 IN
HD1 IN
3
V INT H/V FREQ DETECT V INT
22
VD1 IN ANALOG GND AFC FIL
4
V IN SWITCH V FREQ DETECT SW
21
5
20
V SYNC OUT (DAC1) SYNC 2 IN
6
H AFC
HD POL H C/D
CLAMP PULSE H RAMP
Hf SW V C/D 2xfH V BLNK
19
H VCO
7
H VCO
18
H FREQ SELECT
Vcc
8
V BPP Vf SW
17
IIC CLOCK
IIC BUS DECODER
NOT USED
9
16
IIC DATA
FBP IN BLANKING PULSE OUT SANDCASTLE PULSE OUT
10
FBP/ BLNK H/V BLNK OUT
H BPP
CLAMP PULSE
H BLNK
H DUTY EXT V BLNK
H OUT
15
HORIZ OUT DIGITAL GND SANDCASTLE PULSE IN
11
14
12
CP SW CP/BPP OUT SCP SW SCP IN
13
Figure 4-16, U22407 Sync/Deflection Processor Figure 4-16 is a pinout of the Sync Processor, U22407. The following list includes individual descriptions of the pins. Some pins are not used in the MMC101G or MMC102(G) chassis. Those are identified as not used and grounded, or not used and tied to a supply voltage or other component. 1. 2. 3. 4. 5. 6. 7. HD2: ANALOG INPUT; 1Vp-p at the horizontal scan rate. Derived from incoming video signal. May be either positive or negative going. VD2: ANALOG INPUT; 1Vp-p at the vertical scan rate. Derived from incoming video signal. May be either positive or negative going. HD1: ANALOG INPUT; 1Vp-p at the horizontal scan rate. Derived from incoming video signal. May be either positive or negative going. VD1: ANALOG INPUT; 1Vp-p at the vertical scan rate. Derived from incoming video signal. May be either positive or negative going. ANALOG GND: Ground for IC analog components. AFC Filter: ANALOG INPUT; Varies horizontal frequency by voltage changes. H VCO: ANALOG INPUT; Horizontal Oscillator crystal connection.
36
Sync Processing and Scan Generation 8. 9. Vcc: Not Used: Supply Voltage, +9Vs Not used, grounded through C22422.
10. FBP:ANALOG INPUT; Flyback Pulse Input buffered from pin 15. 0-9Vp-p 11. Blanking Pulse: ANALOG OUTPUT; Horizontal and vertical blanking pulse output. Signal Level: 0-5Vp-p. (H: 5Vp, V: 2.5Vp) 12. SCP Out: ANALOG OUTPUT; Sand Castle Pulse output. Signal Level: 0-5Vp-p. (H: 5Vp, V: 2.5Vp) 13. SCP In: Digital Input. Not used, Grounded. 14. DIGITAL GND (Digital Ground): Ground for IC digital components. 15. HORIZ OUT: ANALOG OUTPUT;Horizontal Sync Output. Open Collector, 0-9Vp-p. 16. SDA (DATA IN/OUT): 0-5Vp-p DIGITAL INPUT/OUTPUT; IIC data I/O line.
17. SCL (Clock IN): DIGITAL INPUT; IIC clock input. 0-5Vp-p. 18. H FREQ SELECT: DIGITAL INPUT; Not Used, Grounded. Horizontal Frequency is bus-selected. 19. SYNC 2 IN: ANALOG INPUT; Composite Sync Input. 01Vp-p 20. V SYNC OUT: ANALOG OUTPUT; current not used, not connected. (DAC1), Open collector output
21. SYNC 1 IN: ANALOG INPUT; Composite Sync Input. 01Vp-p 22. VERT PULSE OUT: DIGITAL OUTPUT; Vertical sync output. 0-5Vp-p 23. H SYNC OUT: ANALOG OUTPUT; Open Collector output either horizontal or composite sync. 09Vp-p 24. VIDEO MUTE: DIGITAL OUTPUT; (DAC3), Open collector output used to provide video muting on bus command. NORMAL: MUTE: 0V 5V
Sync Processing and Scan Generation
37
SEL_H From U38303-3 Sync Switching SEL_V From U38303-8 Sync Switching SCP From U22300-2 Sync Separator
1 2 3 4 21
HD2 IN VD2 IN HD1 IN VD1 IN
U22407 Sync Proc VIDEO MUTE
24
MAIN VIDEO MUTE TO U16501-1
NORMAL: LOW MUTE: HIGH
PIP MUTE
23
PIP VIDEO MUTE TO U16501-8
NORMAL: LOW MUTE: HIGH
VERT OUT BLANKING PULSE OUT SANDCASTLE PULSE OUT H OUT 5 14
22
YPrPb V BLANKING TO U38301-12 2
Not Used YPrPb Composite Sync From YUV Input IIC Control From Run1 Bus
SYNC 1 IN 11
12 13 X U38304 CD4052 0 1 14
SCP OUT
19 17 16 10
SYNC 2 IN IIC CLOCK IIC DATA FBP IN
{
12
U22300 Video Proc
15
YPrPb H BLANKING TO U38301-1
2 1 Y 0 1 5 3 Z 15 25
BLANKING IN
0 1
4
24
CP BSP IN
MODE
0-4, 14,15 / 5-8 12
9 +9Vs R38369 10K 10
CTRL C 16 7 SCP From Deflection Processor U14350-2 +9Vr 19 26
CTRL B 11 CTRL A 8
U38300 Bus Expander
NTSC-YPrPb / VGA 16 VGA2-NTSC/VGA1-YPrPb 14
Q38326 Q38325
MODE 5-8 BLANKING
Figure 4-17, Sync Processing
Sync Processing
Sync processing becomes very complex but by understanding what the signals are and what they do, troubleshooting may be simplified. Figure 4-17 is a block diagram of the sync processing circuitry. Separated sync inputs 1 and 2 of sync processor U22407 are fed from the sync switching circuits discussed previously. These inputs are used only to detect the incoming sync frequency. Separate sync inputs 3 and 4 are derived from the sandcastle signal output from video processor U22300. Composite sync input 1, pin 21 is currently not used. Composite sync input 2 comes directly from the YPrPb rear panel input jacks. Sync for these type of signals is on the Y input. U22407 outputs several useful signals. Pins 23 and 24 carry mute signals to the Main and PIP video to blank video during scan preventing any video from showing up on the CRT during what should be blanking time. Pin 22 is the YPrPb vertical blanking pulse fed back to the sync switch, U38301-1. YPrPb horizontal blanking is generated from pin 15 and buffered before going to the sync switch. Pin 12 provides a sandcastle output based on the incoming sync pulses. This will be used for blanking in the main video processor, U22300.
38
Sync Processing and Scan Generation U22300 provides all video processing whether the RGB or YUV signal is selected and outputs the RGB drive for the cathodes. All sync and blanking must be routed to U22300 by the second sync switch, U38304. Switching for this device is more complex than a standard IC switch.
A 0 0 1 1 B 0 1 0 1 X 0 0 1 1 Y 0 1 0 1 Z 0 1 0 1
Figure 4-18, U38304 Truth Table Note that each switch, X, Y and Z is independent from the other and can have only one connection at a time. If X0 is connected, X1 must be disconnected. The table shows which connection is made from each switch depending upon the input switch logic state. For this application inputs B and C are connected reducing the logic choices. As an example, if logic input A is high (1) and B is low (0), switch X1, Y0 and Z0 are connected. Incoming blanking comes from the deflection processor, U14350 to U38304-5 for modes 0-4, 14 & 15, and to U38304-2 for modes 5-8. The sandcastle pulse output from Sync Processor, U22407-12 is input to U38304-3. The blanking pulse output from Sync Processor, U22407-11 is input to U38304-13. A sandcastle output from the main video processor, U22300-2 representing NTSC sync is input to U38304-12. The output of U38304-14 (switch X) is fed back to input pin 1.
Sync Routing
Routing the proper sync and blanking signals to the video processor becomes very sophisticated. Note the logic designations for the bus expander. U38300-14 may be high or low. When high, the default, it selects NTSC or YPrPb. When low it selects one of the VGA modes. U38300-16 completes the selection. If it is high, also the default, VGA2 or NTSC is selected. When low VGA1 or YPrPb is selected. Pin 12 picks between deflection modes 0-4, 14, 15 and mode 5-8. The truth table for pins 14 and 16 is shown in Figure 4-19.
U38300-16 NTSC-YPrPb (1) NTSC-YPrPb (1) VGA VGA
(0) (0)
U38300-14 VGA1-YPrPb (0) VGA2-NTSC (1) VGA1-YPrPb (0) VGA2-NTSC (1)
SELECTION (CTL A) YPrPb NTSC VGA1 VGA2
(1) (0) (1) (1)
Figure 4-19, U38300 Truth Table
Sync Processing and Scan Generation Note the only time the output of the truth table is actually "0" is when both pins of U38300 are high. Most mode switching is occurring between the video processor, U22300 and the sync switch, U38301. The sync processor is used to form a sandcastle and blanking pulse from separate H/V sync. In addition, U22407 pins 1 and 2 measure the incoming sync pulse to initially detect the frequency to set deflection mode.
39
Sandcastle
Switching may be slightly difficult to see but results in the video and deflection processor using a sandcastle pulse generated by the sync processor based on incoming signals during deflection modes 0, 4, 14 and 15. It uses the sandcastle pulse from the main deflection generator for deflection modes 1-3 and 5-8.
Blanking
Blanking is processed and switched much the same way except for variances during the different input selections. During deflection modes 0-4, 14 and 15 when a YPrPb, VGA1 or VGA2 signal is selected blanking comes from the sync processor U22407-11. If the input is NTSC, blanking is derived from the sandcastle pulse generated from the main video processor, U22300-2 and switched to U22300-25. In modes 5-8 blanking again comes from two different sources. During all input signals blanking is derived from the sandcastle pulse out the main deflection processor, U14350-2. The next few diagrams show the different routing taken by the sandcastle and blanking pulses generated by the main deflection processor, main video processor or the main sync processor.
SEL_H From U38303-3 Sync Switching SEL_V From U38303-8 Sync Switching SCP From U22300-2 Sync Separator
1 2 3 4 21
U22407 Sync Proc 24 HD2 IN VIDEO MUTE VD2 IN HD1 IN VD1 IN SYNC 1 IN SYNC 2 IN IIC CLOCK IIC DATA FBP IN 5 BLANKING 11 PULSE OUT SANDCASTLE 12 PULSE OUT H OUT 14 PIP MUTE 23
MAIN VIDEO MUTE TO U16501-1
NORMAL: LOW MUTE: HIGH
PIP VIDEO MUTE TO U16501-8
NORMAL: LOW MUTE: HIGH
VERT OUT
22
YPrPb V BLANKING TO U38301-12 2
Not Used YPrPb Composite Sync From YUV Input IIC Control From Run1 Bus
SCP OUT
19 17 16 10
{
12 13 2 YPrPb H BLANKING TO U38301-1 1 Y X
U38304 CD4052 0 1 0 1 14
U22300 Video Proc
15
25
BLANKING IN
5 3 0-4, 14,15 / 5-8 12 9 +9Vs R38369 10K NTSC-YPrPb / VGA 16 VGA2-NTSC/VGA1-YPrPb 14 10 Z
0 1
4
24
CP BSP IN
MODE
CTRL C 16 7 SCP From Deflection Processor U14350-2 +9Vr 19 26
CTRL B 11 CTRL A 8
U38300 Bus Expander
Q38326 Q38325
MODE 5-8 BLANKING
Figure 4-20, Sync Processing, NTSC Modes 0-4, 14-15
40
Sync Processing and Scan Generation
From U38303-8 Sync Switching
3
SCP From U22300-2 Sync Separator
HD1 IN VD1 IN SYNC 1 IN SYNC 2 IN IIC CLOCK IIC DATA FBP IN 5
PIP MUTE
23
PIP VIDEO MUTE TO U16501-8
NORMAL: LOW MUTE: HIGH
4 21
VERT OUT
22
YPrPb V BLANKING TO U38301-12 2
Not Used YPrPb Composite Sync From YUV Input IIC Control From Run1 Bus
SCP OUT
19 17 16 10
BLANKING 11 PULSE OUT SANDCASTLE 12 PULSE OUT 15 H OUT 14
YPrPb H BLANKING TO U38301-1 12 13 2 1 Y X
U38304 CD4052 0 1 14
{
U22300 Video Proc
0 1
15
25
BLANKING IN
5 3 0-4, 14,15 / 5-8 MODE 12 U38300 Bus Expander 9 +9Vs R38369 10K NTSC-YPrPb / VGA 16 VGA2-NTSC/VGA1-YPrPb 14 10 Z
0 1
4
24
CP BSP IN
CTRL C 16 7 SCP From Deflection Processor U14350-2 +9Vr 19 26
CTRL B 11 CTRL A 8
Q38326 Q38325
MODE 5-8 BLANKING
Figure 4-21, Sync Processing, NTSC Modes 5-8
SCP From U22300-2
HD1 IN
Sync Separator
4 21
VD1 IN SYNC 1 IN SYNC 2 IN IIC CLOCK IIC DATA FBP IN 5
VERT OUT
22
YPrPb V BLANKING TO U38301-12 2
Not Used YPrPb Composite Sync From YUV Input IIC Control From Run1 Bus
SCP OUT
19 17 16 10
BLANKING 11 PULSE OUT SANDCASTLE 12 PULSE OUT 15 H OUT 14
YPrPb H BLANKING TO U38301-1 12 13 2 1 Y X
U38304 CD4052 0 1 0 1 14
{
U22300 Video Proc
15
25
BLANKING IN
5 3 0-4, 14,15 / 5-8 MODE 12 U38300 Bus Expander 9 +9Vs R38369 10K NTSC-YPrPb / VGA 16 VGA2-NTSC/VGA1-YPrPb 14 10 Z
0 1
4
24
CP BSP IN
CTRL C 16 7 SCP From Deflection Processor U14350-2 +9Vr 19 26
CTRL B 11 CTRL A 8
Q38326 Q38325
MODE 5-8 BLANKING
Figure 4-22, Sync Processing, VGA-YPrPb Modes 0-4,14-15
Sync Processing and Scan Generation
41
From U38303-8 Sync Switching
3
SCP From U22300-2 Sync Separator
HD1 IN VD1 IN SYNC 1 IN SYNC 2 IN IIC CLOCK IIC DATA FBP IN 5
PIP MUTE
23
PIP VIDEO MUTE TO U16501-8
NORMAL: LOW MUTE: HIGH
4 21
VERT OUT
22
YPrPb V BLANKING TO U38301-12 2
Not Used YPrPb Composite Sync From YUV Input IIC Control From Run1 Bus
SCP OUT
19 17 16 10
BLANKING 11 PULSE OUT SANDCASTLE 12 PULSE OUT 15 H OUT 14
YPrPb H BLANKING TO U38301-1 12 13 2 1 Y X
U38304 CD4052 0 1 14
{
U22300 Video Proc
0 1
15
25
BLANKING IN
5 3 0-4, 14,15 / 5-8 12 9 +9Vs R38369 10K NTSC-YPrPb / VGA 16 VGA2-NTSC/VGA1-YPrPb 14 10 Z
0 1
4
24
CP BSP IN
MODE
CTRL C 16 7 SCP From Deflection Processor U14350-2 +9Vr 19 26
CTRL B 11 CTRL A 8
U38300 Bus Expander
Q38326 Q38325
MODE 5-8 BLANKING
Figure 4-23, Sync Processing, VGA-YPrPb Modes 5-8
Low Level Deflection Processing
There are no major differences between the original MM101 Low Level Deflection Processing and the MMC101G/MMC102(G). Most changes are component value changes, algorithm (software control) or elimination of unnecessary components. All low level deflection processing is contained on a SIP board identical to the previous chassis design. For a more detailed explanation of low level deflection processing refer to the previous publication "MM101 Technical Training Manual", TCE Publication #T-MM101-1.
Horizontal Scan Loss
The Deflection Processor, U14350, monitors horizontal scan for proper operation by looking at the horizontal flyback pulse on pin 1. If it disappears, indicating missing horizontal scan, all scan outputs will be stopped and an error message logged to the microprocessor.
Geometry Correction
Most normal geometry correction is done internally by the Deflection Processor. These include, E/W Pincushion correction, symmetry (trapezoidal), DC offset (width) and corner correction. The correction waveform is output from pin 6 and modulates the Scan B+ ZVS and Series Pass supplies depending upon which scan mode the chassis is in. Again, this takes advantage of the premise that raster width has a direct relationship to Scan B+. By varying Scan B+ at the precise time, the raster may be made wider or narrower.
42
Sync Processing and Scan Generation Figure 4-24 is a pinout of the Deflection Processor, U14350. The following list includes individual descriptions of the pins. Some pins are not used in the MM101 chassis. Those are identified as either not used and grounded, or not used and tied to a supply voltage. 1. HPULSE (Horizontal Flyback): ANALOG INPUT; 20Vp-p at the horizontal scan rate. Derived from the flyback portion of horizontal output transformer. DSC (Digital Sandcastle): A/D OUTPUT; Two level signal. Digital H&V blanking signal at 2.5Vp-p. Video clamping signal at 4.5Vp-p. D/A INPUT; >0.5V derived from Vertical Flyback indicating presence of vertical scan. OVP (OverVoltage Protect): Not used, grounded. Analog Ground: Ground for IC analog components. LLCS (Line Locked Clock Select): LOGIC INPUT; Selects line frequency of Deflection Processor. LOW: Low Frequency (1H) Select HIGH: High Frequency (>2H) Select E/W (East/West Geometry): width reference. 0-5Vdc ANALOG OUTPUT; Geometry correction waveform for
1 2 3 4 5 6 7 8 9 10 H Flyback (H PULSE) Digital SandCastle OverVoltage Protect Analog Ground Horizontal Output Off Center Shift SCL 20 19 18 17 16 15 14 13 12 11
Line Clock Select E/W EHT
U14350 DEFLECTION SDA PROCESSOR
Vcc Digital Ground Line Lock Clock In Horizontal Sync Vertical Sync Vertical Output A
2.
Resistive Conversion Flash Detect Vertical Output B
Figure 4-24, Deflection Processor Pinout
3. 4. 5.
6. 7.
EHT: Extra High Tension used to allow compensation of raster size vs high voltage supply. Not used, grounded. However, the EEPROM bit for this setting should be zero. If it is not, the raster will shrink. Initialization of the EEPROM would be indicated. External Resistive Conversion: Resistor sets the reference current. Scales the amplitudes of the various geometry correction signals from the E/W output, VOUT A and VOUT B. FLASH: Reset soft start initiation. Not used, grounded.
8. 9.
10. VOUTB (Vertical Output B): ANALOG OUTPUT; Vertical Output waveform. 11. VOUTA (Vertical Output A): ANALOG OUTPUT; Vertical Output waveform. 12. VERT IN (Vertical Sync In): microprocessor. 5Vp-p ANALOG INPUT; Vertical Sync signal from main
13. HORIZ IN (Horizontal Sync In): Not used, grounded. 14. LLC (Line Locked Clock In): DIGITAL INPUT; Line Locked Clock input locked at 432 or 864 times the horizontal frequency. 15. DIG GND (Digital Ground): Ground for IC digital components.
Sync Processing and Scan Generation 16. Vcc: Supply Voltage, +8Vr 17. SDA (DATA IN/OUT): DIGITAL INPUT/OUTPUT; IIC data I/O line. 0-5Vp-p 18. SCL (Clock IN): DIGITAL INPUT; IIC clock input. 0-5Vp-p. 19. OFCS (Off Center Shift Out): ANALOG OUTPUT; Horizontal Rate output locked to incoming Horizontal Sync by the PLL. 04.5Vp-p 20. HORIZ OUT (Horizontal Output): Output waveform. Horizontal
1 Vcc Voltage Reference SDA LIN SW Vertical Offset 2H Vcc 16
43
2
15
Figure 4-25 is a pinout of the Deflection DAC, U24800. It has eight channels of Digital to Analog converters, individually programmable via the IIC bus. Maximum output voltage range is from +0.1 to +10VDC. The following list includes individual descriptions of the pins. Some pins are not used in the MM101 chassis. Those are identified as either not used and grounded, or not used and tied to a supply voltage. 1. 2. 3. 4. 5. 6. 7. 8. 9. Vcc: Supply Voltage, +12Vr
3
14
4
SCL Digital Ground Not Used Digital Ground Analog Ground
U24800 DEFLECTION DAC
VCO Freq 1H SW
13
5
12
6
Width Alignment 2H PLL Offset S CAP SW
11
7
10
Voltage Reference: ANALOG INPUT; Reference for the DAC's. +10V
8
9
SDA (DATA IN/OUT): DIGITAL INPUT/ Figure 4-25, Deflection DAC Pinout OUTPUT; IIC data I/O line. 0-5Vp-p SCL (Clock IN): DIGITAL INPUT; IIC clock input. 0-5Vp-p. DIG GND (Digital Ground): Ground for IC digital components. NC: Not Used, no connections. DIG GND (Digital Ground): Ground for IC digital components. Analog Ground: Ground for IC analog components. S CAP SW: DAC 0 ANALOG OUTPUT; Tri-State output for S Cap switching.
10. 2H PLL Offset: DAC 1 ANALOG OUTPUT; Used to shift the VCO frequency for the High voltage generator. 11. Width Alignment: DAC 2 ANALOG OUTPUT; Width signal. 12. 1H SW: DAC 3 ANALOG OUTPUT; 1H Switch to 1H/2H Latch 13. VCO Freq: DAC 4 ANALOG OUTPUT; DC voltage used to fine tune the VCO for the Line Locked Clock PLL. 14. 2H Vcc: DAC 5 ANALOG OUTPUT; Switch for Scan Power Supply. 15. Vertical Offset: DAC 6 ANALOG OUTPUT; Vertical DC offset voltage. 16. LIN SW: DAC 7 ANALOG OUTPUT; Dual State output for Linearity Coil Switching.