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TVPO 2066 TV Controller with On-Screen Display for TV Receivers

Edition August 24, 1992 6251-327-3E

ITT Semiconductors

TVPO 2066
Contents Page 3 3 3 4 4 4 5 5 5 5 5 5 5 6 7 8 8 8 8 8 9 9 9 9 10 11 12 14 14 15 16 17 17 18 19 20 20 21 Section 1. 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 2.7. 2.8. 2.9. 2.9.1. 2.9.2. 2.9.3. 3. 3.1. 3.2. 3.3. 3.4. 3.5. 4. 4.1. 4.2. 4.2.1. 4.2.2. 4.3. 4.4. 4.5. 4.5.1. 4.5.2. 4.5.3. 5. 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. Title Introduction The Functional Blocks of the TVPO 2066 The 8049 Microcomputer The Remote­Control Decoder The Mains Flip­Flop and Reset Circuit The IM Bus and Non­Volatile Memory The Clock Generator and the Sequence Control The D/A Converters for the Analog Outputs The Tuning Voltage Generator The Ports The On­Screen Display Outputs and Inputs for the OSD Display Format Display Control Description of Hardware Component Registers Registers for Infrared Control Register for Port 3 Registers for IM­Bus Control Registers for Analog Outputs & MAINS­Control Registers for On­Screen Display Specifications Outline Dimensions Pin Connections 40­Pin DIL Package 44­Pin PLCC Package Pin Descriptions Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Characteristics Appendix DAC Poly­Counter Code On­Screen Display Format Character Set Programmed Versions of TVPO 2066 User Options Application Circuit

2

TVPO 2066
TV­Controller with Integrated On­Screen Display Ability 1. Introduction In comparison to the older TVPO 2065 hardware, the port 3 of the TVPO 2066 consists of 6 x 12 V/2 mA open­ drain outputs instead of 5 V/25 mA open­drain outputs. "TVPO 2066" is the name of the unprogrammed hardware. The programmed versions will be called: ­ TVPO 2066­Axx ­ TVPO 2066­Dxx for analog TV­sets for digital TV­sets 2. The Functional Blocks of the TVPO 2066 The hardware components of the TVPO 2066 are: ­ 8048­core, fully compatible to 8048 instruction set ­ 10K ROM, 256 byte RAM ­ four 64 steps analog output to control vol., color etc. ­ single 4032 steps analog output for controlling of a VS­tuner ­ IR decoder for ITT­IR (remote control with IRT 1250/60) ­ mains flip­flop for standby mode ­ IM­bus interface for non­volatile memory and devices of DIGIT 2000 system for digital video­processing. ­ fast counter input (T1) for automatic search (for analog TV­sets) ­ 12 digital combined inputs/outputs (8 or 10 for DIL­ package) ­ 8 digital outputs ­ integrated 12­digit on­screen display 2.1. The 8049 Microcomputer For the description of the commands and characteristics of the 8049, please refer to the CCU 2030, CCU 2050, CCU 2070 data sheet. The 8049 provides separate address space for program, data, in/out, and external data. The ROM is organized in banks of 2 K Bytes. Bank 0 occupies the addresses 0 to 2047. The other banks (10, 11, 12, 13) share the addresses 2048 to 4095. The different banks are selected through the bank select register 15 as described for the CCU 2070 in the CCU 2030, 2050, 2070 data sheet. Banks 14 through 17 of the CCU 2070 are not available in the TVPO. The data and control registers of the TVPO's peripheral units are located in the address space of external data.

with the version­no. xx. Application diagrams and descriptions of different software versions are available in additional data sheets. The TVPO 2066 is an intelligent microcomputer in N­ channel MOS technology. On one silicon chip, it contains all operating and tuning functions of a modern TV receiver. Thus, along with the non­volatile memory (MDA 2062, NVM 3060), the SAA 1250, IRT 1250 or IRT 1260 remote­control transmitter and the TBA 2800 preamplifier this offers a very economic solution for TV receivers with on­screen display and voltage synthesizer. The device is available in 44­pin PLCC package and 40­pin DIL package. The PLCC version has 4 pins more for digital combined inputs/outputs.

Control Input/Output for Keyboard and Standard, etc.

IM­Bus and Memory Interface

Tuning Signal Generator

four D/A Converters

Remote Control

Mains FF

Reset Circuit

Clock Oscillator

On­Screen Display

8049 ROM RAM

Fig. 1­1: Functional block diagram of the TVPO 2066

3

TVPO 2066
They are accessed by the "Move External" instruction (MOVX). Electrically, the connection is provided by the lines DB0 to DB7, RD, WR, and ALE. These connections of the 8049 microcomputer are not available during normal operation. In "Test Mode" (EA = 5 V or EA = 12 V), some pins are switched so that the TVPO's peripherals can be accessed from the outside via DB0 to DB7. In normal operation, only P2 of the 8049's original ports remains unchanged. During test operation, RD, WR, ALE and PSEN are connected to P24 to P27 (compare CCU 2030, CCU 2050, CCU 2070 data sheet). 2.2. The Remote­Control Decoder In the already mentioned standby mode, and also during normal operation, the remote­control decoder expects infrared­transmitted signals that were transmitted by the SAA 1250, IRT 1250 or IRT 1260 remote­control transmitter IC, received by an infrared photo diode, and amplified by the TBA 2800 infrared preamplifier IC. The decoder frees the remote­control signal from interference and decodes each command word that is recognized as correct. A valid command word is made available to the microcomputer by way of two registers. No interrupt is initiated. Rather, it is the task of the program to continuously check the infrared registers. A command word transmitted via infrared consists of 10 bits ­ four address bits and six data bits. These two parts of the command word are provided in two different registers. Bit 7 in the address register is low when a valid command word is detected. When the data word is read, both infrared registers are cleared. It is possible to mask­program which infrared commands also carry the power­on information and switch the TVPO from standby to full operation. For this purpose, up to five groups of commands within a binary decoder matrix are programmable for one infrared address (compare CCU 2030, CCU 2050, CCU 2070 data sheet). 2.3. The Mains Flip­Flop and Reset Circuit Mains flip­flop and reset circuit operate from the standby supply. After switching on the standby supply it takes 100 ms at most until the TVPO is in full standby operation. The Mains output is controlled by the mains flip­ flop. In the "Mains off" position the output is high. The mains flip­flop is set by means of the infrared "Mains on" commands or by an active low level applied to the Mains output for at least 20 µs. A reset for the mains flip­flop is generated whenever: 1. The standby supply voltage is less than approx. 3.5 V (e.g. during power­on) 4 2. The microcomputer executes a "Mains off" command. The microcomputer clears the mains flip­flop by writing a 1 into bit 3 of the external register 13. In order to properly charge the stray capacitances at the Mains output, the mains flip­flop remains blocked in the "Mains off" position for 16 ms after any reset. After this time has elapsed, the TV set may be turned on again. With no Reset option set (compare CCU 2030, CCU 2050, CCU 2070 data sheet), the mains flip­flop is also reset by any Reset signal going low. The TVPO­internal Reset', which is different from the externally­applied Reset is high only when both Mains is in the low state and Reset is at high level. Two options are mask­programmable in this respect: Reset 1: The Reset signal, going low, does not reset the mains flip­flop. If the customer does not specify, this option will be set as default. Reset 2: The TVPO­internal Reset' is identical to the Reset signal and independent of the state of the mains flip­flop. Resetting the mains flip­flop clears the remote­control decoder. The other parts of the TVPO are cleared by the TVPO­internal Reset' signal via the Reset input. Delaying the Reset signal with respect to the VDD supply voltage is done by an external RC network at the Reset input. The input voltage of the regulator for the 5 V VDD supply voltage should be monitored to prevent the system's circuits from resetting improperly and the NVM 3060 EEPROM from programming false data. With no Reset option set, any spike or excessive noise present on the Reset line may cause the mains flip­flop to be reset. In such cases, a ceramic filter capacitor should be provided near the Reset pin. 2.4. The IM­Bus and Non­Volatile­Memory It is by means of this part of the circuit that the TVPO 2066 communicates with the non­volatile memory (MDA 2062 or NVM 3060) which stores the tuning and analog data, acquired during the Memo procedure and the options. The IM­Bus consists of three lines Clock, Ident and Data. Clock and Ident are unidirectional signals from the TVPO 2066 to the memory (and to the VSP­processor in case of a digital TV set), and Data is bidirectional for transferring the data in both directions. In addition, the MDA 2062 (not the NVM 3060) requires a memory clock signal which is issued from the TVPO 2066 (approx. 1 kHz). All these signals on the IM­Bus have TTL level. In the nonoperative state all three bus lines are high. The start of a telegram is initiated when Ident and Data are low. Data takeover occurs at the positive edge of Clock. For a detailed description of the IM­ Bus protocol please refer to the data sheet of the MDA 2062 or NVM 3060.

TVPO 2066
2.5. The Clock Generator and the Sequence Control For the purpose of generating the clock signals required to operate the TVPO 2066 the chip contains an oscillator which is designed for crystals in the frequency range from 3.5 to 4.5 MHz. For the exact requirement of "off­ timer" and "sleep­timer" functions, a 4 MHz crystal is needed. The crystal is connected to the `Xtal' input. All timing specification in this data sheet relate to a crystal frequency of 4 MHz. With other crystal frequencies, there will be corresponding variations. ues (volume, brightness etc.) on a TV screen. The TVPO 2066 software controls the OSD through a set of 16 external write registers. The TVPO 2066 delivers four additional output signals: ­ R_out ­ G_out ­ B_out ­ FB_out character signal red character signal green character signal blue fast blanking (1 Vpp) (1 Vpp) (1 Vpp) (TTL level)

2.6. The D/A Converters for the Analog Outputs The TVPO 2066 provides four analog outputs for adjustment of the TV's basic settings (e.g. volume and for analog TV sets additional brightness, contrast and color saturation). These control voltages are made available as pulse/pause modulated signals, where the ratio can be varied in 64 steps. The needed DC level signal is obtained by means of a simple RC lowpass filter.

Fast blanking is used for switching between video and OSD signals and shows the validity of the R, G, B outputs. For synchronization and to place the display, the TVPO 2066 needs two additional input signals: ­ H_in ­ V_in horizontal synchronization vertical synchronization (TTL level) (TTL level)

2.7. The Tuning Voltage Generator The tuning voltage for the capacitance diodes of the TV tuner is generated as a pulse/interval modulated signal by a modified rate multiplier. The range of variation of the pulse/interval ratio extends from 0 (no pulses) to infinity (continuous signal) with a resolution of 4032 steps. At a clock frequency of 4 MHz the basic period of the rate multiplier is 0.5 ms which results in tolerable filter expenditure.

2.9.2. Display Format The OSD generates a rectangular display block, which contains 2 rows of 6 characters each (see Fig. 2­1). The characters are addressed depending on their position within this display block. Each address is attached to one TVPO 2066 register. The content of each register describes the character type and its color.

2.8. The Ports The TVPO 2066 has two ports (Port 2 and Port 3) which are used by the software versions as control outputs/inputs for a keyboard, band selection, multi­standard indicators, multi­video indicators and AFC switch. The PLCC version of the TVPO 2066 has in addition four pins of Port 1 (P14...P17). The DIL version of the TVPO 2066 is also available in other pinnings: the D/A converter DA3 and DA4 can be exchanged to port input/outputs. DA3 to Port 1, Bit 5 (P15) and DA4 to Port 1, Bit 6 (P16). This possibility is very useful in digital TV sets, because in this case only one D/A converter is needed for volume control.

0 0000 8 1000

1 0001 9 1001

2 0010 A 1010

3 0011 B 1011

4 0100 C 1100

5 0101 D 1101

(Hex) (Bin) (Hex) (Bin)

Fig. 2­1: On­Screen Display Block A character is displayed in 5 x 7 dot matrix format, which is stored in the character ROM. The size of one dot can be programmed to 4 different values (size = 1, 2, 3, 4). ­ character format ­ dot format vertical = 5 x 7 dot = 2 lines x size

­ dot format horizontal = 2 x T0 x size T0 is the duration of one clock period of the system clock (CLK = 4 MHz ! T0 = 0.25 ns). To make the characters easier to see without increasing the storage requirement, a smoothing algorithm is implemented. The space between two diagonal dots is filled with one pixel. Thus the character appears in a 10 x 14 matrix format. 5

2.9. The On­Screen Display 2.9.1. Outputs and Inputs for the OSD The OSD is an additional hardware module on the TVPO 2066 chip, which allows the display of 12 different characters such as the program number and analog val-

TVPO 2066
Dots Row 1­Line1/2 Row 2­Line 3/4 Row 3­Line 5/6 Row 4­Line 7/8 Row 5­Line 9/10 Row 6­Line 11/12 Row 7­Line 13/14 1 2 3 4 5 12345678910 2.9.3. Display Control The interface between TVPO 2066 and OSD consists of 16 external write registers in which the TVPO 2066 software can store the structure, size and position of the display (see also Table 3­1). There are 32 different character types (C4...C0) in 8 colors (R, G, B) available. One special character is the `display off code'. In this case the display is switched off for one character. The remaining 31 codes are used as address for the character ROM which stores 31 characters represented in a 5 x 7 matrix format. It is possible to use 3 kinds of background modes. 1. No Background Only the character itself is laid over the TV picture on those points where the character matrix are set. A blank character for instance is not visible. 2. Square Background The whole display block is visible in the desired background color. The characters differ from the background by use of another color. Only the `display off code' switches off the background at the concerning character position. 3. Fringe Background This function creates a fringe of one pixel around and inside of each character. The color of the fringe is programmable. Only this fringe and the character itself is laid over the TV picture. The display control bits are explained in the next chapter.

Fig. 2­2: Character smoothing

­ pixel format vertical ­ pixel format horizontal

= 1 line x size = T0 x size

The horizontal space between two characters is 1 dot, the vertical space is 2 dots. A fringe of 1 dot lies around the 12 characters. The overall size of the display block is: ­ block format vertical ­ block format horizontal = 18 dot = 37 dot

The start position of the display's left, upper corner on the TV screen is specified by two registers and can be programmed in steps of 18 video lines, respectively 12 clock periods.

­ start position vertical ­ start position horizontal

= 18 lines x Vpos = 12 x T0 x Hpos

6

TVPO 2066
3. Description of Hardware Component Registers Table 3-1: Registers of hardware components (x=`0' or `1') Register Address 1 2 3 7 8 9 10 11 12 13 16 17 18 19 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Register Contents IR­ADDR. IR­COMM. PORT3 IMB­ADDR. IMB­DATH IMB­DATL IMB­CTRL. TUNE­VL TUNE­VH MAINS­FF. DAC 1 DAC 2 DAC 3 DAC 4 CHAR 0 CHAR 1 CHAR 2 CHAR 3 CHAR 4 CHAR 5 CHAR 8 CHAR 9 CHAR A CHAR B CHAR C CHAR D SIZE/Vpos Hpos Mode Test Format 3 A3 C3 B3 A3 B11 B3 C3 x T7 MOF B3 B3 B3 B3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 V3 H3 CR0 SM

7 CR 0 B7 A7 B15 B7 BB T3 T11 x x x x x R R R R R R R R R R R R S1 x BGR RO

6 0 0 B6 A6 B14 B6 x T2 T10 x x x x x G G G G G G G G G G G G S0 x BGG GO

5 0 C5 B5 A5 B13 B5 x T1 T9 x x x x x B B B B B B B B B B B B x x BGB BO

4 0 C4 B4

2 A2 C2 B2 A2 B10 B2 C2 x T6 x B2 B2 B2 B2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 V2 H2 SQ T0

1 A1 C1 B1 A1 B9 B1 C1 x T5 x B1 B1 B1 B1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 V1 H1 FR TM

0 A0 C0 B0 A0 B8 B0 C0 x T4 x B0 B0 B0 B0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 V0 H0 DI x

A4 B12 B4 x T0 T8 x B4 B4 B4 B4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 x H4 CRF FBO

7

TVPO 2066
3.1. Registers for Infrared Control Register 1: Infrared Address (READ only) A0 ...A3: Address CR : 0 = valid command received 1 = no command received Register 18: Digital/Analog converter Output 3 (WRITE only) B0...B5: Input of DAC3 Register 19: Digital/Analog converter Output 4 (WRITE only) B0...B5: Input DAC4 The DAC's of reg. 16...19 with a polynomial code shown in Table 5­1. 3.5. Registers for On­Screen Display 3.2. Register for Port 3 Register 3: Port 3 (WRITE only) B0...B7 : Set status of port 3, Bit 0...7 3.3. Registers for IM­Bus Control Register 7: IM­Bus address (WRITE only) A0...A7 : IM­Bus address 0...255 Register 8: IM­Bus data high (READ/WRITE) B8...B15: IM­Bus data, bit 8...15 Register 9: IM­Bus data low (READ/WRITE) B0...B7: IM­Bus data, bit 0...7 Register 10: IM­Bus control (READ/WRITE) C0...C3: IM­Bus control (READ/WRITE) C3 1 1 1 0 C2 1 1 0 1 C1 0 1 1 1 C0 1 0 1 1 Read Read Write Write 8 bit 16 bit 8 bit 16 bit Register 45: Register 46: Register 32...43:C0...C4: Character to be displayed R, G, B: RGB­color of character to be displayed Register 32: Character 0 of OSD (WRITE only) Register 33: Character 1 of OSD (WRITE only) Register 34: Character 2 of OSD (WRITE only) Register 35: Character 3 of OSD (WRITE only) Register 36: Character 4 of OSD (WRITE only) Register 37: Character 5 of OSD (WRITE only) Register 38: Character 8 of OSD (WRITE only) Register 39: Character 9 of OSD (WRITE only) Register 40: Character A of OSD (WRITE only) Register 41: Character B of OSD (WRITE only) Register 42: Character C of OSD (WRITE only) Register 43: Character D of OSD (WRITE only) Register 44: OSD size and vertical position (WRITE only) V0...V3: vertical position S0...S1: size 1...4 OSD horizontal position (WRITE only) H0...H4: horizontal position OSD Mode (WRITE only) DI : 0 = OSD off, 1 = OSD on (set 0 by power­on reset) SQ, FR: 00 = no background 01 = fringe background 1x = square background CR0 : 1 = char. code 0 is 1st char. 0 = char. code 0 is blank CRF : 1 = char. code 1F is 32nd char 0 = char. code 1F is display off BGx : x = RGB, 1 of 8 background colors OSD Test (WRITE only) TM : 1 = test mode on (set 0 by power­on reset) T0 : 0 = RGB­outp. sync to TVPO clock 1 = RGB­outp. sync to hor. blanking SM : 1 = Smoothing off FB0 : 1 = Fast­Blank. output disabled x0 : x = RGB 1 = RGB output disabled (all bits are set 0, if TM is set 0)

Register 2: Infrared Command (READ only) C0...C5: Command

3.4. Registers for Analog Outputs & MAINS­Control Register 11: Tuning Voltage (WRITE only) T0...T3 : LSB's of DAC­Input Register 12: Tuning Voltage (WRITE only) T4...T11: MSB's of DAC­Input DAC worked with binary (dual) code Range is 0...4031 dec. = 0...FBF hex. Register 13: Mains Flipflop (WRITE only) MOF: Mains off Register 16: Digital/Analog converter Output 1 (WRITE only) B0...B5: Input of DAC1 Register 17: Digital/Analog converter Output 2 (WRITE only) B0...B5: Input of DAC2 8

Register 47:

TVPO 2066
4. Specifications 4.1. Outline Dimensions

Fig. 4­1: TVPO 2066 in 40­pin DIL Package 20 B 40 according to DIN 41866 Weight approx. 6 g Dimensions in mm
2.4 1.2 x 45° 0.45 +0.1 6 7 2 1 40 39 10 x 1.27 = 12.7 ± 0.1 1.27± 0.1 1.2 x 45° 2.4 16.5 ± 0.1 0.1

17 18 17.4 +0.25 28

29 1.9 1.5 4.05 4.75 ± 0.15

Fig. 4­2: TVPO 2066 in 44­pin PLCC Package Weight approx. 2.2 g Dimensions in mm

0.254

4.2. Pin Connections

8 9

P27: Port P2, Bit 7 Vstb: Standby Supply Voltage GND: Ground, 0 Vsup: Supply Voltage Xtal: Oscillator Input T1: T1 Input Clck: Memory Clock Output Reset: Reset Input Mains: Mains Switch Input/Output EA (normally at GND) 9

4.2.1. 40­Pin DIL Package 1 2 3 4 5 6 7 Vin: Vertical Blanking Pulse Input Hin: Undel. Horizontal Blanking Pulse Input DA3: Analog 3 Output (P15: Port P1, Bit 5) DA4: Analog 4 Output (P16: Port P1, Bit 6) P24: Port P2, Bit 4 P25: Port P2, Bit 5 P26: Port P2, Bit 6

10 11 12 13 14 15 16 17

10 x 1.27 = 12.7 ± 0.1

17.4+0.25

16.5 ± 0.1

0.711

1.27± 0.1

TVPO 2066
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 IMD: IM Bus Data Input/Output IMI: IM Bus Ident Output IMC: IM Bus Clock Output DA1: Analog 1 Output DA2: Analog 2 Output IR: Infrared Remote Control Input VS: Tuning Voltage Output P30: Port P3, Bit 0 P31: Port P3, Bit 1 P32: Port P3, Bit 2 P33: Port P3, Bit 3 P34: Port P3, Bit 4 P35: Port P3, Bit 5 P36: Port P3, Bit 6 P37: Port P3, Bit 7 P20: Port P2, Bit 0 P21: Port P2, Bit 1 P22: Port P2, Bit 2 P23: Port P2, Bit 3 R_out: RED Output G_out: GREEN Output B_out: BLUE Output FB_out: Fast Blanking Pulse Output 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 4.2.2. 44­Pin PLCC Package 1 2 3 4 5 6 10 Vsup: Supply Voltage GND: Ground, 0 Vstb: Standby Supply Voltage P27: Port P2, Bit 7 P26: Port P2, Bit 6 P25: Port P2, Bit 5 31 32 33 34 35 36 37 P24: Port P2, Bit 4 P17: Port P1, Bit 7 P16: Port P1, Bit 6 P15: Port P1, Bit 5 P14: Port P1, Bit 4 Hin: Undel. Horizontal Blanking Pulse Input Vin: Vertical Blanking Pulse Input FB_out: Fast Blanking Pulse Output B_out: BLUE Output G_out: GREEN Output R_out: RED Output P23: Port P2, Bit 3 P22: Port P2, Bit 2 P21: Port P2, Bit 1 P20: Port P2, Bit 0 P37: Port P3, Bit 7 P36: Port P3, Bit 6 P35: Port P3, Bit 5 P34: Port P3, Bit 4 P33: Port P3, Bit 3 P32: Port P3, Bit 2 P31: Port P3, Bit 1 P30: Port P3, Bit 0 VS: Tuning Voltage Output IR: Infrared Remote Control Input DA2: Analog 2 Output DA1: Analog 1 Output DA4: Analog 4 Output DA3: Analog 3 Output IMC: IM Bus Clock Output IMI: IM Bus Ident Output

TVPO 2066
38 39 40 41 42 43 44 IMD: IM Bus Data Input/Output EA (normally at GND) Mains: Mains Switch Input/Output Reset: Reset Input Clck: Memory Clock Output T1: T1 Input Xtal: Oscillator Input Pin 30 ­ Tuning Voltage Output Fig. 4­9 shows the diagram of this push­pull output. Pin 30 supplies the tuning voltage for the capacitance diodes of the TV tuner in the shape of a pulsewidth­modulated signal. After amplification by an external transistor, the tuner DC voltage is derived by multiple RC filtering. A temperature­compensated Zener diode ZTK 33 must be provided for stabilizing the tuning voltage against variations of supply voltage and ambient temperature. Pin 31 ­ IR: Remote­Control Input The internal configuration of this pin is shown in Fig. 4­10. Via an external coupling capacitor of 10 nF, the remote­control signal, amplified by the TBA 2800 preamplifier IC, is fed to the remote­control decoder. The input is self­biasing to approximately 1.4 V, and the input DC resistance is approximately 150 kOhm. For highest input sensitivity, this pin must not be loaded resistively. A small capacitor connected from pin 31 to ground can be useful to suppress steep transients. Pins 32 to 35 ­ Analog Outputs These pins are open­drain outputs with diagram shown in Fig. 4­11. They supply the squarewave signals whose variable pulse/interval ratio is described in section 2.5. These signals serve for actuating the analog control elements. External pull­up resistors are required to produce the squarewave output signals. Pins 36 to 38 ­ IM Bus Connections The internal configuration of these pins are shown in Figs. 4­12 and 4­13. Via these pins, the TVPO 2066 is connected to the IM bus (see section 2.3.). This bus interlinks the TVPO 2066 and the non­volatile memory. The ident and clock outputs are unidirectional (see Fig. 4­12). The data pin acts as input and output for reading and writing data (Fig. 4­13). Pin 40 ­ Mains: Mains Switch Input/Output The internal configuration of this input/output is shown in Fig. 4­13. Pin 40 represents the output of the mains flip­flop with a resistive pull­up. The output is active low (mains on). In the case of infrared remote control, this pin acts as output and drives an external switching amplifier, the mains relay, In the case of direct operation, this pin is used as input for switching on the TV receiver by means of an active low level applied to this pin, which sets the main flip­flop. More information is given in section 2.3. 11 Pins 22 to 29 ­ Port P3, Bits 0 to 7 The diagram of these open­drain outputs is shown in Fig. 4­8. The voltage handling capability of Port­bits 0 and 1 (pins 28 and 29) is limited to Vsup, but supplies a high output current. The Port­bits 2 to 7 (pins 22 to 27) are outputs with a 12 V rating and a lower output current. In standby, bit 7 of P3 is grounded. screen display outputs. Therefore, there are different colors to represent the output.

4.3. Pin Descriptions for 44­Pin PLCC Pin 1 ­ Vsup This pin must be connected to the positive of the 5 V supply. Pin 2 ­ Ground This pin must be connected to the negative of the supply. Pin 3 ­ Vstb: Standby Supply pin +5 V Via this pin, clock oscillator, reset circuit and remote­ control decoder are powered. By means of this, it is possible to switch on the TV receiver by remote control. The standby consumption is very small. Pins 4 to 7, 8 to 21 ­ Port P2, Bits 0 to 7 The internal configuration of these in/outputs is shown in Fig. 4­3. Direct data transfer with the µC can be executed via this port. The push­pull outputs drive one TTL gate. Pins 8 to 11 ­ Port P1, Bits 4 to 7 The internal configuration of these in/outputs is shown in Fig. 4­4. Direct data transfer with the µC can be executed via this port. The outputs are open­drain with a 12 V rating. Four outputs are available in the 44­pin PLCC package. In the 40­pin DIL package up to two P1­outputs (instead of analog outputs) are available by changing the bonding. Pins 12 and 13 ­ Vertical and Horizontal synchronization Inputs These inputs are shown in Fig. 4­5. They are used to synchronize the on­screen display. Negative pulses are needed. The internal delayed­clock­generator for the OSD section synchronizes to the positive edge of the Hin signal. Pin 14 ­ Fast Blank Output This output, which is shown in Fig. 4­6, is used to stop the normal display, and thus characters can be displayed on the screen. Pins 15 to 17 ­ Video Outputs Red, Green and Blue (RGB) These outputs are shown in Fig. 4­7 and used for on­

TVPO 2066
Pin 41 ­ Reset: Reset Input The internal configuration of this input is shown in Fig. 4­14. The function of this pin is explained in section 2.4. The input circuit is of a Schmitt trigger configuration and provides some noise immunity. In critical applications, however, an additional ceramic capacitor, connected between this pin and GND, may be necessary to increase noise immunity. Pin 42 ­ Osc Out: fosc/4096 Output The internal configuration of this output is shown in Fig. 4­15. This push­pull output provides the memory clock signal for the non­volatile memory MDA 2062 EEPROM (1 kHz). The drive capability of this pin is one TTL gate. This pin is not needed for the non­volatile memory NVM 3060. Pin 43 ­ T1: T1 Input This input can be used as timer input or normal input (e.g. to count the pulses of the horizontal frequency for autosearch function in analog TV sets). For more details about this input, see the CCU 2030, CCU 2050, CCU2070 data sheet. Pin 44 ­ Xtal: Oscillator Crystal The internal configuration of this input/output is shown in Fig. 4­16. For normal use, a 4 MHz crystal is connected to this oscillator pin and to GND. The input is self­ biasing to approximately 3.8 V, input DC resistance is approx. 350 kOhm. The output signal is the 4 MHz clock signal of the TVPO 2066. +5 V D E 0 Fig. 4­5: Inputs (Vin, Hin)

+5 V E E 0

Fig. 4­6: Output (Fast Blank)

+5 V 2...4 k +1 V E E

4.4. Pin Circuits

0.5... 1k +5 V

0

Fig. 4­7: Outputs (RGB)

D D E E 1 0 2 Fig. 4­3: Inputs and Outputs (Port 2) E E 0 Fig. 4­8: Outputs (Port 3)

+5 V E 1 0 2 Fig. 4­4: Inputs and Outputs (Port 1) E E E 0

Fig. 4­9: Output (VS)

12

TVPO 2066
+5 V Stby. D 1 D D E 0 Fig. 4­10: Input (IR) E 0 2 E Fig. 4­14: Input (Reset) E D +5 V Stby

E 0

Fig. 4­11: Outputs (DAC1...4) E D E E

+5 V

+5 V D E 0

0

Fig. 4­15: Output (Mem Osc.)

Fig. 4­12: Outputs (IMC, IMI) +5 V Stby E

1

2 Pin 40: +5 V Stby Pin 38: +5 V D E 0 Fig. 4­13: Inputs/Outputs (Mains, IMD)

E D D

D E

D D D

0

Fig. 4­16: Oscillator (Xtal)

13

TVPO 2066
4.5. Electrical Characteristics All voltages are referred to pin 2. Pins for 44­pin PLCC package. 4.5.1. Absolute Maximum Ratings Symbol TA TS VSUP VStby Parameter Ambient Operating Temperature Storage Temperature Supply Voltage Standby Voltage Output Voltages VP1O VP2O Port P1 Port P2 Open Drain Configuration TTL Configuration Port P3, Analog Tuning IM Bus Mains Oscillator Output Currents IP1O IP2O Port P1 Port P2 Open Drain Configuration TTL Configuration Port P3 Analog Tuning TTL Configuration IM Bus TTL Configuration Mains TTL Configuration Oscillator TTL Configuration Input Voltages, all Inputs except Pins 8 to 11 Port P1 8 to 11 ­0.3 ­0.3 VSUP 13.5 V V 8 to 11 4 to 7, 18 to 21 22 to 27 28, 29 32 to 35 30 ­2 36 to 38 ­2 40 ­2 42 ­2 5 mA 5 mA 5 mA 5 mA ­ ­ ­2 ­ ­ ­ 5 5 5 5 25 5 mA mA mA mA mA mA Bits 0 to 1 Bits 2 to 7 8 to 11 4 to 7, 18 to 21 28 to 29 22 to 27 32 to 35 30 36 to 38 40 42 ­0.3 ­0.3 ­0.3 ­0.3 ­0.3 ­0.3 ­0.3 ­0.3 ­0.3 ­0.3 +13.5 VSUP VSUP VSUP +13.5 +13.5 VSUP VSUP VSUP VSUP V V V V V V V V V V Pin No. ­ ­ 1 3 Min. 0 ­40 ­ ­ Max. 65 +125 6 6 Unit °C °C V V

VP3O VAO VTO VIMO VMO VOO

IP3O IAO ITO IIMO IMO IOO VI VIn VIP1

14

TVPO 2066
4.5.2. Recommended Operating Conditions Symbol VSUP VStby Parameter Supply Voltage Standby Voltage Input Voltages VIRI VMIL VRIL VRIH VnIH VnIL fcr fs Rr Clock Frequency Ser. Resonance Freqency of the Crystal at CL = 20 pF Effective Series Resistance of the Crystal at CL = 20 pF Equivalent Load Configuration (in addition to the crystal, see Fig. 4­17) CL CS RS C31 CL Load Capacitance Series Load Capacitance Series Load Resistance Coupling Capacitor at Pin 31 Load Capacitance at Pins 30 and 42 at Pins 14 to 17 31 30, 42 14 to 17 ­ ­ 300 ­ ­ ­ ­ ­ ­ 10 ­ ­ 3 5 ­ ­ 150 15 pF pF k nF pF pF 44 IR Mains (active) Reset (active) (inactive) All other inputs 2.4 ­ 3.5 3.5 ­ ­ ­ ­ ­ ­ ­ 0.8 4.6 4.6 60 V V MHz MHz 31 40 41 ­ 1.8 ­ ­ 0.8 ­ V V 400 ­ ­ ­ ­ 0.8 mVpp V Pin No. 1 3 Min. 4.75 4.75 Typ. 5.0 5.0 Max. 5.25 5.25 Unit V V

TVPO 44 2066 CR

CL

CS RS

Fig. 4­17: Maximum equivalent load configuration

15

TVPO 2066
4.5.3. Characteristics at VSUP = VStby = 5 V, TA = 25 °C
Symbol Parameter Current Consumption ISUP IStby Output Voltages Port P2, FB TTL Configuration Tuning, Osc. VOH VOL Port P1 Port P3 Bits 2 to 7 Analog VOL VOH Port P3 Bits 0 and 1 RGB VOH VOL IM Bus VOH VOL Mains VOH VOL Output Leakage Currents Port P1 Port P3 Bits 2 to 7 Analog IR IR ­IK CI Port P3 Bits 0 and 1 Short Circuit Output Current IM Bus Input Capacitance Code of the Infrared Transmitter 28, 29 36 to 38 12, 13 8 to 11 22 to 27 32 to 35 ­ ­ ­ ­ ­ ­ ­ 5 20 20 2.8 ­ µA µA mA pF VO = 12 V VO = 5 V VO = 0 40 VStby ­0.4 ­ ­ ­ ­ 1 V V ­IOH = 100 µA IOL = 1.0 mA 36 to 38 2.7 ­ ­ ­ ­ 0.4 V V ­IOH = 200 µA IOL = 200 µA 28 to 29 15 to 17 0.8 ­ 1.0 ­ 1.2 100 V mV ­IOH = 25 µA IOL = 25 µA 8 to 11 22 to 27 32 to 35 ­ ­ ­ ­ 0.4 0.5 V V IOL = 4 mA IOL = 20 mA 4 to 7, 14, 18 to 21 30, 42 2.7 ­ ­ ­ ­ 0.4 V V ­IOH = 100 µA IOL = 1.6 mA 1 3 ­ ­ 90 10 115 20 mA mA Pin No. Min. Typ. Max. Unit Test Conditions

see Data Sheets SAA 1250, IRT 1250, IRT 1260

16

TVPO 2066
5. Appendix 5.1. DAC Poly­Counter Code Table 5­1: DAC Poly­Counter Code Step 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Code [bin] 00111111 00011111 00101111 00110111 00111011 00111101 00011110 00001111 00100111 00110011 00111001 00011100 00101110 00010111 00101011 00110101 00011010 00001101 00000110 00000011 00100001 00010000 00101000 00110100 00111010 00011101 00001110 00000111 00100011 00110001 00011000 00101100 Code [hex] 3F 1F 2F 37 3B 3D 1E 0F 27 33 39 1C 2E 17 2B 35 1A 0D 06 03 21 10 28 24 3A 1D 0E 07 23 31 18 2C Step 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Code [bin] 00110110 00011011 00101101 00010110 00001011 00100101 00010010 00001001 00000100 00100010 00010001 00001000 00100100 00110010 00011001 00001100 00100110 00010011 00101001 00010100 00101010 00010101 00001010 00000101 00000010 00000001 00000000 00100000 01100000 00111000 00111100 00111110 Code [hex] 36 1B 2D 16 0B 25 12 09 04 22 11 08 24 32 19 0C 26 13 29 14 2A 15 0A 15 02 01 00 20 30 38 3C 3E

17

TVPO 2066
5.2. On­Screen Display Format

Start Position

37 dot

1 dot 7 dot

2 dot

18 dot Display Off Character

7 dot

1 dot Fig. 5­1: On­screen display format

18

TVPO 2066
5.3. Character Set LOWER 000 UPPER 00

001

010

011

100

101

110

111

01

10

11

Also available: ­ character set 2: code 0EH = `A' instead of `+' ­ character set 3: code 0EH = `A' instead of `+' code 0FH = `D' instead of ` ­ '

DISPLAY VARIATION 00000 10000 11111

DISPLAY VARIATION 00000 10000 11111

CRO = 1 CRF = 1

CRO = 1 CRF = 0

CRO = 0 CRF = 1

CRO = 0 CRF = 0

19

TVPO 2066
5.4. Programmed Versions of TVPO 2066 Some programmed versions of the TVPO 2066 are available (all versions use the non­volatile­memory NVM 3060): ­ TVPO 2066­A25 for analog TV­sets. With auto­searching of stations, 4 multi­standards, up to 99 stations, sleep­timer, Teletext with TPU 2735 with FLOF & exended characters (Spanish, Polish, Hungarian and Turkish). ­ TVPO 2066­D03 for digital TV­sets. Along with the VSP 2860 and the VCU 2133 it offers a very economical solution of digital TV­sets (simple TV). Some features are 4 standards: PAL, NTSC, SECAM East/West, up to 99 stations, 3 video modes, auto­searching analog output for analog audio (volume) control and more. Separate data sheets are available for analog and digital versions. Application diagrams will be found there. The last page shows an application diagram for analog TV­ sets. 5.5. User Options If the manufacturer writes his own software for the TVPO 2066, he can choose some options by program mask or diffusion mask. For explanation of the RESET option see section 2.3.

Table 5­2: Options Option Reset Port 2 configuration address and commands for power on in the remote­control decoder Character set Default Setting Reset 1 TTL address 16, commands 3, 17...26, 35, 36 Set 1 Alternative Setting none or Reset 2 open­drain up to 5 groups in a binary decoder matrix Set 2, Set 3 or customer specific setting

20

TVPO 2066
5.6. Application Circuit (pin numbers for 40­pin DIL package)

21

TVPO 2066

22

TVPO 2066

23

TVPO 2066

ITT Semiconductors Group World Headquarters INTERMETALL Hans-Bunte-Strasse 19 D-7800 Freiburg Tel. (0761) 517-0, Telex 772 715 Telefax (0761) 517-174 Printed in Germany by A. Simon & Sohn, Freiburg (9/92) Order No. 6251-327-3E

Reprinting is generally permitted, indicating the source. However, our consent must be obtained in all cases. Information furnished by ITT is believed to be accurate and reliable. However, no responsibility is assumed by ITT for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of ITT. The information and suggestions are given without obligation and cannot give rise to any liability; they do not indicate the availability of the components mentioned. Delivery of development samples does not imply any obligation of ITT to supply larger amounts of such units to a fixed term. To this effect, only written confirmation of orders will be binding.

24

Arrangement for On­Screen Display

R G B FB Vin Hin
35 36 6 7 8 1 40 39 38 37 9 15 H V F B G R B P22 P23 P25 P26 P27 2

+5 V Standby MAINS Switch 1N4148

10k 18k ZPD5V6 10k BC548

1k

BC548 2.2 k

1u 17 10 11 15 14 18 19 20

100

47 n

+12 V

RESET IMD IMI

4 7 6 5 +12 V 4 x 3.3 k

8

2 3

+5 V

4 8 Keyboard 12 16

3 7 11

2 6 10

1 5 9 13

25 26 27 28

P30 P31 P32 P33

NVM 3060 EEPROM 1 GND of Power Supply

IMD

15 14

21

4 x 47 k Analog 1 (Brightness) Analog 2 (Color) 4 x 0.1u Analog 3 (Contrast) Analog 4 (Volume) +12 V

TVPO 2066­A25

22 3 4

12 4 MHz

Xtal 5 x 22 k P34 29 P35 30

Band I Band III Band IV/V 3 x BC 308 3 x 1N4148 47 k

+5 V Standby

Infra­Red Remote Control Key board IRT 1250

+ BPW 22u 41

100 I R 23 TBA 2800 10 n 10 k 1M 50...200p 1.2 n 10 n P P P P P 24 2 2 3 3 T 2 VS 1 0 7 6 1 4 470p 34 33 32 31 13 5 10 k BF240 10 k 10 k 47 u 47 k 18 k 0.47u 39 k 0.22u

+

2.2 u

47 k

>40 V Tuning Voltage 47 k 0.1u GND Tuner AFC Switch Hor. Sync. VCR AV AV MS0 MS0 MS1 MS1

47 k

ZTK 33

AV MS COM

MS1 MS0 COM

see description