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ST7282A5 - ST7282B5
ROM FROM EPROM
PRELIMINARY DATASHEET
s s
ST72-Core Controller/Driver for max. 20 × 16, 28 × 8 or 32 × 4 LCD segments (ST7LCD4) 56 bytes LCD-RAM 864 bytes data RAM 512 bytes EEPROM (eep2a) 32Kbytes program ROM 24 digital I/O (ST7 IO3) with pull up, interrupt input, analog input, push-pull/ open drain output 36 LCD/IO combi pins (ST7 LCIO1) with pull-up, interrupt input, push-pull, open drain output, LCD output 16 bit reload timer (ST7TIM4) Watchdog Timer (ST7 WD2) 8 bit synchronous serial I/O (ST7SIO)
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s s s s s s
s
s s s s s
Group & Block Sync Module for RDS (ST7 RDS GB) RDS filter (ST7 RDS FI) LCD Synchro IN / Out System Frequency 8.55 MHz
8 bit A/D Converter (ST7ADC2)
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RDS Demodulator (ST7 RDS BD)
s
n n
Family ST7
Issuer Ref. PG-RO
Chrono 97115 7282A5B5
March 26, 1997
Previous Ref Page 1/23
Edition Target C
ST7282A5 - ST7282B5 - ROM FROM EPROM
1 GENERAL DESCRIPTION
Figure 1. Block Diagram
S 1 6 /P D 7 S 1 5 /P D 6 S 1 4 /P D 5 S 1 3 /P D 4 S 1 2 /P D 3 S 1 1 /P D 2 S 1 0 /P D 1 S 9 /P D 0 S 8 /P F 7 S 7 /P F 6 S 6 /P F 5 S 5 /P F 4 S 4 /P F 3 S 3 /P F 2 S 2 /P F 1 S 1 /P F 0 B P 1 6 /S 0 /P G 7 B P 1 5 /S - 1/P G 6 B P 1 4 /S - 2/P G 5 B P 1 3 /S - 3/P G 4 B P 1 2 /S - 4/P G 3 B P 1 1 /S - 5/P G 2 B P 1 0 /S - 6/P G 1 B P 9 /S -7 /P G 0
Seg. Drv. PORT D
ST7 LCIO
VDDP VSSP VDDA VSSA PC0/AIN PC1/AIN PC2/AIN PC3/AIN PC4/AIN PC5/AIN PC6/AIN PC7/AIN PB0/AIN PB1/AIN PB2/AIN PB3/AIN PB4/AIN PB5/AIN PB6/AIN PB7/AIN PO R T C S T 7 IO 3 PO RT B S T 7 IO 3 P A 0 /C P 1/A IN P A 1 /C P 2/A IN P A 2 /A IN P A 3 /A IN P A 4 /A IN P A 5 /A IN P A 6 /A IN P A 7 /A IN R D S C O M P /P E 4 /S 2 1 VD D VS S V P P /T E S T R E SE T MPX R D S F IL RDS REF O S C IN O S C O U T /S T O P S 2 2 /P E 5 S 2 1 /P E 4 /R D S C O M P O s c - O p tio n PORT A AD C ST 7 A DC 2 ST7 LCIO S IO RDS DEM OD. ST 7 R DS B D G R P & B LK S Y N C ST 7 R D S G B R D S F ilte r ST7 LCIO ST 72 CO R E ST 7 R DS F I O S C IL L A T O R S T 7 O S C IL L A T O R
LCD C O N TR OL S T7 LC D 4 S eg . D rv ./P or t E
E E P R O M 51 2
W A TC H D O G ST 7 W D 2 Seg. Drv. PORT F
T IM E R 1 6 b it S T 7 T IM 4
RA M 864
3 2K R O M
Seg. Drv. PORT G
LCD RAM 5 6B y te
PO R T H S T 7 L C IO
ST7 IO3
8 .5 5 M H z
S T 7 L C IO
BP8/S-9/PH7
BP7/S-10/PH6
BP6/S-11/PH5
BP5/S-12/PH4
BP4/PH3
BP3/PH2
BP2/PH1
BP1/PH0
VLCD
VLCD 4/5
VLCD 3/5
VLCD 2/5
VLCD 1/5
S17/PE0
S18/PE1
S19/PE2
n n n
Family ST7
Issuer Ref. PG-RO
Chrono 97115 7282A5B5
March 26, 1997
S20/PE3
Previous Ref Page 2/23
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ST7282A5 - ST7282B5 - ROM FROM EPROM
1.1 Quick Reference
The ST7282A5/B5 is a 32K ROM version of the ST72 family, using the ST72CORE and N-Well technology. It is derived from EPROM M4 version replacing EPROM by ROM. Two different commercial products are supported by this device : ST7282A5 (no LCD driver) functionnality described in specification SD70KL1618 ed. F) and ST7282B5 (LCD driver) functionnality described in specification 96096 ed. B). It contains an LCD controller/driver with 20 segment and 16 backplane outputs able to drive up to 20 x 16 = 320 segments. The LCD control logic reads automatically data from the LCD-RAM independently from the ST7282 B5. Further it contains up to 62 I/O pins, 24 of them can be used as analog inputs to the 8 bit analogdigital converter. Each digital I/O pin can individually be defined by software to work in one of the following modes: open-drain output, push pull output, input, input with pull-up (23 pins only) or inter1.2 Parameters The values below substitute the corresponding values in the specifications of dedicated functions. 1.2.1 Absolute maximum ratings
Supply voltage Input voltage* Output voltage* Input current Output current* Power dissipation Storage temperature Operation temperature Display voltage Output voltage Seg+COM ESD LU susceptibility ( VDD - VSS ) VIN VOUT Iin IOUT PD Tstg Tamb (VLCD - VSS) VOUT ESD LU -0.3 ... +7V VSS-0.3V...VDD +0.3V VSS-0.3V ... VDD+0.3V -10 ... +10mA -10 ... + 10mA tbd -55 ... +125°C -40 ... +85°C VDD ... 7V VSS-0.3V ... VLCD+0.3V 2500V VDDA, Pin 52 - Class C
rupt input with pull up (23 pins only). 3 of the digital I/O pins serve as interface to the SIO. On pin PA4 the pull-up resistor is desactivated. Port pins PD, PE, PF, PG and PH are multiplexed with LCD Segment and backplane pins. A 512 byte EEPROM for non volatile storage of data is available. The programming voltage for that device is generated on chip without external components. So no extra supply is necessary. 16 bytes are protected against external readout. One interrupt vector is connected to the I/O ports. Five more interrupt vectors are available for the timer, the ADC, the serial I/O interface and the Group & Block Sync module (2). The watchdog can be set by the user in 64 increments from 2.8msec to 182msec ( fOSC = 8.55 MHz ). A synchronous 8 bit serial interface for serial data IN/OUT is also implemented. RDS signals can be decoded with the help of RDS filter, RDS demodulator and Group & Block Sync module.
1.2.2 Recommended operating conditions
Supply voltage Supply votage difference (VDD - VSS) (VDD, VDDP, VDDA) (VSS, VSSP, VSSA) 4.5 ... 5.5V 50mV
The maximum accumulated current of all I/O pins should not exceed 40 mA for VDDP and 40 mA for VSSP.
Family ST7 Issuer Ref. PG-RO Chrono 97115 7282A5B5
* except LCD pins ** MIL 883B Mode, 100pF through 1.5k
March 26, 1997
Previous Ref Page 3/23
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ST7282A5 - ST7282B5 - ROM FROM EPROM
1.2.3 Electrical Characteristics The values given in the specifications of dedicated functions are generally not applicable for chips. Therefore, only the limits listed below are valid for the product. T = -40 ... +85°C, VDD - VSS = 5V unless otherwise specified.
PARAMETER Supply voltage Supply current Run Mode Supply current Wait Mode Supply current slow wait mode Supply current halt mode Supply current Reset Mode Display voltage Supply voltage differences (VDD, VDDP, VDDA) (VSS, VSSP, VSSA) OSCILLATOR: Input/output cap Cin, Cout Oscillation frequency Built up time 2) RESET: Input current Input current 4) Input current 5) Input voltage high Input voltage low POWER-ON RESET Supply rise time Supply recovery time Trigger level on Trigger level off RDS FILTER: Center frequency 3dB Bandwith Gain Attenuation fc BW G A Vin = 3mVRMS 57 KHz, Vin = 3mVRMS f = ±4 KHz f = 38 KHz f = 67 KHz Input impedance Load impedance MPX input signal Family ST7 Issuer Ref. PG-RO RI RL VIN Chrono 97115 7282A5B5 March 26, 1997 56.5 2.5 18 18 50 35 100 1 170 57 3 20 22 80 50 160 250 57.5 3.5 22 200 600 Edition Target C Page 4/23 KHz KHz dB dB dB dB K M mVRMS
6) 3) 1)
SYMBOL
CONDITION
MIN 4.5
TYP 10 3 0.7 10 -
MAX 5.5 20 5 2 100 15 7 50
UNIT V mA mA mA µA mA V mV
VDD IDD IDD IDD
IDD
fOSC=8.55MHz
no output load
VDD -
fOSC=8.55MHz
WD, Timer, LCD active no output load no output load VRESET=VSS f=8.55MHz
IDD VLCD VD
9.00 fOSC tBU
pF MHz ms
VDD = 4.5V
VDD=5.0V
8.55 -
8.55 8
8.55 20
C1=C2=22pF
Crystal -IR IR IR VR VR tr trec Vtlon Vtloff 10%-90% VR=VSS VR=VDD VR=VDD 0.7VDD +50 +10 .+100 +20 1 0.2VDD 10 3 µA µA mA V V ms ms V V
.01 10 1.4 -
Previous Ref
ST7282A5 - ST7282B5 - ROM FROM EPROM
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNIT
I/O PORTS: Input leakage current 7) Input leakage current Input voltage high Input voltage low Output voltage high (PA,PB,PC) Output voltage high (PD, PE, PF, PG, PH) Output voltage low (PA, PB, PC, PD, PE, PF, PG, PH) Output voltage slope Output current slope Noise amplitude Pullup Resistor Current IIL IIH VIH VIL VOH VOH VOH VOH VOL VOL dVO/dt dIO/dt VN V=VSS V=VDD leading edge trailing edge I=5mA, VDD=4.5V I=1.0mA, VDD=4.5V I=2.5mA, VDD=4.5V I=0.5mA, VDD=4.5V I=-5mA, VDD=4.5V I=-1.6mA, VDD=4.5V CL=50pF CL=50pF 20MHz-250MHz 0.7VDD 3.0 4.1 3.0 4.1 0.25 2.5 100 50 10 10 0.2VDD 1.0 0.4 µA µA V V V V V V V V V/ns mA/ns µV µA
VIN=VSS IRPU
fOSC=8.55MHz 8) fOSC=8.55MHz
ADC: Resolution Total Error Conversion time Input capacitance Analog source impedance Osc. frequency range LCD DRIVER: Frame frequency DC offset voltage 9) COM output voltage high COM output voltage low SEG output voltage high SEG output voltage low EEPROM: Write time tW VDD=4.5V 10 ms fF VOS VOH VOL VOH VOL fOSC=8.55MHz VLCD=VDD, no load I=50µA I=50µA I=25µA I=25µA 132 50 0.5 0.5 Hz mV V V V V RVA tcon VA1 34 8.55 +2 35 5 30 bit LSB µs pF K MHz fOSC=8.55MHz 8)
1)Operation below 30 KHz Mis possible but requires increased supply current 2)Time to build up the oscillation amplitude to 90% VDD 3)Pull-up resistor 4)WD not active 5)WD generating a reset 6)Period for which VDD has to be disconnected or at OV to allow internal reset function at next power up 7)pull up off
Family ST7 Issuer Ref. PG-RO Chrono 97115 7282A5B5 March 26, 1997 Previous Ref Page 5/23 Edition Target C
ST7282A5 - ST7282B5 - ROM FROM EPROM
8) noise at VDD, VSS < 10 mV 9)The DC offset voltage refers to all segment and common outputs. It is the difference between the measured voltage value and nominal voltage value for every voltage level. Rin of voltage meter must be > 10 M.
Family ST7
Issuer Ref. PG-RO
Chrono 97115 7282A5B5
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Edition Target C
ST7282A5 - ST7282B5 - ROM FROM EPROM
1.3 ST7282A5/B5 ADDRESS MAPPING
ADDR. $0000 $0001 $0002 $0003 USER Port A Data Reg. Port A Data Direction Reg. Port A Option Reg. Port A Pin status
$0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F
Port B Data Reg. Port B Data Direction Reg. Port B Option Reg. Port B Pin status Port C Data Reg. Port C Data Direction Reg. Port C Option Reg. Port C Pin status Port D Data Reg. Port D Data Direction Reg. Port D Option Reg. Port D Pin status
$0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D) --------) $0023)
ADC Control Reg. ADC Data Reg. Watchdog Reg. LCD Ctrl. 1 EECR1 EECR2 SIO Data Reg. SIO Interrupt Disable Timer Reg. 1 Timer Reg. 2 Timer Reg. 3 Timer Reg. 4 Timer Reg. 5 (Not to be used ** (----(from $001D to $0023
Family ST7
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ST7282A5 - ST7282B5 - ROM FROM EPROM
$0024 $0025 $0026 $0027 $0028 $0029 $002A $002B $002C $002D $002E $002F
CRC Test Reg. ( ST use ) CRC Test Reg. ( ST use ) Misc. Reg. LCD Ctrl. 2 reserved reserved Filter Reg. 1 Filter Reg. 2 RDS_R0 RDS_R1 RDS_R2 reserved
$0030 $0031 $0032 $0033 $0034 $0035 $0036 $0037
RDS_BD_H RDS_BD_L RDS_CORRP RDS_QU RDS_INT reserved reserved reserved
$0038 $0039 $003A $003B $003C $003D $003E $003F
reserved reserved reserved reserved reserved reserved reserved reserved
$0040 ----$0047 $0048 ----$005F
LCD RAM 8 Byte MUX8 SEG.-7-0 = Byte 40 ... 47 BP1 ... BP8 = Bit0 ... Bit7 LCD RAM 24 Byte MUX8,11,16 SEG. 1 - 24 = Byte 48 ... 5F BP1 ... BP8 = Bit0 ... Bit7
Family ST7
Issuer Ref. PG-RO
Chrono 97115 7282A5B5
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ST7282A5 - ST7282B5 - ROM FROM EPROM
$0060 ----$0063 $0064 $0065 $0066 $0067 $0068 ----$007F $0080 ----$008F
LCD RAM 4 Byte Mux 4 Seg -8, -9, -10, -11 BP1 ... BP4 = Bit0 ... Bit3
LCD RAM not used for display
LCD RAM 24 Byte MUX 11, 16 SEG. 1-24 = Byte 68 ... 7F BP9 ... BP16 = Bit0 ... Bit7
reserved
$0090 $0091 $0092 $0093
Port E Data Register Port E Data Direction Register Port E Option Register Port E Pin Status
$0094 $0095 $0096 $0097 $0098 $0099 $009A $009B $009C $009D $009E $009F $00A0 ----$03FF
Port F Data Register Port F Data Direction Register Port F Option Register Port F Pin Status Port G Data Register Port G Data Direction Register Port G Option Register Port G Pin Status Port H Data Register Port H Data Direction Register Port H Option Register Port H Pin Status
RAM 864 Stack = 300-3FF
Family ST7
Issuer Ref. PG-RO
Chrono 97115 7282A5B5
March 26, 1997
Previous Ref Page 9/23
Edition Target C
ST7282A5 - ST7282B5 - ROM FROM EPROM
$0400 ----$0DFF $0E00 ----$0E0F $0E10 ----$0FFF $1000 ----$1FFF $2000 ----$7FFF $8000 ----$FFDF $FFE0 ----$FFEF $FFF0 ----$FFFF user vectors reserved (ST Routram area) ROM 32k reserved not available (test area) EEPROM 512 EEPROM read out protected reserved
"Not to be used" is mandatory. Any access would modify the functionality.
Family ST7
Issuer Ref. PG-RO
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ST7282A5 - ST7282B5 - ROM FROM EPROM
2 IMPLEMENTATION REMARKS OF THE DEDICATIONS
In this chapter the options of the dedications, which are implemented are described. The dedications are described in detail in the target specs of the dedications. In case of discrepancies between this specification and the specs. of the dedications, this specification is valid. 2.1 Core 2.1.1 Oscillator The oscillator can be used with quartz or ceramic resonator. The pins OSCIN and OSCOUT permit connection to the on chip clock oscillator circuit. OSCIN is the input, OSCOUT the clock oscillator output. A quartz or a ceramic resonator can be connected to these pins. Two external ceramic capacitors of 22pF connect the oscillator pins to ground. Also an external system clock can be applied to the oscillator input OSCIN. 2.1.2 External reset input RESET Low level active external reset input with Schmitt-Trigger characteristic. A pull-up resistor of typically 300k ( 200k - 500k ) is integrated. This pin is resetting the I/O ports immediately without any need of a clock. 2.1.3 Stack The Stack is located at 3FFH and may go down to 300H. 2.1.4 Interrupts I1 is connected to IOPorts A ... H (start address FFFAH ) I2 is connected to RDS GRP & BLK SYNC (block interrupt) ( start address FFF8H ) I3 is connected to SIO ( start address FFF6H ) I4 is connected to Timer ( start address FFF4H ) I5 is connected to ADC (start address FFF2H ) I6 is connected to RDS GRP & BLK SYNC (bit interrupt) (start address FFF0H ) If more then 1 input pin of a group, connected to the same interrupt, is selected as interrupt input with pullup, all selected inputs are "AND" connected. WARNING : Read modify write instructions may clear interrupt flags of dedications unintentionally if the interrupt flag is set after the read and before the write. Operations on control registers of dedications should be done with sufficient timing distance to interrupt events. 2.1.5 Miscellaneous register( 0026h ) Read/Write Reset Value: 0000 0000 ( 00h ) This register is a various 8-Bit register where only 3 bits are used for interrupt and slow mode. b6 = INTP: Interrupt Positive allows to select the I1 line triggering mode in conjunction with INTN. It can only be modified when the I bit of the CCR is set. b5 = INTN: Interrupt Negative allows to select the I1 line triggering mode in conjunction with INTP. It can only be modified when the I bit of the CCR is set. b1 = SM: Slow Mode. Setting this bit to "1" enables Slow Mode, thus reducing power consumption. In this mode, an extra divider by 64 is added in the clock circuitry. In Halt Mode SM bit is automatically reset.Registers of all RDS-Modules should not be accessed during slow mode.
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ST7282A5 - ST7282B5 - ROM FROM EPROM
Figure 2. External Interrupt Options
INTP 0 0 1 1 INTN 0 1 0 1 I1 External Interrupt Options Negative edge and Low level sensitive Negative edge only Positive edge only Positive and negative edge sensitive
2.2 LCD controller/driver The LCD module contains an LCD controller/driver with 20 segment and 16 backplane outputs able to drive up to 20 x 16 = 320 segments. The LCD control logic reads automatically data from the LCD-RAM independently from the ST72 core. Two signals (LCF32K,LCSYNCHINOUT) can be activated on pins PC0, PC1 to connect a slave display chip for expanding the number of segments. To activate these pins as LCF32K, LCSYNCHINOUT, bit0 of register LCD Ctrl.2 (0027H) has to be set. During reset this bit is cleared. VLCD must never be below VDD. 2.2.1 Address mapping of the picture elements The LCD-RAM is located in the address region of the ST72 data space from address 40H - 7FH. The LCD forms a matrix of 20 segment lines ( columns ) and 16 backplane lines ( rows ). Each bit of the LCD-RAM is mapped to one dot of the LCD matrix according to fig. 1. If a bit is set, the corresponding LCD segment is switched on, if it is reset, the segment is switched off. After reset, the LCD-RAM is not initialized and contains arbitrary information. As the LCD control register is cleared, the LCD is completely switched off. In halt mode no clock for the LCD module is available from the main oscillator. The LCD module is switched off in halt mode. The input frequency of the LCD controller is fOSC/2 (4.275MHz). A 32kHz stand by oscillator is not available. Therefore the mode FEXT (C5, C4, C3 = 001) of LCD control register cannot be used. In any case a missing LCD clock ( no oscillator active, broken crystal etc. ) is detected by a clock supervisor circuit which switches all segment and common lines to ground to avoid destructive DC levels at the LCD. If the LCD clock is not missing but far too slow (e.g. due to incorrect setting of C5, C4, C3 in LCD control register) the LCD is switched off periodically. This situation has to be avoided. A division factor of +256 is recommended for the prescaler (C5, C4, C3 = 110; fOUT = 16.699KHz). With this setting of the predevider, frame frequencies of 132.2Hz, 66.1Hz, 44.1Hz and 33.1Hz can be generated. The frequency out of the prescaler must not be below 15KHz in order not to switch off the display through the LCD oscillator supervisor. To activate segments and backplanes, data and option register bits of the corresponding combiport pins have to be set to 1. During reset data and option register bits of combiports are set to 1.
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Chrono 97115 7282A5B5
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ST7282A5 - ST7282B5 - ROM FROM EPROM
2.2.2 External Divider Chain The different display voltage levels are supplied by an external resistor chain as shown in fig. below. Two different configurations with five or four display voltage levels can be chosen. The resistors have to have a good matching within < 1% to avoid DC voltage levels on the liquid crystal device. DC levels trigger electrode reactions on the liquid crystal cell, deteriorating display quality rapidly.
Figure 3. External Divider Chain
VLCD VLCD
R5 C4 VLCD45 C3
R4
VLCD45 R4 C3 VLCD35 C2 R3 C2 VLCD25 R2 R2 C1 VLCD15 C1 VLCD15 VLCD25 R3 VLCD35
R1
R1 GND
GND
ST6LCD3 4.DS4
C1 = C2 = C3 = C4 = 0.1 ... 0.3µF R1 = R2 = R3 = R4 = R5 = 1 ... 200k
Family ST7
Issuer Ref. PG-RO
Chrono 97115 7282A5B5
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ST7282A5 - ST7282B5 - ROM FROM EPROM
2.2.2.1 Working with 1/5 Bias Figure 4. Waveform on common and on segment output working with 1/5 Bias
VLCD 4/5 3/5 2/5 1/5 GND 0 1 0 1 VLCD 4/5 3/5 2/5 1/5 GND 0 1 0 1
BACKP LANE OFF
ST6LC352.DS 4
BACKP LANE SELECTED
VLCD 4/5 3/5 2/5 1/5 GND 0 1 0 1
SEGMENT S ELECTED
VLCD 4/5 3/5 2/5 1/5 GND 0 1 0 1
SEGMENT OFF
ST6LC351.DS 4
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ST7282A5 - ST7282B5 - ROM FROM EPROM
2.2.2.2 Working with 1/4 Bias Depending on the selected display material, the operating mode and the display voltage VLCD, it is possible to reduce the LCD resistor chain to 4 resistors, and operate with the 1/4 bias method.
If VLCD35 and VLCD25 are connected to the same voltage, the segment and backplane drivers will work in the same way as with 1/5 bias, but the resulting waveforms will look a bit different :
Figure 5. Waveform on common and on segment output working with Bias 1/4
VLCD 4/5 3/5 2/5 1/5 GND 0 1 0 1
SEGMENT SELECTED
VLCD 4/5 3/5 2/5 1/5 GND 0 1 0 1
SEGMENT OFF
ST6LC351.DS 4
VLCD 3/4 2/4 1/4 GND 0 1 0 1
VLCD 3/4 2/4 1/4 GND 0 1 0 1
SEGMENT SELECTED
SEGMENT OFF
ST6LC362.DS 4
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ST7282A5 - ST7282B5 - ROM FROM EPROM
Figure 6. Address Mapping of the LCD-RAM MUX16
BP1 BP2 BP3 BP4 BP5 BP6 BP7 BP8 BP1 BP2 BP3 BP4 BP5 BP6 BP7 BP8
bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 S E G 1 S E G 2 S E G 8 S E G 8 S E G 20 S E G 24 (SEG21 ... SEG24 are not available) 68 69 -6F 70 -7B --7E 7F 48 49 -4F 50 ----5E 5F ADRESSES 40 ... 47 and 60 ... 67 not used
Figure 7. Address Mapping of the LCD-RAM MUX8
BP1 BP2 BP3 BP4 BP5 BP6 BP7 BP8 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 S E G -7 S E G -6 S E G 0 S E G 1 S E G 2 S E G 24 (SEG21 ... SEG24 are not available) 40 41 -47 48 49 ----5E 5F ADRESSES 60 ... 7F not used
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ST7282A5 - ST7282B5 - ROM FROM EPROM
Figure 8. Address Mapping of the LCD-RAM MUX4
BP1 BP2 BP3 BP4
bit0 bit1 bit2 bit3 60 61 62 63 40 41 -47 48 49 ---5E 5 F S E G 24
ADRESS ES 64 ... 7F not used
S E G -11
S E G -10
S E G -9
S E G -8
S E G -7
S E G -6
S E G 0
S E G 1
S E G 2
(SEG21 ... SEG24 are not available)
2.3 TIMER 4 16 bit autoreload timer with 2 capture inputs connected to PA0, PA1 (see spec. ST7TIM4). The in2.4 WATCHDOG The WD2 is used to reset the ST7282 B5 after a certain period of time in the range of 2.8 msec up to 184 msec when fOSC = 8.55 MHz is used. WD2 will be activated, if bit0 in Watchdog Reg. (Adr. 12h) is set ("1"). Once WD2 is running, any software access to bit0 in Watchdog Reg. will NOT influence WD2. However, a RESET signal (either externally or caused by WD2) will reset bit0 of Watchdog Reg. 2.5 I/O PORTS Pins PD0 ... PD7, PE0 ... PE3, PF0 ... PF7, PG0 ... PG7 and PH0 ... PH7 are of type LCIO. Pins PA0 ... PA7, PB0 ... PB7 and PC0 ... PC7 are of type IO3 and can also be used as analog inputs. The interrupt outputs of PORT A, PORT B, PORT C, PORT D, PORT E, PORT F, PORT G and PORT H are anded and connected to the interrupt input I1 of core ( start address FFFAH ). So every port pin which is programmed as an input with interrupt enabled can generate an interrupt. If more than one port pin is programmed as an interrupt input, overlapping interrupts cannot be detected due to the AND function. PA0, PA1 are also used as CP1, CP2 inputs of TIMER 4. The pins PA5 ... PA7 are also used by the serial I/O ( see fig. 2 ). PA5 is connected with SCL ( clock input ), PA6 is connected with SDA ( data input ) and PA7 is connected with DOUT ( data output ) of the SIO. For serial input operation PA5 and PA6 have to be programmed as inputs. For serial output PA7 has to be programmed as open drain output ( DDR = 1, OPR = 0 ). In this operation mode the output of the SIO shift register instead of the port data register is connected to the port buffer. When PA7 is programmed as push pull output ( DDR = 1, OPR = 1 ), the port data register is connected to the port buffer. When the SIO pins are not used PA5 ... PA7 can be used as any other I/O pin (PA7 not in open drain output mode). After reset ports PA0 ... PA7, PB0 ... PB7 and PC0 ... PC6 are in input mode with pull up resistors switched on and interrupt disabled. After a RESET, WD2 is deactivated and set to it's longest period ( 184 msec for fOSC = 8.55 MHz ). WD2 is able to produce a SW-Reset ( bit0 set to "1", bit1 to "0" ). Dedication address of WD2 is 12h . If WD2 is enabled, any stop instruction will generate a reset. However, the use of a stop instruction (HALT) is not recommended in this case. put clock of the timer is fosc divided by 2.
Family ST7
Issuer Ref. PG-RO
Chrono 97115 7282A5B5
March 26, 1997
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Edition Target C
ST7282A5 - ST7282B5 - ROM FROM EPROM
PA4 does not have a pull-up resistor. Ports PD0 ... PD7, PE0 ... PE3, PF0 ... PF7, PG0 ... PG7 and PH0 ... PH7 are in the "LCD Output mode" (all pins switched to VSS). 2.6 ADC The reference voltage inputs of the ADC1N are connected to VDDA, VSSA. Therefore special care has to be taken to stabilize VDDA, VSSA and to avoid switching of I/O pins during conversion. Analog inputs may be multiplexed from pins PA0 ... PA7, PB0 ... PB7 and PC0 ... PC7. Up to 24 analog inputs can be multiplexed. Selection of an analog input is done by programming the corresponding pin of a port as analog input ( DDR = 0, DR = 1, OPR = 1 ). Be sure that only one port pin is programmed as analog input at a time. Otherwise the analog sources are shorted by the analog multiplexer. Conversion time for an 8.55 MHz clock is 34 µsec (i.e. 288 clocks + 0...6 clocks of fOSC) because the ADC is supplied with a clock signal of fOSC : 6 that is also available dur2.7 SERIAL I/O The 8 bit SIO generates an interrupt after the falling edge of the eight external clock pulse. The interrupt signals to the ST72 to read or write the SIO via an 8 bit register ( adr. 26H ). The SIO uses the input/output structure of Port A ( PA5 : SCL, PA6 : SDA, PA7 : DOUT ) (see fig. 2). The 3 pins can be operated in the following ways: directly by software, as an S-BUS, as an I2C-BUS and as a standard SIO ( clock, data, enable ).
PC7 is switched to analog input mode during reset ( data register and option register bits are set ). PC0, PC1 may optionally be used to "cascade" the LCD (refer to: 2. LCD CONTROLLER/DRIVER).
ing WAIT. The ADC interrupt is connected to level sensitive interrupt input I5 of the core ( start address FFF2H ). So the interrupt has to be cleared before the interrupt service routine is left. A stop instruction will stop the clock of the ADC and will switch off its comparator to achieve minimum power consumption. This can also be done by clearing bit 5 ( SC ) of ADC control register ( 10H ). A rising edge on EOC-bit sets the interrupt flipflop. To remove the interrupt, a write operation to ADCControl register has to be executed, to clear the interrupt flipflop. After the reset, the interrupt flipflop is also cleared.
To operate the SIO PA5 and PA6 have to be programmed as inputs, PA7 as open drain output. The SIO interrupt ( active low ) is connected to the interrupt input I3 of the core ( address FFF6H ). After reset all ports are in input mode with pull up resistors switched on and the SIO interrupt is disabled.
Family ST7
Issuer Ref. PG-RO
Chrono 97115 7282A5B5
March 26, 1997
Previous Ref Page 18/23
Edition Target C
ST7282A5 - ST7282B5 - ROM FROM EPROM
Figure 9. Peripheral Interface Configuration of Serial I/O
PP / OD 0 1
OPR DR OUT
DOUT / PA7
MUX
IN SDA / PA6 DR
SERIAL I/O
CLOCK SCL / PA5 DR
INTERFA C.DS 4
2.8 RAM The RAM is located in the address range A0H3FFH. 2.9 EEPROM The 512 bytes EEPROM is located at addresses 0E00 - 0FFF. 2 cells of 256 bytes each or one cell of 512 bytes may be used. EEPROM control register EECR (adr. 014H) is used to control the different operation modes of the range 0E00H - 0EFFH, EEPROM control register EECR2 (adr. 015H) that of range 0F00H - 0FFFH. Some of its bits are read only, some are write only. So no single bit instructions are allowed. To avoid destruction of data during power up or down, the reset pin directly desactivates the chargepump of EEPROM cells. The EEPROM can be used for data storage only, no program execution and no read modify write instructions (single bit, increment, decrement) are possible. After bit E2LAT of EECR goes to low, there should not be a read operation during the next 20 µsec. A parallel programming mode for 8 bytes is available. No clear is needed before a write. Two cells of 256 bytes are used, parallel programming of bytes in each cell is possible. This should be avoided however, to keep software compatitility between all future versions and ROM versions, that have only one physical register, that will be addressed through two different addresses 14H and 15H. 300H-3FFH may be used as Stack area.
Family ST7
Issuer Ref. PG-RO
Chrono 97115 7282A5B5
March 26, 1997
Previous Ref Page 19/23
Edition Target C
ST7282A5 - ST7282B5 - ROM FROM EPROM
Before access to one area, also the control register of the other area should be checked and access done only, if both areas allow the required access.
EEAREA 0E00 Adr. 14H Reg 0EFF future 0F00 Adr. 15H Reg 0FFF
SGS-THOMSON may implement a single or double register version in future ROM or EPROM versions.
Adr. 14H Reg Adr. 15H
EEAREA 0E00
0FFF
PADD.DS 4
2.10 32K ROM The 32K ROM is located at addresses 8000H-FFFFH. 16 bytes ( FFE0H - FFEFH ) are reserved for SGS-Thomson test vectors. 2.11 RDS Modules ( see separate specs ) Registers of all RDS-Modules should not be accessed ( read or write ) during slow mode of CPU. 2.12 OSCILLATOR The ST7 Oscillator allows operation with a crystal or external input. The corresponding mode is defined by a metal option. In case of external input the clock amplitude into OSCI may not be lower then 50mV. The pin OSCO/STOP then is serving as output for the stop signal to synchronize with external clock sources. In the present version, the device works with a dedicated crystal.
Family ST7
Issuer Ref. PG-RO
Chrono 97115 7282A5B5
March 26, 1997
Previous Ref Page 20/23
Edition Target C
ST7282A5 - ST7282B5 - ROM FROM EPROM
3 TESTING
Pin VPP/TEST is used for testing the device. For normal operation pin VPP/TEST has to be connected to VSS or has to be left open. An internal pull down resistor of about 100k is integrated to select normal operation mode if pin VPP/TEST is not connected. The testmodes are for SGS THOMSON internal use only!
4 PIN DESCRIPTION
4.1 Connection diagram Figure 10. Connection Diagram ( top view ) for the 80 pin quad flat pack
PC1/LCSYNC/AIN PC0/LCF32K/AIN
PC5/AIN
PC4/AIN
PC3/AIN
PC2/AIN
PB7/AIN
PB6/AIN
PB5/AIN
PB4/AIN
PB3/AIN
PC6/AIN PC7/AIN STOP/OSCOUT OSCIN S16/PD7 S15/PD6 S14/PD5 S13/PD4 S12/PD3 S11/PD2 S10/PD1 S09/PD0 VPP/TEST S8/PF7 S7/PF6 S6/PF5 S5/PF4 S4/PF3 S3/PF2 S2/PF1 S1/PF0 BP16/S-0/PG7 BP15/S-1/PG6 BP14/S-2/PG5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
PB2/AIN
GNDP
VDDP
GND
VDD
PB1/AIN PB0/AIN PA7/DOUT/AIN PA6/SDA/AIN PA5/SCL/AIN PA4/AIN PA3/AIN PA2/AIN PA1/CP2/AIN PA0/CP1/AIN RESET VSSA VDDA RDSREF MPX RDSFIL PE5/S22 RDSCOMP/PE4/S21 S20/PE3 S19/PE2 S18/PE1 S17/PE0 VLCD1/5 VLCD2/5
ST 7282 B5
53 52 51 50 49 48 47 46 45 44 43 42
41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 BP4/PH3 BP3/PH2 BP2/PH1 BP1/PH0 VLCD VLCD4/5 BP7/S-10/PH6 BP6/S-11/PH5 BP13/S-3/PG4 BP12/S-4/PG3 BP11/S-5/PG2 BP10/S-6/PG1 BP5/S-12/PH4 BP9/S-7/PG0 BP8/S-9/PH7 VLCD3/5
CONDIAG.DS 4
Family ST7
Issuer Ref. PG-RO
Chrono 97115 7282A5B5
March 26, 1997
Previous Ref Page 21/23
Edition Target C
ST7282A5 - ST7282B5 - ROM FROM EPROM
4.2 P I N
DESCRIPTION
Ports A, B, C, D, E, F, G are described on page 18 STOP/OSCOUT STOP/OSCIN VPP/TEST VLCD VLCD 4/5 VLCD 3/5 VLCD 2/5 VLCD 1/5 NC RDSCOMP RDSFIL MPX RDSREF VSSA VDDA VDD GND VDDP GNDP I/O Pins for the RDS module (see seperate spec) (not connected) - must be left open Voltage levels for the LCD module Test pin Oscillator pins
Analog voltages for the ADC and filter module
Supply voltage
Peripheral supply voltage
Reset
Reset pin - active low
Family ST7
Issuer Ref. PG-RO
Chrono 97115 7282A5B5
March 26, 1997
Previous Ref Page 22/23
Edition Target C
ST7282A5 - ST7282B5 - ROM FROM EPROM
5 RELATED DOCUMENTS
ST7 ADC2- SD 70K L138 ed. A ST7 RDS BD - SD 70K L145 ed. B ST7 RDS GB - SD 70K L144 ed. B ST7 RDS FI - SD 70K L129 ed. C ST7 SIO - # 96098 ed. B ST7 OSCILLATOR - SD 70K L163 ed. A ST7 LCIO1 - SD 70K L135 ed. C ST7 IO3 - SD 70K L136 ed. B ST7 LCD4 - SD 70K L140 ed. B ST7 TIM4 - SD 70K L130 ed. A ST7 WD2 - SD 70K L137 ed. A ST7 EEPROMeep2a
6 HISTORIC
Below, the differences between the original specification # 96096 ed. B (ST7282B5) and the present specification # 97115 ed. B:
Page # modified in original spec 96096 1 2 3 Block diagram : S21, S22
Modifications
New page 2 3 3
Quick reference : 2 commercial products VLCD changed from target of 10V to < 7V LU on all pins changed from target of class A to class A on all pins except pin VDDA (52) class C Islow changed from target of 1mA to 2mA; Ihalt changed from target of 10µA to 100µA ; VLCD changed from target of 10V to 7V. Address mapping : TIMER EEPROM : 2 bank 256 bytes Oscillator
4 7 21
4-5 7 - 8 - 9 - 10 19 20 21 23
23
Connection diagram : S21, S22 Related documents, sales types
7 ORDERING INFORMATION
SALES TYPE ST7282A5Q6B/XXX ST7282B5Q6B/XXX OPTIONS NO LCD -40°C to 85°C WITH LCD PQFP80 TEMP RANGE PACKAGE
The user code to be delivered to SGS-THOMSON must be in Motorola S.format (.S19) and must
n n n
NOT include EEPROM content.
Family ST7
Issuer Ref. PG-RO
Chrono 97115 7282A5B5
March 26, 1997
Previous Ref Page 23/23
Edition Target C