SGS-Thomson ST7282A5 free download

File name ST7282.pdf

ST7282A5 - ST7282B5 ROM FROM EPROM PRELIMINARY DATASHEET s s ST72-Core Controller/Driver for max. 20 Ч 16, 28 Ч 8 or 32 Ч 4 LCD segments (ST7LCD4) 56 bytes LCD-RAM 864 bytes data RAM 512 bytes EEPROM (eep2a) 32Kbytes program ROM 24 digital I/O (ST7 IO3) with pull up, interrupt input, analog input, push-pull/ open drain output 36 LCD/IO combi pins (ST7 LCIO1) with pull-up, interrupt input, push-pull, open drain output, LCD output 16 bit reload timer (ST7TIM4) Watchdog Timer (ST7 WD2) 8 bit synchronous serial I/O (ST7SIO) s s s s s s s s s s s s s s Group & Block Sync Module for RDS (ST7 RDS GB) RDS filter (ST7 RDS FI) LCD Synchro IN / Out System Frequency 8.55 MHz 8 bit A/D Converter (ST7ADC2) s RDS Demodulator (ST7 RDS BD) s n n Family ST7 Issuer Ref. PG-RO Chrono 97115 7282A5B5 March 26, 1997 Previous Ref Page 1/23 Edition Target C ST7282A5 - ST7282B5 - ROM FROM EPROM 1 GENERAL DESCRIPTION Figure 1. Block Diagram S 1 6 /P D 7 S 1 5 /P D 6 S 1 4 /P D 5 S 1 3 /P D 4 S 1 2 /P D 3 S 1 1 /P D 2 S 1 0 /P D 1 S 9 /P D 0 S 8 /P F 7 S 7 /P F 6 S 6 /P F 5 S 5 /P F 4 S 4 /P F 3 S 3 /P F 2 S 2 /P F 1 S 1 /P F 0 B P 1 6 /S 0 /P G 7 B P 1 5 /S - 1/P G 6 B P 1 4 /S - 2/P G 5 B P 1 3 /S - 3/P G 4 B P 1 2 /S - 4/P G 3 B P 1 1 /S - 5/P G 2 B P 1 0 /S - 6/P G 1 B P 9 /S -7 /P G 0 Seg. Drv. PORT D ST7 LCIO VDDP VSSP VDDA VSSA PC0/AIN PC1/AIN PC2/AIN PC3/AIN PC4/AIN PC5/AIN PC6/AIN PC7/AIN PB0/AIN PB1/AIN PB2/AIN PB3/AIN PB4/AIN PB5/AIN PB6/AIN PB7/AIN PO R T C S T 7 IO 3 PO RT B S T 7 IO 3 P A 0 /C P 1/A IN P A 1 /C P 2/A IN P A 2 /A IN P A 3 /A IN P A 4 /A IN P A 5 /A IN P A 6 /A IN P A 7 /A IN R D S C O M P /P E 4 /S 2 1 VD D VS S V P P /T E S T R E SE T MPX R D S F IL RDS REF O S C IN O S C O U T /S T O P S 2 2 /P E 5 S 2 1 /P E 4 /R D S C O M P O s c - O p tio n PORT A AD C ST 7 A DC 2 ST7 LCIO S IO RDS DEM OD. ST 7 R DS B D G R P & B LK S Y N C ST 7 R D S G B R D S F ilte r ST7 LCIO ST 72 CO R E ST 7 R DS F I O S C IL L A T O R S T 7 O S C IL L A T O R LCD C O N TR OL S T7 LC D 4 S eg . D rv ./P or t E E E P R O M 51 2 W A TC H D O G ST 7 W D 2 Seg. Drv. PORT F T IM E R 1 6 b it S T 7 T IM 4 RA M 864 3 2K R O M Seg. Drv. PORT G LCD RAM 5 6B y te PO R T H S T 7 L C IO ST7 IO3 8 .5 5 M H z S T 7 L C IO BP8/S-9/PH7 BP7/S-10/PH6 BP6/S-11/PH5 BP5/S-12/PH4 BP4/PH3 BP3/PH2 BP2/PH1 BP1/PH0 VLCD VLCD 4/5 VLCD 3/5 VLCD 2/5 VLCD 1/5 S17/PE0 S18/PE1 S19/PE2 n n n Family ST7 Issuer Ref. PG-RO Chrono 97115 7282A5B5 March 26, 1997 S20/PE3 Previous Ref Page 2/23 Edition Target C ST7282A5 - ST7282B5 - ROM FROM EPROM 1.1 Quick Reference The ST7282A5/B5 is a 32K ROM version of the ST72 family, using the ST72CORE and N-Well technology. It is derived from EPROM M4 version replacing EPROM by ROM. Two different commercial products are supported by this device : ST7282A5 (no LCD driver) functionnality described in specification SD70KL1618 ed. F) and ST7282B5 (LCD driver) functionnality described in specification 96096 ed. B). It