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PILLAR ROCK
Table of Contents
Page
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Montevina Mobile Platform CUSTOMER REFERENCE BOARD
Merom
Fab 3
Rev. 1.0
Description TITLE PAGE NOTES Penryn (1 of 2) Penryn (2 of 2) CPU Thermal Sensor CANTIGA (1 OF 6) CANTIGA (2 OF 6) CANTIGA (3 OF 6) CANTIGA (4 OF 6) CANTIGA (5 OF 6) CANTIGA (6 OF 6) CANTIGA STRAP & CAMARILLO DDR2 SODIMM 0 DDR2 SODIMM 1 DDR2 TERMINATION CRT LVDS TVO PCIE GRAPHICS XDP ICH9M (1 of 4) ICH9M (2 of 4) ICH9M (3 of 4) ICH9M (4 of 4) PCI-E Slots (1 & 2) PCI-E Slots (3,4 & 5) High Definition Audio HDA Power Supply USB 1.1/2.0 SATA (1 of 3) SATA (2 and 3 of 3) PCI Edge Connector(Gold finger) LAN Boaz LAN Docking and SPI CK505 DB800 & Buffers FWH and I/O Port Expander SIO Legacy Support H8 2116 KBC(1 of 2) H8 2116 KBC(2 of 2) PS2 LPC Slot, TPM Header, DOCKING TPS51120 SYSTEM POWER VR DDR2 VR CANTIGA VR DDR VREF GRAPHICS CORE VR SYSTEM CHARGER VR SYSTEM CHARGER BATTERY IMVP-6 CONTROLLER IMVP-6 DRIVERS&FETS CPU Decoupling DISCHARGE CIRCUITS Start Up Sequence Sleep control POWER SEQUENCING
C
B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58
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Pillar Rock
Title TITLE PAGE Size A Date:
3
Intel Confidential
A
Document Number 355659 Tuesday, August 28, 2007
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Rev 1.0 Sheet 1
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MONTEVINA CUSTOMER REFERENCE PLATFORM
SCHEMATIC ANNOTATIONS AND BOARD INFORMATION
D
Voltage Rails
POWER PLANE +VBATA +VBAT +VBATS +V12S -V12A -V12S +V5A +V5 +V5S +V3.3A +V3.3M +V3.3M_CK505 +V3.3 +V3.3S +V1.8 +V1.5S +V1.05M +V1.05S +V0.9 +VCC_CORE +VCC_GFXCORE VOLTAGE 6V-14.1V 6V-14.1V 6V-14.1V 12V -12V -12V 5V 5V 5V 3.3V 3.3V 3.3V 3.3V 3.3V 1.8V 1.5V 1.05V 1.05V 0.9V 0.35V-1.5V 0.7V-1.25V ACTIVE IN S0/M0, S0/M0, S0/M0 S0/M0 S0/M0, S0/M0 S0/M0, S0/M0, S0/M0 S0/M0, S0/M0, S0/M0, S0/M0, S0/M0 S0/M0, S0/M0 S0/M0, S0/M0 S0/M0, S0/M0 S0/M0 (S3-S5)/M1, (S3-S5)/M-off (S3-S5)/M1, (S3-S5)/M-off (S3-S5)/M1, (S3-S5)/M-off (S3-S5)/M1, (S3-S5)/M-off S3/M1, S3/M-off (S3-S5)/M1, (S3-S5)/M-off (S3-S5)/M1, S3/(M-off w/WOL_EN) (S3-S5)/M1 S3/M1, S3/M-off (S3-S5)/M1, S3/M-off (S3-S5)/M1 (S3-S5)/M1, S3/M-off GMCH, ICH core, and FSB rail DDR command & control pull up. CPU core rail GMCH Graphics core rail LAN Clock, MCH DDR core DESCRIPTION Battery Battery Battery Only on Only on Only on Rail in Mobile Power Mode Rail in Mobile Power Mode Rail in Mobile Power Mode in DT Power Mode in DT Power Mode in DT Power Mode
I
2
C / SMB Addresses
Address 1101 001x 1101 110x 1010 000x 1010 010x 0011 000x 0011 010x 0100 110x 0011 xxxx 0111 001x 0011 110x 1001 100x 1001 101x 0001 110x 0001 111x 0011 000x 0011 001x 1001 100x TBD TBD TBD TBD TBD TBD TBD TBD Hex D2 DC A0 A4 30 34 4C 3x 72 3C 98 9A 1C 1E 30 32 98 TBD TBD TBD TBD TBD TBD TBD TBD Bus SMB_ICH_M3 SMB_ICH_M3 SMB_ICH_M2 SMB_ICH_M2 SMB_ICH_M2 SMB_ICH_M2 SMB_ICH_M2 SMB_ICH ALS EMA SMB_THRM SMB_THRM SMB_BS SMB_BS SMB_BS SMB_BS SMB_BS SMB_ME SMB_ICH_A1 SMB_ICH_A1 SMB_ICH_A1 SMB_ICH_A1 SMB_ICH_S4 SMB_ICH_S4 SMB_ICH_S4
Jumper / Switch Settings
Jumper J1G1 J1G3 J1G5 J2B2 J2G1 J2H2 J3C1 J3J2 J4H1 J4J2 J5G1 J5H2 J7A1 J7E1 J7H1 J7H2 J8B1 J8B2 J8C1 J8F2 J8G1 J8G3 J8G4 J8G5 J8G6 J8H1 J9C1 J9D1 J9F1 J9G2 J9H1 J9H2 J9H3 J9H4 Default 1-2 1-2 1-2 All OPEN 1-X All OPEN 1-2, 3-4 1-X 1-X 1-2 1-X 1-X 1-2 1-2 1-2 1-X 1-2 1-2 1-X 1-X 1-X 1-X 1-X 1-2 1-X 1-2 1-X 1-X 1-2 1-2 1-X 1-2 1-X 1-X Description BSEL2 BSEL1 BSEL0 CPU CORE VID Force Shutdown GFX CORE VID CPU thermal sensor Power ON Latch No ME G3 to M1 support SATA Power Enable SRTC RST CMOS Clear In-circuit SMC Programming SIO Reset SATA interlock switch for port0 TPM PHYSICAL PRESENCE PM Lan enable In-circuit SMC Programming SELCETING SPI0 or SPI1 TO BE PROGRAMMED BIOS recovery SV Setup SMC MD2 CRB/SV Detect SMC MD1 KBC disable Boot BIOS Strap PROGRAMMING SPI1 PROGRAMMING SPI0 KSC Enable Boot Block Programming NMI SATA interlock switch for port1 LID Position Virtual Battery Page
Device Clock Generator DB800 Clock Buffer SO-DIMM0 SO-DIMM1 SO-DIMM0 Thermal Sensor SO-DIMM1 Thermal Sensor DDR Thermal Sensor I2C Bus Expander Ambient Lighr Sensor EMA Display CPU Thermal Sensor IMVP6 Amb. Temp. Sensor Battery A Battery B Board ID Port Expander Docking Port Expander Skin Temperature Sensor H8 PCI-Slot3 PCI-Gold Finger PCI-Express Slot1-5 Docking PCIe x16 Slot (PEG) TPM Header ITP-XDP
C
Buses labeled SMB_ICH_xx come out of ICH, via an I2C expander. The rest come out of EC.
PCI Devices
Device Slot 3 LAN IDSEL # AD18 REQ/GNT # 2 2 Interrupts D, C, A, B
(AD24 internal)
Net Naming Conventions
Suffix # = Active Low Signal Prefix H = Host M = DDR Memory TP = Test Point (does not connect anywhere else)
B
Power States
S0 (Full on)/M0 S3 (Suspend to RAM)/M1 S3 (Suspend to RAM)/Moff SLP_S3# S4_STATE# HIGH HIGH LOW LOW HIGH HIGH HIGH LOW LOW LOW LOW SLP_S4# HIGH HIGH HIGH HIGH HIGH HIGH LOW LOW SLP_S5# HIGH HIGH HIGH HIGH HIGH LOW HIGH LOW SLP_M# HIGH HIGH LOW LOW +V*A ON ON ON ON ON ON ON ON
+V3.3M_WOL ON ON OFF ON ON ON
S3 (Suspend to RAM)/Moff w/WOL_EN LOW S4 (Suspend to Disk)/M1 S5 (Soft Off)/M1 S4 (Suspend to Disk)/Moff S5 (Soft Off)/Moff LOW LOW LOW LOW
Wake Events
A
Wake Events RI# from serial port PME# from PCI, mini PCI slot/device, LPC slot/device PCI Express, mini PCI Express, Express-card wake event Wake on LAN LID switch attached to SMC USB HDA wake on ring SmLink for AOLII Hot Key from Scan matrix keyboard PS/2 Keyboard/mouse PWRBTN# Netdetect
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State Supported S3 S3 S3 S3/M1 S3 S3 S3 S3 S3 S3 S3 S3, S4, S5 / M1
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HIGH HIGH LOW LOW OFF OFF
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+V1.05M ON ON +V3.3M ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF OFF OFF
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+V1.8/+V0.9 ON ON ON ON ON ON OFF OFF ON ON ON OFF OFF OFF OFF
+V5/+V3.3 ON
-s p
+V*S ON OFF OFF OFF OFF OFF OFF OFF Clocks ON only MCH BCLK OFF OFF only MCH BCLK only MCH BCLK OFF OFF
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35 35 35 52 56 49 5 56 56 31 21 21 39 38 30 23 40 39 34 23 63 40 64 40 40 31 34 34 40 42 42 31 41 41
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SL No 1 2 3 NO_STUFF L5F1 4 5 6
Changes for Pillar Rock with PM GMCH SKU
STUFF
U6E2, U6E3, U6E4
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R5E4, R5T5, R5T8, R5T9, R5T10, R5T12, R5T17 Page 21 39 39 39 39 39 39 39 40 40 40 57 57 57 57 57 57 64 Reference CR7H1 CR1B1 CR1B2 CR1B3 CR1B4 CR1B5 CR1B6 CR1B7 CR9G1 CR9G3 CR9G2 CR5H6 CR5H3 CR5H7 CR5H5 CR5H4 CR7H3 CR8G1
D
R5E5, R5F9, R5T16, R5U3, R5U11, R5U14, R5U21, R6V1 C5E8, C5E9, C5E11, C5E12, C5E13, C5E14, C5E15, C5T12, C5T13, C5U1, C5U2, C5U3 FB5F1, FB5F2, FB5T1 J2G1(3 4), J2G1(5 6), J2G1(7 8)
C5E8,C5E9,C5T13,C5U3 with 0 Ohm 0402 size res IPN A93549-001
J2G1(1 2), J2G1(13 14)
C
LEDs and Switches
LED xTA Activity VID0 VID1 VID2 VID3 VID4 VID5 VID6 Num Lock Scroll Lock Caps Lock S3 M0/M1 S4 S5 S0 System Power Good LT Status
B
Switch SW9H1 SW9H3 SW9H2 SW7J1 SW1C1 SW1C2 SW8E1 Default 1 - 2 1 - 2 1 - 2 1 - 2 Description Virtual Docking Virtual Battery LID Switch Hybrid GFX switch Power Button Reset Button Net Detect Page 41 41 41 41 56 56 56
PCB Footprints
1 3 2
SOT-23
1 2 3
5
SOT23-5
As seen from top
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Pillar Rock
Title NOTES Size A Date:
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Intel Confidential
A
Document Number 355659 Tuesday, August 28, 2007
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Rev 1.0 Sheet 2
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4,20,35,39,43,52,54
+V1.05S_CPU
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H_A#[35:3] H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16
U2E1A
D
CONTROL
6 6
H_ADSTB#0 H_REQ#[4:0]
J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 K3 H2 K2 J3 L1 Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A5 C4 D5 C6 B4 A3
A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#
ADS# BNR# BPRI# DEFER# DRDY# DBSY# BR0# IERR# INIT# LOCK#
H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 C1 F3 F4 G3 G2 G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20
H_RS#0 H_RS#1 H_RS#2
H_ADS# 6 H_BNR# 6 H_BPRI# 6 H_DEFER# 6 H_DRDY# 6 H_DBSY# 6 H_BREQ# H_IERR#_R H_INIT# 21 6
R2H2 56
Connect H_IERR# with no stub to the connector J2H1 and then connect to the 56 ohm pull up Resistor R2H2.
R2H3 H_IERR# 56 Place testpoint on H_IERR# with a GND 0.1" away
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#
RESET# RS[0]# RS[1]# RS[2]# TRDY# HIT# HITM# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
H_LOCK# 6 H_CPURST# 6,20 H_RS#[2:0]
6
H_TRDY#
6 NO_STUFF TP1F1 XDP_BPM#0 20
6
H_A#[35:3]
H_HIT# 6 H_HITM# 6
XDP/ITP SIGNALS
XDP_BPM#1 35 XDP_BPM#2 35 XDP_BPM#3 35 XDP_BPM#4 20 XDP_BPM#5 20 XDP_TCK 20 XDP_TDI 20 4,20,35,39,43,52,54 XDP_TDO 20 XDP_TMS 20 XDP_TRST# 20 XDP_DBRESET# 20
+V1.05S_CPU
C
Layout note: no stub on H_STPCLK TP. H_STPCLK# to be routed in daisy chain fashion from ICH to LPC slot and then to CPU. 6 H_STPCLK#_R NO_STUFF TP2F1 21 21 21 H_ADSTB#1 H_A20M# H_FERR# H_IGNNE#
THERMAL
PROCHOT# THERMDA THERMDC THERMTRIP# D21 H_PROCHOT#_D A24 B25 C7
H_THERMDA H_THERMDC 5 5 7,21
R1R4 TP1D1 68 5% NO_STUFF .
Place TP1D1 close to CPU.
6
H_D#[63:0]
A20M# FERR# IGNNE#
. PM_THRMTRIP# should connect to ICH9 and GMCH without T-ing (No stub)
PM_THRMTRIP#
21,43 H_STPCLK#
R2U11 0 21 H_INTR 21,43 H_NMI 21,43 H_SMI#. TP_CPU_RSVD01 TP_CPU_RSVD02 TP_CPU_RSVD03 TP_CPU_RSVD04 TP_CPU_RSVD05 CPU_RSVD06 CPU_RSVD09
STPCLK# LINT0 LINT1 SMI# RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09]
H CLK
BCLK[0] BCLK[1] A22 A21
CLK_CPU_BCLK 35 CLK_CPU_BCLK# 35
Layout Note: TP2F1 should be placed close to J1G7
RESERVED
M4 N5 T2 V3 B2 D2 TP_CPU_RSVD07 D22 TP_CPU_RSVD08 D3 F6
4,20,35,39,43,52,54
+V1.05S_CPU
Penryn_Ball-out_Rev_1p0
H_GTLREF
B
4,20,35,39,43,52,54 XDP_TMS XDP_TDI XDP_BPM#5 R2U4
+V1.05S_CPU 54.9 1% 54.9 1% 54.9 1% 54.9 1% 649
R2U3 R1U6
Layout Note: Place R1U6 close to CPU with stub length <200mils.
XDP_TCK XDP_TRST#
R1T2 R1T3
A
5
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1% .
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NO_STUFF R3P5 1K R3P6 1K NO_STUFF
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Layout note: Zo=55 ohm, 0.5" max for GTLREF.
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R1R16 1K 1% . R1R17 2K 1% .
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C1T1
DATA GRP 3
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6 6 6 6 H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[63:0] 6 6 6 H_DSTBN#1 H_DSTBP#1 H_DINV#1 CPU_TEST1 CPU_TEST2 CPU_TEST3
H_PROCHOT#_D
DATA GRP 2
R1D1 0
H_PROCHOT#
52
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H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15
U2E1B
E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25
D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#
ic t a
D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# COMP[0] COMP[1] COMP[2] COMP[3] DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
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H_D#[63:0] 6 H_DSTBN#2 6 H_DSTBP#2 6 H_DINV#2 6 H_D#[63:0] 6
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ADDR GROUP_0 ADDR GROUP_1
D
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47
C
DATA GRP 0 DATA GRP 0
ICH
H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31
N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 R26 U26 AA1 Y1 E5 B5 D24 D6 D7 AE6
H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
DATA GRP 1
Layout note: Comp0,2 connect with trace length shorter Comp1,3 connect with trace length shorter
Zo=27.4ohm, make than 0.5". Zo=55ohm, make than 0.5".
H_DSTBN#3 6 H_DSTBP#3 6 H_DINV#3 6 COMP0 COMP1 COMP2 COMP3 R2R3 R2R2 R2U1 R2U2 27.4 54.9 27.4 54.9 1% 1% 1% 1%
B
CPU_TEST4
CPU_TEST5 CPU_TEST6 CPU_TEST7 35 CPU_BSEL0 35 CPU_BSEL1 35 CPU_BSEL2 Place C1T1 close to the CPU_TEST4 pin. Make sure CPU_TEST4 routing is reference to GND and away from other noisy signals. 0.1uF 10% NO_STUFF
AD26 C23 D25 C24 AF26 AF1 A26 C3 B22 B23 C21
GTLREF MISC TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2]
H_DPRSTP# 7,21,43 H_DPSLP# 21,43 R1U15 1K 5% . H_DPWR# 6 H_PWRGD 21,43 H_PWRGD_XDP 20
H_CPUSLP# PSI# 52
6,43 TP3E2 NO_STUFF
Penryn_Ball-out_Rev_1p0 Layout: Connect test point TP3E2 with no stub
Place Series Resistor on H_PWRGD_XDP Without Stub
A
Pillar Rock
Title Penryn (1 of 2) Size Document Number Custom 355659 Date:
3
Intel Confidential
Rev 1.0 Sheet 3
1
Tuesday, August 28, 2007
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53,54,55
+VCC_CORE U2E1C
53,54,55
+VCC_CORE
D
C
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18
VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]
VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] VCCA[01] VCCA[02] VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] VCCSENSE VSSSENSE
.
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 G21 CPU_G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 B26 C26
R3T2 is for test purpose only.
9,10,24,47,55 NO_STUFF TP3E1 R3T2 0 . C2U2 270uF 20% . 3,20,35,39,43,52,54 +V1.05S_CPU R3U2 2 0 R3U1 2 0
+V1.05S
1 NO_STUFF 1 NO_STUFF
10,11,24,28,47,55,57
+V1.5S
+VCCA_PROC 53,54,55 +VCC_CORE C3R3 0.01uF 10% . C3R2 10uF 20% .
AD6 AF5 AE5 AF4 AE3 AF3 AE2 AF7 AE7
H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6
52 52 52 52 52 52 52
R1T16 100 1% . VCCSENSE 52
Penryn_Ball-out_Rev_1p0
R1T14 100 1% .
B
A
5
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4
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VSSSENSE 52
Layout Note: Route VCCSENSE and VSSSENSE traces at 27.4 Ohms with 50 mil spacing. Place PU and PD within 1 inch of CPU.
-s p
Layout Note: Place C3R3 near pin-B26
R3R13
0.01 1%
h c
m e
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A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3
U2E1D
VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081]
.c s
VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
m o
D
C
B
Penryn_Ball-out_Rev_1p0 .
A
Pillar Rock
Title Penryn (2 of 2) Size Custom Date:
3
Intel Confidential
Document Number 355659 Tuesday, August 28, 2007
2
Rev 1.0 Sheet 4
1
of
58
5
4
3
2
1
7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57
+V3.3S
CPU Thermal Sensor
7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S C3N10 0.1uF 20% . U3B3 1 VDD R3B19 10K 5% . R3N22 10K 5% . R3N19 10K 5% .
D
Layout Note: Route H_THERMDA and H_THERMDC on same layer w/ 10 mil trace & 10 mil spacing. Route away from noise sources with ground guard tracks on each side. C3N11 J3C1 3 3 H_THERMDA H_THERMDC THERM_DXP R3N27 0 THERM_DXN R3N26 . . 1000pF 5% 0 NO_STUFF
R3N21 10K 5% NO_STUFF ADT_THERM_DXP ADT_THERM_DXN ADT_THM#
SMBCLK SMBDAT OS#/A0 GND
8 7 6 5
THRM_ALERT#
SMB_THRM_CLK 12,40,43
2 3 4
1 3
2X2HDR
2 4
D+ DT_CRIT#
LM95245C
J4A1 3Pin_Recepticle
NOTE : R3N27, R3N26, C3N11 are placeholders for the new thermal sensor (NS LM95245).
Note: No-Stuff R3N20 for normal operation, No Stuff (R9G11, Sheet 40) if R3N20 is stuffed
2 THERMDP
1 THERMDN
NO_STUFF
GND0 GND2 GND1 3 4 5 6 GND3
C
J3C1 1-2 3-4
Thermal Diode Connector
Connects the Internal CPU Thermal sensor to the ADT7461A (Default) Connect an external Thermal sensor to the ADT7461A
1-X 3-X
CPU Fan Power Control
11,12,16,17,18,24,28,30,31,32,39,48,49,52,55,56,57 +V5S
B
C3N4 0.1uF 10% .
C3N6 4.7uF 10% .
7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57
EU3B1 _
8
40,43 CPU_PWM_FAN R3N14 15K 1% . OPA567_POSIN
9
V+ TF EN OUT OPA567 + IS IF HS V-
C3B5 1uF 10% .
A
5
w
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la .
3
. OPA567_ISIN_R OPA567_NEGIN R3N6 20K 5% .
2
to p
VOUT_OPAMP
-s p
CPU_TACHO_R_FAN
h c
+V3.3S R2N4 0 .
m e
ic t a
R3N20 0 NO_STUFF
SMB_THRM_DATA 12,40,43 PM_THRM# 12,23,40,43
.c s
m o
D
C
B
R2N6 1K 1% .
1 12
10 11
3
CPU_TACHO_FAN 40,43
4 5 13 6 7
CR2N2 BAT54
Note: No-Stuff R2N4 to Disable PWM control of FAN
1
R3N8 1.74K 1% .
J2B3
CONN3_HDR . R3N10 3.32K 1% .
3 2 1
3 2 1
Pillar Rock
Title CPU Thermal Sensor & Fan Size A Date:
4 3
Intel Confidential
A
Document Number 355659 Tuesday, August 28, 2007
2
Rev 1.0 Sheet 5
1
of
58
5
4
3
2
1
U5E1A 3 H_D#[63:0] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
D
10
+VCCP_GMCH
R4E8 221 1% .
H_SWING H_SWING
R4E5 100 1% .
C4F1 0.1uF 20% .
H_RCOMP
C
R4E2 24.9 1% .
B
10
+VCCP_GMCH
R4E7 1K 1% . H_AVREF
R4E4 2K 1% .
H_DVREF
A
5
w w
H_VREF & H_DVREF Default= R4E6(STUFF) R4E3, R4F1(NO_STUFF) on Sheet # 65
H_AVREF & H_DVREF shorted togther (same voltage divider) For EV= R4E6(NO_STUFF) R4E3, R4F1 (STUFF) on Sheet # 65 H_AVREF & H_DVREF can be schoomed independently for EV (separate voltage divider)
. w
NO_STUFF R4E6 0 .
p la
3,20 H_CPURST# 3,43 H_CPUSLP# C4E12 0.1uF 10%
to
H_SWING H_RCOMP
-s p
C5 E3 H_SWING H_RCOMP C12 E11 H_CPURST# H_CPUSLP# A11 B11 H_AVREF H_DVREF
CANTIGA_1p2
F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6
H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63
H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#
A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20
h c
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2
H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9
m e
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
H_A#[35:3]
3
HOST
ic t a
H_ADS# 3 H_ADSTB#0 3 H_ADSTB#1 3 H_BNR# 3 H_BPRI# 3 H_BREQ# 3 H_DEFER# 3 H_DBSY# 3 CLK_MCH_BCLK 35 CLK_MCH_BCLK# 35 H_DPWR# 3 H_DRDY# 3 H_HIT# 3 H_HITM# 3 H_LOCK# 3 H_TRDY# 3 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 3 3 3 3 3 3 3 3 3 3 3 3 H_RS#[2:0] 3
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m o
D
C
J8 L3 Y13 Y1 L10 M7 AA5 AE6
L9 M8 AA6 AE5 B15 K13 F13 B13 B14 B6 F12 C8
H_REQ#[4:0]
3
B
Pillar Rock
Title CANTIGA (1 OF 6) Size A Date: Document Number 355659 Tuesday, August 28, 2007
2
Intel Confidential
A
Rev 1.0 Sheet 6
1
of
58
4
3
5
U5E1B MCH_RSVD_1 MCH_RSVD_2 MCH_RSVD_3 MCH_RSVD_4 MCH_RSVD_5 MCH_RSVD_6 MCH_RSVD_7 MCH_RSVD_8
4
3
2
1
DDR CLK/ CONTROL/COMPENSATION
TP_MCH_RSVD9
M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12
RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9
SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1 SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1 SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1 SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1 SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1 SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF SM_PWROK SM_REXT SM_DRAMRST#
AP24 AT21 AV24 AU20 AR24 AR21 AU24 AV20 BC28 AY28 AY36 BB36 BA17 AY16 AV16 AR13 BD17 AY17 BF15 AY13 BG22 BH21
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR3 M_CLK_DDR4 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#3 M_CLK_DDR#4 M_CKE0 M_CKE1 M_CKE3 M_CKE4 M_CS#0 M_CS#1 M_CS#2 M_CS#3 M_ODT0 M_ODT1 M_ODT2 M_ODT3 SM_RCOMP SM_RCOMP# 13,15 13,15 14,15 14,15 13,15 13,15 14,15 14,15 13,15 13,15 14,15 9,10 14,15
13 13 14 14 13 13 14 14 17 L_BKLT_CTRL 17 L_BKLT_EN 17,20 L_CTRL_CLK 17,20 L_CTRL_DATA 17 LVDS_DDC_CLK 17 LVDS_DDC_DATA R5U18 0 NO_STUFF TP5F1 R5T11 2.37K 1% . +V1.8_GMCH 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 . LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3 L_VDD_EN_R LVDS_VBG
U5E1C
L32 G32 M32 M33 K33 J33 M29 C44 B43 E37 E38 C41 C40 B37 A37
L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK
D
MCH_RSVD_14 TP_MCH_RSVD15 TP_MCH_RSVD17 TP_MCH_RSVD20
T24 B31 M1 AY21 B2 BG23 BF23 BH18 BF18
RSVD14
RSVD15 RSVD17 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25
17 LVDS_VDD_EN LVDS_IBG
MCH_RSVD_21 MCH_RSVD_24 MCH_RSVD_25
TP_MCH_RSVD22 TP_MCH_RSVD23
BF28 SM_RCOMP_VOH BH28 SM_RCOMP_VOL AV42 AR36 BF17 BC36 B38 A38 E41 F41 F43 E43
SM_PWROK 46 SM_REXT R4R7 499 TP_SM_DRAMRST# 1% . DREFCLK 35 DREFCLK# 35 DREFSSCLK 35 DREFSSCLK# 35 CLK_PCIE_3GPLL 35 CLK_PCIE_3GPLL# 35
NO_STUFF M_VREF_MCH R5R5 1K 1% NO_STUFF 46,48 NOTE:SM_DRAMRST# Would be needed for DDR3 only
H48 D45 F40 B40
LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3
DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# PEG_CLK PEG_CLK#
CLK
15
MCH_TCK MCH_TDI MCH_TDO MCH_TMS 35 MCH_BSEL0 35 MCH_BSEL1 35 MCH_BSEL2 12 MCH_CFG_[17:3]
AL34 AK34 AN35 AM35
ME_JTAG_TCK ME_JTAG_TDI ME_JTAG_TDO ME_JTAG_TMS
PCI-EXPRESS
NOTE: All LVDS data signals/and its compliments SHOULD BE ROUTED DIFFERENTIALLY
C
15 15 15
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3
AE41 AE37 AE47 AH39 AE40 AE38 AE48 AH40
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
DMI_TXN[3:0] 22 18 18 18 DMI_TXP[3:0] 22 TVA_DAC TVB_DAC TVC_DAC
MCH_CFG_3 MCH_CFG_4 MCH_CFG_5 MCH_CFG_6 MCH_CFG_7 MCH_CFG_8 MCH_CFG_9 MCH_CFG_10 MCH_CFG_11 MCH_CFG_12 MCH_CFG_13 MCH_CFG_14 MCH_CFG_15 MCH_CFG_16 MCH_CFG_17
MCH_CFG_18 12 MCH_CFG_19 12,19 MCH_CFG_20 TP5F2
B
23 PM_SYNC# 3,21,43 H_DPRSTP# 40 PM_EXTTS#0_EC 13,14 TS#_DIMM0_1 23 DELAY_VR_PWRGOOD 3,21 PM_THRMTRIP# 23,43,52 PM_DPRSLPVR
R5F10 MCH_CFG_20_R 0 NO_STUFF . PM_SYNC#_R R5F13 R29 R4T2 PM_DPRSTP#_R 0 B7 0 N33 R5P2 PM_EXTTS#1_R P32 . 0 AT40 . R4R11 100 RST_IN#_MCHAT11 . R4T3 0 THRMTRIP#_R T20 R5U31 0 DPRSLPVR_R R32
GRAPHICS VID
T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 T28
CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20
AE35 DMI_RXN0 AE43 DMI_RXN1 AE46 DMI_RXN2 AH42 DMI_RXN3 AD35 DMI_RXP0 AE44 DMI_RXP1 AF46 DMI_RXP2 AH43 DMI_RXP3
DMI_RXN[3:0]
22
Layout Note: Place 150 Ohm termination resistors close to GMCH
DMI
DMI_RXP[3:0]
22
DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4
B33 B32 G33 F33 E33
GFX_VR_EN
C34
9,10
A
HDA
R5D1 20 1%
. . TP_MCH_NC1 PLT_RST# 19,22,25,26,38,41,57 TP_MCH_NC2 TP_MCH_NC3 TP_MCH_NC4 TP_MCH_NC5 TP_MCH_NC6 TP_MCH_NC7 TP_MCH_NC8 TP_MCH_NC9 TP_MCH_NC10 TP_MCH_NC11 TP_MCH_NC12 TP_MCH_NC13 TP_MCH_NC14 TP_MCH_NC15 +V1.8_GMCH TP_MCH_NC16 TP_MCH_NC17 TP_MCH_NC18 TP_MCH_NC19 TP_MCH_NC20 TP_MCH_NC21 TP_MCH_NC22 R5D4 TP_MCH_NC23 80.6 TP_MCH_NC24 TP_MCH_NC25 1% SM_RCOMP SM_RCOMP# 1% 80.6 R5D3
5
w
R5R1 20 NO_STUFF 1%
BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1
w w
MISC NC
CANTIGA_1p2
NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25
la .
CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC# TSATN# N28 M28 G36 E36 K36 H36 B12 HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC B28 B30 B29 C29 A28
ME
AH37 AH36 AN36 AJ35 AH34 MCH_CLVREF_R NO_STUFF
0 R5D9
t p
GFXVR_VID_0 GFXVR_VID_1 GFXVR_VID_2 GFXVR_VID_3 GFXVR_VID_4
GFXVR_EN 49
p o
49 49 49 49 49 9,10 CL_CLK0 23 CL_DATA0 23 MPWROK 23,46 CL_RST#0 23 MCH_CLVREF
-s
16 16 R5D10 1K 1% R5D12 511 1% .
Layout Note: Place 150 Ohm termination resistors close to GMCH
R5T4 R5T5 R5T6
h c
R5U4 R5U7 R5U6 16 16 16 150 1% 150 1% 150 1% R5D11 0 NO_STUFF
R5U9 0 5% R5U8 0 5% R5U5 0 . 5% . 150 1% . 150 1% 150 1%
18 TV_DCONSEL0_MCH 18 TV_DCONSEL1_MCH
CRT_BLUE
m e
****
A41 H38 G37 J37 B42 G38 F37 K37
LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3
GRAPHICS
R5R4 1K 1%
MCH_TVA_DAC F25 MCH_TVB_DAC H25 MCH_TVC_DAC K25
ic t a
H47 E46 G40 A40 LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3 TVA_DAC TVB_DAC TVC_DAC TV_RTN
.c s
PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15 J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46 J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46
PEG_COMPI PEG_COMPO
T37 T36
m o
10 PEG_COMP R5T3 49.9 PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15 PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15 PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9 PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15 PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8 PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15
+VCC_PEG
PEG_RX#[15:0]
19
D
RSVD ME JTAG ME JTAG CFG CFG PM PM
LVDS LVDS TV TV
PEG_RX[15:0] 19
PEG_TX#[15:0] 19
C
H24
C31 E32
TV_DCONSEL_0 TV_DCONSEL_1
E28 G28 J28 G29 H32 J32 J29 E29 L29
PEG_TX[15:0] 19
CRT_BLUE CRT_GREEN CRT_RED CRT_IRTN CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC
CRT_GREEN CRT_RED
VGA VGA
16 CRT_DDC_CLK_MCH 16 CRT_DDC_DATA_MCH R5U10 30.1 HSYNC . 1.02k CRTIREF R5T7 0.5% . VSYNC R5U11 30.1 .
CRT_HSYNC CRT_VSYNC
B
CLK_MCH_OE# PM_EXTTS#0_EC PM_EXTTS#1_R 15
CANTIGA_1p2 5,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 9,10 +V1.8_GMCH R5D5 1K 0.10% EV_VCC_V1.05_CLVREF0 R5D8 3.01k 1% C5R2 0.01uF 10% 402 +V3.3S
R5U13 R5U12 R5P5
10K 10K 10K
+V1.25S_1.05M_CANTIGA
SM_RCOMP_VOH C5R4 2.2uF 10% .
DDPC_CTRLCLK 19 DDPC_CTRLDATA 19 SDVO_CTRLCLK 19 SDVO_CTRLDATA 19 CLK_MCH_OE# 35 MCH_ICH_SYNC# 23 MCH_TSATN# 41
C5D3 0.1uF 10% .
SM_RCOMP_VOL
R7V4 R7V3 R7V8 R7V23 R5F9
33 33 33 33 0
NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF
NO_STUFF
HDA_CODEC_BCLK HDA_CODEC_RST# HDA_SDIN HDA_CODEC_SDATAOUT HDA_CODEC_SYNC IMPORTANT NOTE: When the Resistors R8E7, R7H3 (Page-28) are mounted, then the resistors R7V4, R7V3, R7V8, R7V23, R5F9 should be NO_STUFF.
HDA_BIT_CLK 21,27 HDA_RST# 21,27 HDA_SYNC 21,27 HDA_SDOUT 21,27 HDA_SDIN3 21,27
R5D6 1K 0.10%
C5R1 0.01uF 10% 402
C5R3 2.2uF 10% .
.
Pillar Rock
Title CANTIGA (2 OF 6) Size A Date: Document Number 355659 Tuesday, August 28, 2007
2
Intel Confidential
A
.
Rev 1.0 Sheet 7
1
of
58
4
3
5
4
3
2
1
13 M_A_DQ[63:0]
U5E1D M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
14 M_B_DQ[63:0]
U5E1E M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
D
C
B
AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12
SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63
CANTIGA_1p2
SA_BS_0 SA_BS_1 SA_BS_2 SA_RAS# SA_CAS# SA_WE#
BD21 BG18 AT25 BB20 BD20 AY20
M_A_BS0 13,15 M_A_BS1 13,15 M_A_BS2 13,15 M_A_RAS# 13,15 M_A_CAS# 13,15 M_A_WE# 13,15
SYSTEM
DDR
A
5
w
w w
la .
4
to p
DDR
SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14
BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14
M_A_A[14:0] 13,15
SYSTEM
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7
AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
M_A_DQS[7:0]
13
B
SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7
A
AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7
M_A_DM[7:0] 13
M_A_DQS#[7:0]
13
-s p
h c
AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3
m e
CANTIGA_1p2
SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
SB_BS_0 SB_BS_1 SB_BS_2 SB_RAS# SB_CAS# SB_WE#
BC16 BB17 BB33 AU17 BG16 BF14
a
SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7
SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14
MEMORY
MEMORY
ic t
AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2 AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5
M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14
.c s
M_B_BS0 14,15 M_B_BS1 14,15 M_B_BS2 14,15
M_B_RAS# 14,15 M_B_CAS# 14,15 M_B_WE# 14,15
m o
14 14
D
M_B_DM[7:0] 14
M_B_DQS[7:0]
M_B_DQS#[7:0]
C
AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33
M_B_A[14:0] 14,15
B
Pillar Rock
Title CANTIGA (3 OF 6) Size A Date:
3
Intel Confidential
A
Document Number 355659 Tuesday, August 28, 2007
2
Rev 1.0 Sheet 8
1
of
58
5
4
3
2
1
49 U5E1G 7,10 +V1.8_GMCH
+VGFX_CORE 10,15,35,47,55 +V1.05M R5U3 0.002 1% C5U4 270uF 20% SMC7343 Place close to the GMCH C5T3 22uF 20% SMC0805 . C5R11 0.22uF 20% SMC0603 C5T1 0.22uF 20% SMC0603 C5T4 0.1uF 10% SMC0402 . +VCC_GMCH
D
AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32 AY32 AW32 AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29 AW29 AV29 AU29 AT29 AR29 AP29 BA36 BB24 BD16 BB21 AW16 AW13 AT13 VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36/NC VCC_SM_37/NC VCC_SM_38/NC VCC_SM_39/NC VCC_SM_40/NC VCC_SM_41/NC VCC_SM_42/NC VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16
Cavity Capacitors
49
+VCC_GFXCORE
7,10
+V1.25S_1.05M_CANTIGA +V1.25S_1.05M_CANTIGA For Teenah STUFF: NO_STUFF: For Cantiga STUFF: NO_STUFF:
2
10,15,35,47,55 +V1.05M
1 0.002 NO_STUFF
R4F6 .
R3F1
R3F1 R4F6 R4F6 R3F1
Pins BA36, BB24, BD16, BB21, AW16, AW13, AT13 could be left NC for DDR2 boards
VCC SM
2
1 0.002
49
+VCC_GFXCORE R3F2 0.002 1%
49
+VGFX_CORE
C
4,10,24,47,55
+V1.05S
POWER
VCC_SM_36 VCC_SM_37 VCC_SM_38 VCC_SM_40 VCC_SM_42 +VGFX_CORE
3
0.002 1% NO_STUFF
+ C4T7 330uF 20%
3
+ C4T5 330uF 20%
smc7343_TAK
smc7343_TAK
R4U5
Place close to the GMCH
R5C6
0.002 1%
A
49 VCC_AXG_SENSE 49 VSS_AXG_SENSE
AJ14 AH14
VCC_AXG_SENSE VSS_AXG_SENSE
Route VCC_AXG_SENSE and VSS_AXG_SENSE differentially
CANTIGA_1p2
5
w
w w
VCC SM LF
VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7
AV44 BA37 AM40 AV21 AY5 AM10 BB13
la .
+VCCSM_LF1 +VCCSM_LF2 +VCCSM_LF3 +VCCSM_LF4 +VCCSM_LF5 +VCCSM_LF6 +VCCSM_LF7
Place C5C7 where LVDS and DDR2 taps.
C5C7 0.1uF 10% SMC0402 .
C5C8 330uF 20% SMC7343_75h
C5D2 22uF 20% SMC0805 .
C5D1 22uF 20% SMC0805 .
C5R13 0.1uF 10% NO_STUFF
PLACE ON THE EDGE
VCC GFX
CANTIGA_1p2
C4R4 0.1uF 10% SMC0402 .
C4R8 0.1uF 10% SMC0402 .
C4R5 0.22uF SMC0402
C4R6 0.22uF SMC0402
C5R10 0.47uF SMC0402
C5R7 1.0uF 20% SMC0402
C5R8 1.0uF 20% SMC0402
VCC NCTF
B
Y26 AE25 AB25 AA25 AE24 AC24 AA24 Y24 AE23 AC23 AB23 AA23 AJ21 AG21 AE21 AC21 AA21 Y21 AH20 AF20 AE20 AC20 AB20 AA20 T17 T16 AM15 AL15 AE15 AJ15 AH15 AG15 AF15 AB15 AA15 Y15 V15 U15 AN14 AM14 U14 T14
VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42
VCC GFX NCTF
R4U5 TO BE STUFFED ONLY AS BACKUP OPTION FOR +VGFX_CORE
C5R12 0.1uF 10%
to p
C4R10 0.1uF 10%
C4R11 0.1uF 10%
C4R12 0.1uF 10%
-s p
VCC_SM_42 C4R13 0.1uF 10% NO_STUFF +V1.8
h c
C4T3 0.47uF SMC0603
C4R9 1uF 20% SMC0603 .
m e
C4T2 10uF 20% SMC0805 . C4T6 22uF 20% SMC0805 . Cavity Capacitors
C5T2 0.1uF 10% SMC0402 .
a
ic t
NO_STUFF R5T1 0 . +VCC_MCH_35 7,10
POWER
AG34 AC34 AB34 AA34 Y34 V34 U34 AM33 AK33 AJ33 AG33 AF33 AE33 AC33 AA33 Y33 W33 V33 U33 AH28 AF28 AC28 AA28 AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24 AJ23 AH23 AF23 T32
VCC CORE
.c s
U5E1F
VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35
m o
+VCC_GMCH
D
C
1
1
C4T4 C5T10 0.1uF 1.0uF 10% 20% SMC0402 402 .
2
2
VCC_SM_36
VCC_SM_37
VCC_SM_38
VCC_SM_40
R5T1 is used for internal test purpose only
10,13,14,46,48,55,57 +V1.8_GMCH
VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44
AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23
B
Pillar Rock
Title CANTIGA (4 OF 6) Size A Date: Document Number 355659 Tuesday, August 28, 2007
2
Intel Confidential
A
Rev 1.0 Sheet 9
1
of
58
4
3
5
7,9 +V1.25S_1.05M_CANTIGA +V3.3S_A_TV_CRT_BG +V3.3S_A_CRT_DAC
4
3
2
1
.
1
R5F14 0.002
R5F2
2 0.002
C5E12 0.1uF 10% SMC0402 . C5E17 0.01uF 10% SMC0402 R5E5 0 NO_STUFF U5E1H 6 +VCCP_GMCH 4,9,24,47,55
2
+V1.05M_DPLLA L5F1
1
+V1.05M_MCH_PLL
10uH 2 + C5U7 220uF 10% . C5E8 0.1uF 10% SMC0402 . +V1.05M_DPLLB
10% 201005-548
B27 A26 1
R5F6
VCCA_CRT_DAC_1 VCCA_CRT_DAC_2 VCCA_DAC_BG VSSA_DAC_BG
D
VTT
L6F1 10uH 1 2 10% 201005-548 + C5F1 220uF 10% .
C5E13 0.1uF 10% SMC0402 .
C5E16 0.01uF 10% SMC0402
R5E6 0 NO_STUFF
+V1.05M_DPLLA
F47
+V1.05M_DPLLB
+V3.3S +V1.8_TXLVDS
+V1.05M_MPLL
VCCA_HPLL VCCA_MPLL VCCA_LVDS VSSA_LVDS
PLL
C5E5 0.1uF 10% SMC0402 .
VCCA_DPLLA VCCA_DPLLB
CRT
2 0.002
+V3.3S_A_DAC_BG
A25 B25
L48
+V1.05M_HPLL
AD1 AE1
+V1.25S_1.05M_CANTIGA . 1 4,11,24,28,47,55,57 R4D6 0.002 +V1.5S R5D13 0 NO_STUFF R6E1 . C4E4 4.7uF 10% SMC0603 . C5E7 1000pF 10% . MC0402 S
J48 J47
A LVDS
+VCCA_PEG_BG
C4E14 1.0uF 20% SMC0402
NO_STUFF
VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25
U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1
1
C4E6 0.47uF SMC0603 C4E9 2.2uF 10% SMC0805 . C4E7 4.7uF 10% SMC0805 . C4E10 4.7uF 10% SMC0805 . C4F2 270uF 20%
R4F5
+V1.05M_AXF
1 2
+V1.05M_HPLL R4E9 . 0
2 0.002
C5E2 0.1uF 10% SMC0402 . +V1.05M_A_SM_R SMR0603 . +V1.05M_A_SM C4R1 22uF 20% SMC0805 C4R2 22uF 20% SMC0805 . C4R3 C4R7 4.7uF 1.0uF 10% 20% SMC0603 SMC0402 . +V1.05M_PEGPLL
AD48
VCCA_PEG_BG
C
C4R3: Edge Cap
A SM
+V1.8_TXLVDS
C4T1 22uF 20% SMC0805 .
7,9 +V1.25S_1.05M_CANTIGA R4R2 0.002 . +V1.05M_A_SM_CK_R R5R3 0 NO_STUFF . SMR0603 +V1.05M_A_SM_CK C5R5 2.2uF 10% SMC0603 C5R6 22uF 20% SMC0805 . C5R9 0.1uF 10% SMC0402 .
9,13,14,46,48,55,57
1
C4E3 7,9 +V1.25S_1.05M_CANTIGA 0.1uF 10% R4R1 SMC0402 . 1 2 0.002 +V1.05M_MPLL . + FB4E1 SMF0603 C4E2 100uF 120ohm@100MHz C4E1 SMC7343 0.1uF R4E1 0.51 10% 1% SMC0402 . +V1.05M_MPLL_RC SMR0402
AA48
C5R7:Cavity Cap NO_STUFF R4R3 0
VCCA_PEG_PLL VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 VCCA_SM_6 VCCA_SM_7 VCCA_SM_8 VCCA_SM_9
NO_STUFF
AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16
POWER
1
2
5
+V3.3S_TVDAC FB4F1 180ohm@100MHz SMF0603
+V3.3S_A_TV_CRT_BG
+V3.3S_A_TV_DAC
1
R4F3
2 0.002
C5E18 0.1uF 10% SMC0402 . C5E14 0.01uF 10% SMC0402 R5E7 0 NO_STUFF +VCC_HDA
+V3.3S_A_TV_DAC
B
NOTE: CAPS USED IN +V3.3S_TVDAC should be within 250mils of edge of MCH
+V1.5S_TVDAC
PEG
R5T10 0 5%
47,55,57
+V1.5S
+V1.5S_TVDAC
1
R4U3
28
+V1.5S_LDO_QDAC
R4U2 0 NO_STUFF
SMC0402
LVDS
C4D3 0.1uF 10% . Topside Cap
AA47
VCCD_PEG_PLL VCCD_LVDS_1 VCCD_LVDS_2
VTTLF
0.002 R4U4
R4U2 to be stuffed & R4U4 to be no_stuffed , if val needs to be done from switcher FB5U1 180ohm@100MHz SMF0603 C5U3 0.1uF 10% SMC0402 .
1
C5T6 0.1uF 10% SMC0402 .
DMI
2 0.002
C5U1 0.1uF 10% SMC0402 .
C5T9 0.01uF 10% SMC0402
+V1.5S_LDO_QDAC_R
C5U2 0.01uF 10% SMC0402
A
+V1.05M_PEGPLL
1
+V1.25S_1.05M_CANTIGA R5T8 . +V1.05M_PEGPLL_R
SMF0805
1
2 0.002
220ohm_at_100MHz +V1.05M_PEGPLL_RC R5T2 C5T8 10uF 20% SMC0805 .
SMR0402
5
w
FB5T1 1.00 1%
w w
+V1.5S_QDAC 46 R5U2 0 NO_STUFF 4,11,24,28,47,55,57 +V1.5S 10% SMC0402 . C5T5 0.1uF
9,13,14,46,48,55,57 +V1.8_LDO
la .
+V1.8
+V1.5S_QDAC
+V1.05M_MCH_PLL2
t p
R5F8
M25
VCCD_TVDAC VCCD_QDAC VCCD_HPLL
D TV/CRT
+V1.05M_PEGPLL
p o
B24 A24 A32 VCC_HDA L28 AF1 M38 L37
CANTIGA_1p2 R5T9 0 5% C5E9 1.0uF 20% SMC0402
SM CK
VCC_TX_LVDS VCC_HV_1 VCC_HV_2 VCC_HV_3 VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5 VCC_DMI_1 VCC_DMI_2 VCC_DMI_3 VCC_DMI_4
K47 C35 B35 A35 V48 U48 V47 U47 U46 AH48 AF48 AH47 AG47
+V3.3S_HV
TV
VCCA_TV_DAC_1 VCCA_TV_DAC_2
C5E4 4.7uF 10% SMC0805 .
C5E3 22uF 20% SMC0805 .
.
AP28 AN28 AP25 AN25 AN24 AM28 AM26 AM25 AL25 AM24 AL24 AM23 AL23
VCCA_SM_CK_1 VCCA_SM_CK_2 VCCA_SM_CK_3 VCCA_SM_CK_4 VCCA_SM_CK_5 VCCA_SM_CK_NCTF_1 VCCA_SM_CK_NCTF_2 VCCA_SM_CK_NCTF_3 VCCA_SM_CK_NCTF_4 VCCA_SM_CK_NCTF_5 VCCA_SM_CK_NCTF_6 VCCA_SM_CK_NCTF_7 VCCA_SM_CK_NCTF_8
HDA
NO_STUFF
-s
A CK
+V1.05S
h c
AXF
VCC_AXF_1 VCC_AXF_2 VCC_AXF_3 VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4
B22 B21 A21
m e
7 C4E5 0.47uF SMC0402 C4E8 0.47uF SMC0402
+V1.8_SM_CK
2
C4D1 10uF 20% SMC0805 .
2
C4D2 0.1uF 10% SMC0402 .
ic t a
R4F2 0
1
2
C4E15 10uF 20% SMC0805
SMR1210
.c s
SMC7343 7,9 +V1.05M_AXF_R
2 0.002
m o
+V1.05S +V1.25S_1.05M_CANTIGA 7,9 +V1.8_GMCH
1
D
1
R4F4 .
2 0.002
+V1.05M_MCH_PLL2
A PEG
L4D1
1
2
1uH 30% SML0805 46
+V1.8_SM_CK_RR
1
R4D1
2 0.002
1
R4D2
+V1.8_SMCK_RC
+V1.8_LDO
C
1% 1.00 SMR0402
R5F3 0.002
+V1.8
1
C5E6 1000pF 10% . MC0402 S C5E15 22uF 20% SMC0805 .
R5E4 0 5% NO_STUFF
L5E1 2 0.10uH 20% SML0805 .
+V_TXLVDS_PM
1
R5F4
2 0.002
BF21 BH20 BG20 BF20
+VCC_PEG R5E3 0
9,15,35,47,55
+V1.05M
1
+ C6E11 220uF 10% SMC7343
2
SMR1210
+V1.05M_PEG_LR 1 .
R6E3
2 0.002
+V1.05S
4,9,24,47,55 NO_STUFF
1
R6E2
HV
2 0.002
B
+VCC_DMI 7 R5E1 +VCC_PEG
1
C5E1 0.1uF 10% SMC0402 .
2 0.002
To use seperate filters for VCC_PEG & VCC_DMI rails No-Stuff R5E1 and stuff L5D1 ,C5C9 & R5D7
9,15,35,47,55 +VCC_DMI
+V1.05M
VTTLF1 VTTLF2 VTTLF3
+VTTLF_CAP1 A8 +VTTLF_CAP2 L1 AB2 +VTTLF_CAP3 C4T8 0.47uF NO_STUFF C4E13 0.47uF SMC0402 C4T9 0.47uF
NO_STUFF + C5C9 220uF 10% SMC7343
L5D1 +V1.05M_DMI_LR 1 91nH 20% SML1210-STD NO_STUFF
R5D7
2 0.002
+V1.8_DLVDS
NO_STUFF
2
1
2 0.002
4,9,24,47,55 R5F5
2
1 0.002 NO_STUFF
1
CR5F1 BAT54 +V1_05S_SD 3 R5U19 10 5%
NO_STUFF
NO_STUFF
Pillar Rock
Title
+V3.3S_HV
Intel Confidential
A
+VCC_HDA R5U1
+V3.3S
CANTIGA (5 OF 6) Size A Date: Document Number 355659 Tuesday, August 28, 2007
2
1
2 0.002
C5E11 0.1uF 10% SMC0402 .
1
R5F1
2
2 0.002
C5E10 0.1uF 10% SMC0402 .
Rev 1.0 Sheet 10
1
of
58
4
3
5
4
3
2
1
U5E1I
U5E1J
D
C
B
A
AU48 AR48 AL48 BB47 AW47 AN47 AJ47 AF47 AD47 AB47 Y47 T47 N47 L47 G47 BD46 BA46 AY46 AV46 AR46 AM46 V46 R46 P46 H46 F46 BF44 AH44 AD44 AA44 Y44 U44 T44 M44 F44 BC43 AV43 AU43 AM43 J43 C43 BG42 AY42 AT42 AN42 AJ42 AE42 N42 L42 BD41 AU41 AM41 AH41 AD41 AA41 Y41 U41 T41 M41 G41 B41 BG40 BB40 AV40 AN40 H40 E40 AT39 AM39 AJ39 AE39 N39 L39 B39 BH38 BC38 BA38 AU38 AH38 AD38 AA38 Y38 U38 T38 J38 F38 C38 BF37 BB37 AW37 AT37 AN37 AJ37 H37 C37 BG36 BD36 AK15 AU36
VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99
CANTIGA_1p2
VSS
5
w
VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198
w w
AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23
BG21 L12 AW21 AU21 AP21 AN21 AH21 AF21 AB21 R21 M21 J21 G21 BC20 BA20 AW20 AT20 AJ20 AG20 Y20 N20 K20 F20 C20 A20 BG19 A18 BG17 BC17 AW17 AT17 R17 M17 H17 C17 BA16 AU16 AN16 N16 K16 G16 E16 BG15 AC15 W15 A15 BG14 AA14 C14 BG13 BC13 BA13 AN13 AJ13 AE13 N13 L13 G13 E13 BF12 AV12 AT12 AM12 AA12 J12 A12 BD11 BB11 AY11 AN11 AH11 Y11 N11 G11 C11 BG10 AV10 AT10 AJ10 AE10 AA10 M10 BF9 BC9 AN9 AM9 AD9 G9 B9 BH8 BB8 AV8 AT8
VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_235 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296
VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325
AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4 BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1 U24 U28 U25 U29 AJ6
VSS
VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355
la .
4
t p
VSS NCTF VSS SCB NC
VSS_SCB_6 NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42 NC_43
A3 E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48 A47
2
p o
VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17 BH48 BH1 A48 C1 VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4
MCH_VSS_351 MCH_VSS_352 MCH_VSS_353 MCH_VSS_354 MCH_VSS_355
-s
.
R4T4 0 R5T12 0 R4T5 0 R5T13 0 R4R13 0
PM_SLP_S3_SHDN2
h c
m e
+V5S C3D2 1.0uF 10%
ic t a
R3R9 10K 5% U3D1 SC1563
.c s
R3R7 17.8K 1% C3D1 22uF C3R1 0.1uF 10% .
m o
+V1.5S
D
4,10,24,28,47,55,57
1
CR3R2 BAT54
C
3
NO_STUFF
V1_5SFOLLOW
5,12,16,17,18,24,28,30,31,32,39,48,49,52,55,56,57
1
5,12,16,17,18,24,28,30,31,32,39,48,49,52,55,56,57 R3R8 10 5% NO_STUFF 10,48,55
+V5S
2
+V3.3S_TVDAC
5 1
IN OUT SHDN GND 2 ADJ 3
4
V3.3S_TVDAC_R2
R3D2 0.01 1%
TVDAC_ADJ2 R3R10 10K 1%
B
3
Q3D1 BSS138
23,40,43,44,46,47,49,55,57 PM_SLP_S3#
1
R3R11 100 5% NO_STUFF
Pillar Rock
Title CANTIGA (6 OF 6) Size A Date:
3
Intel Confidential
A
CANTIGA_1p2
Document Number 355659 Tuesday, August 28, 2007
2
Rev 1.0 Sheet 11
1
of
58
5
Layout Note: Location of all MCH_CFG strap resistors needs to be close to trace to minimize stub
4
3
2
1
5,7,10,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57
+V3.3S
7 MCH_CFG_7 7 MCH_CFG_5 MCH_CFG_7 ME TLS Confidentiality (Isolation Bypass Enable) DMI X2 Select MCH_CFG_5 Low = DMIx2 High = DMIx4 (default) R1T11 2.21K 1% NO_STUFF Low = AMT Firmware will use TLS cipher suite with no confidentiality (Isolators are bypassed] High = AMT Firmware will use TLS cipher suite with Confidentiality {Isolators are active (Default)} R1T9 2.21K 1% NO_STUFF
Digital Display Port (SDVO/DP/iHDMI) Concurrent with PCIe MCH_CFG_20 Low = Only Digital Display Port (SDVO/DP/iHDMI) or PCIE or is operational (Default) High = Digital Display Port (SDVO/DP/iHDMI) and PCIE are operating simultaneously via PEG port R5P7 4.02K 1% NO_STUFF
D
7,19 MCH_CFG_20
GMCH Fan Power Control
7 MCH_CFG_16 FSB Dynamic ODT MCH_CFG_16 Low = Dynamic ODT Disabled High = Dynamic ODT Enabled (default) R1E1 2.21K 1% NO_STUFF C3P4 0.1uF 10% . C3C13 4.7uF 10% . 5,11,16,17,18,24,28,30,31,32,39,48,49,52,55,56,57 +V5S
5,7,10,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57
EU4C1 _
8
40,43 MCH_PWM_FAN R4P2 15K 1% . OPA567_POSIN_R
9
V+ TF EN OUT OPA567 + IS IF HS V-
2 3
4 5 13 6 7
C
7 MCH_CFG_9 7 MCH_CFG_6 R1T7 2.21K 1% .
C4C19 1uF 10% .
.
stuff J1C3 to enable ITPM
3 2 1
PCI Express Graphics Lane MCH_CFG_9 Low = Reverse Lane (default) High = Normal operation
R1U4 2.21K 1% .
1
MCH_CFG_6_R J1C3
,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57
+V3.3S
MCH_CFG_6 (iTPM Host Interface) Low = iTPM Host Interface is enabled High = iTPM Host Interface is Disabled (default)
DMI Lane Reversal MCH_CFG_19 Low = Normal (default) High = Lanes Reversed R5F11 4.02K 1% NO_STUFF
B
7 MCH_CFG_19
5,7,10,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 5,7,10,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S
3
7 MCH_CFG_10 7 MCH_CFG_12 7 MCH_CFG_13
A
5
w w
R1T12 2.21K 1% NO_STUFF R1T15 2.21K 1% NO_STUFF
. w
Q3C3
2
Place in IMVP_6 Hot Spot
R1T17 2.21K 1% NO_STUFF
Design Note: Only one of the CFG10/CFG12/CFG13 straps can be enabled at any time
p la
7481_D1P_Q
1 2N3904
7481_D1N_Q
to
R3B16 0 . C3N9 1000pF 10% R3B18 0 .
NO_STUFF
-s p
R3B20 10K 1% C3B7 0.1uF 20% U3B2 7481_D1P 7481_D1N
h c
R4P1 20K 5%
OPA567_NEGIN_R
m e
MCH_TACHO_OP_FAN
3
CR3P1 BAT54
1
a
3 2 1
ic t
J3C2
1 12
10 11
.c s
+V3.3S R3P3 1K 1% . R3P4 0 .
m o
MCH_TACHO_FAN 40,43
D
MCH_TACHO_R_FAN
C
OPA567_ISIN_MCH_R
R3P2 1.74K 1%
CONN3_HDR
R4C25 3.32K 1%
2
IMVP6 & Amb Thermal sensors
B
R3B21 10K 1% NO_STUFF
+V3.3S
1 2 3 4 5
VDD SCLK D1+ SDATA D1ALRT#/THM2# THM# D2+ GND D2-
10 9 8 7 6
SMB_THRM_CLK 5,40,43 SMB_THRM_DATA 5,40,43 7481_D2P C3N8 1000pF 10% 7481_D2N 7481_D2P_Q R3B15 0
7481_THRM2#
R3N24 0 NO_STUFF
3 1
Q3B1 2N3904
ADT7481ARMZ-1 TEMP MON
. R3B17 7481_D2N_Q 0 .
2
Spare sensor, For Amb. temp sensor
PM_THRM# 5,23,40,43
Place ADT7481 near Air inlet not under SODIMM
7481_THRM#
R3N23 0 NO_STUFF
XOR / ALLZ / Clock Un-gating MCH_CFG_13 MCH_CFG_12 Configuration 0 0 Reserved 1 0 XOR Mode Enabled 0 1 All-Z Mode Enabled 1 1 Normal Operation (Default) MCH_CFG_10 (PCIE Loopback enable) Low = Enabled High = Disabled (Default)
Pillar Rock
Title CANTIGA STRAPPING Size A Date: Document Number 355659 Tuesday, August 28, 2007
2
Intel Confidential
A
Rev 1.0 Sheet 12
1
of
58
4
3
5
4
3
2
1
D
8,15 M_A_A[14:0]
J5P1A M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14
8,15
M_A_BS2
102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 107 106 110 115 30 32 164 166 79 80 113 108 109 198 200 197 195 114 119
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16_BA2 BA0 BA1 S0# S1# CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# WE# SA0 SA1 SCL SDA ODT0 ODT1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7
C
7 7 7 7 7,15 7,15 8,15 8,15 8,15
8,15 M_A_BS0 8,15 M_A_BS1 7,15 M_CS#0 7,15 M_CS#1 M_CLK_DDR0 M_CLK_DDR#0 M_CLK_DDR1 M_CLK_DDR#1 M_CKE0 M_CKE1 M_A_CAS# M_A_RAS# M_A_WE#
SA0_DIM0 SA1_DIM0
Note: SO-DIMM0 SPD Address is 0xA0 SO-DIMM0 TS Address is 0x30
14,15,23 SMB_CLK_M2 14,15,23 SMB_DATA_M2 R3C5 10K 5% . R3C6 10K 5% . 7,15 M_ODT0 7,15 M_ODT1 8 M_A_DM[7:0]
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
10 26 52 67 130 147 170 185 13 31 51 70 131 148 169 188 11 29 49 68 129 146 167 186
8 M_A_DQS[7:0]
B
8 M_A_DQS#[7:0]
A
5
w
w w
la .
4
to p
CON200_DDR2-SODIMM-STAN DQ0 5 DQ1 7 DQ2 17 DQ3 19 DQ4 4 DQ5 6 DQ6 14 DQ7 16 DQ8 23 DQ9 25 DQ10 35 DQ11 37 DQ12 20 DQ13 22 DQ14 36 DQ15 38 DQ16 43 DQ17 45 DQ18 55 DQ19 57 DQ20 44 DQ21 46 DQ22 56 DQ23 58 DQ24 61 DQ25 63 DQ26 73 DQ27 75 DQ28 62 DQ29 64 DQ30 74 DQ31 76 DQ32 123 DQ33 125 DQ34 135 DQ35 137 DQ36 124 DQ37 126 DQ38 134 DQ39 136 DQ40 141 DQ41 143 DQ42 151 DQ43 153 DQ44 140 DQ45 142 DQ46 152 DQ47 154 DQ48 157 DQ49 159 DQ50 173 DQ51 175 DQ52 158 DQ53 160 DQ54 174 DQ55 176 DQ56 179 DQ57 181 DQ58 189 DQ59 191 DQ60 180 DQ61 182 DQ62 192 DQ63 194
M_A_DQ[63:0] M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
8
14,15,23,35,55,57
To connect TS on DIMM0&1 o/p to H8, stuff R5P3 and no-stuff R5P1
-s p
h c
+V3.3S +V1.8 R5C3
7,14 TS#_DIMM0_1
15,40 PM_EXTTS#0_DIMM0_1
m e
+V3.3M R4C1 0.022 R5P1 10K 48 M_VREF_DIMM0 +V1.8_DIMM0 C4C8 0.1uF 10% . C4C9 0.1uF 10% . 0.002 1% C5C1 330uF 20% 2.5V
ic t a
+V3.3M_DIMM0 C3C7 0.1uF 10% . C4C7 2.2uF 10% . NO_STUFF C6P2 0.1uF 10% . R5P3 0 C6P1 2.2uF 10% . C5C5 0.1uF 10% .
.c s
112 111 117 96 95 118 81 82 87 103 88 104 199 83 120 50 69 163 1 201 202 47 133 183 77 12 48 184 78 71 72 121 122 196 193 8 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDDSPD NC1 NC2 EVENT# NC4 NCTEST VREF GND0 GND1 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15
m o
VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162
D
+V1.8_DIMM0 J5P1B CON200_DDR2-SODIMM-STAN
C
C4C10 0.1uF 10% .
Layout Note: Place these Caps near SO-DIMM0.
B
Layout Note: Place these Caps near SO-DIMM0. 9,10,14,46,48,55,57 +V1.8_DIMM0
C4C13 2.2uF 10% .
C5C3 2.2uF 10% .
C4C12 2.2uF 10% .
C5C4 2.2uF 10% .
C4C11 2.2uF 10% .
Pillar Rock
Title DDR2 SODIMM 0 Size A Date:
3
Intel Confidential
A
Document Number 355659 Tuesday, August 28, 2007
2
Rev 1.0 Sheet 13
1
of
58
5
4
3
2
1
D
8,15 M_B_A[14:0]
J5N1A M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14
8,15
M_B_BS2
102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 107 106 110 115 30 32 164 166 79 80 113 108 109 198 200 197 195 114 119
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16_BA2 BA0 BA1 S0# S1# CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# WE# SA0 SA1 SCL SDA ODT0 ODT1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7
C
13,15,23,35,55,57 +V3.3M
7 7 7 7 7,15 7,15 8,15 8,15 8,15 R3B23 10K 5%
8,15 M_B_BS0 8,15 M_B_BS1 7,15 M_CS#2 7,15 M_CS#3 M_CLK_DDR3 M_CLK_DDR#3 M_CLK_DDR4 M_CLK_DDR#4 M_CKE3 M_CKE4 M_B_CAS# M_B_RAS# M_B_WE#
SA0_DIM1 SA1_DIM1
Note: SO-DIMM1 SPD Address is 0xA4 SO-DIMM1 TS Address is 0x34
.
13,15,23 SMB_CLK_M2 13,15,23 SMB_DATA_M2 7,15 M_ODT2 7,15 M_ODT3 8 M_B_DM[7:0] R4B24 10K 5% .
M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7
10 26 52 67 130 147 170 185 13 31 51 70 131 148 169 188 11 29 49 68 129 146 167 186
8 M_B_DQS[7:0]
8 M_B_DQS#[7:0]
B
A
5
w
w w
la .
4
to p
CON200_DDR2-SODIMM-REV DQ0 5 DQ1 7 DQ2 17 DQ3 19 DQ4 4 DQ5 6 DQ6 14 DQ7 16 DQ8 23 DQ9 25 DQ10 35 DQ11 37 DQ12 20 DQ13 22 DQ14 36 DQ15 38 DQ16 43 DQ17 45 DQ18 55 DQ19 57 DQ20 44 DQ21 46 DQ22 56 DQ23 58 DQ24 61 DQ25 63 DQ26 73 DQ27 75 DQ28 62 DQ29 64 DQ30 74 DQ31 76 DQ32 123 DQ33 125 DQ34 135 DQ35 137 DQ36 124 DQ37 126 DQ38 134 DQ39 136 DQ40 141 DQ41 143 DQ42 151 DQ43 153 DQ44 140 DQ45 142 DQ46 152 DQ47 154 DQ48 157 DQ49 159 DQ50 173 DQ51 175 DQ52 158 DQ53 160 DQ54 174 DQ55 176 DQ56 179 DQ57 181 DQ58 189 DQ59 191 DQ60 180 DQ61 182 DQ62 192 DQ63 194
M_B_DQ[63:0] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
8
-s p
h c
+V1.8_DIMM1 C4B22 0.1uF 10% . C4B20 0.1uF 10% . +V1.8_DIMM1 C5B4 2.2uF 10% . C4B21 2.2uF 10% .
m e
C4B19 0.1uF 10% . C4B23 0.1uF 10% . C4B18 2.2uF 10% . C5B6 2.2uF 10% . C4B17 2.2uF 10% .
13,15,23,35,55,57
ic t a
+V3.3M R4