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Schematics/Layouts (V13)
System Block Diagram
NSE5
1880 .. 1880 1805 .. GSM/PCN Diplex MHZ 1805
MHZ
187 MHz
71 MHz
13 MHz
RXINP/ RXINN
RX ADC 12bit
I+ modulato Q
r 541.6 kS/S 8kS/S
DLR3 Supply (MCUGENIO0) AUDIO
UI
Earpiece
58 MHz 116 MHz GSM Duplex f/ 2 232 MHz f f f/4 Summa, Crfu3 Summa Charge. Vref Vcp Vxo Vsyn_1 Vrx_1 Vsyn_2 Vrx_2 Vtx TXIP/ TXIN SYNTH ENA1 CLK DATA TXQP/ TXQN TXC RXC
RX AUDIO DAC 13bit
Headset
SUMMA
116 MHz GSM
Vctcxo Crfu3, lo_buff Rx, Tx, Synth. Crfu3, Rx Summa, VCO's Summa, Rx Crfu3, Summa, Tx
960 935 PCN Rx/Tx ..
CRFU3
MHZ Band Select 2067 .. 1992 f f/2 1031 .. MHZ 464 MHz VHF VCO UHF VCO 2067 MHz 1942 ..
TxC/AGC DAC10bit
XEar SGnd
PCN Tx
mic bias
8kS/S
f f/2 Rx + GSM Tx 16/17
f f/2
slide MIC
XMIC
EXT. RF
Vtx Diplexer
TX AUDIO ADC 13bit
Couplers 915 890 .. MHZ
232 MHz PCN
1006
MHZ
2017 1942 ..
MHZ
PLL LOGIC
64/65
TXI DAC 8bit TXQ DAC 8bit AFC DAC 11bit
Headset
1.083kS/S
1.083kS/S
COBBA _GJP
st 64 BGA
KEYBOARD PDATA register
Buzzer
Det BIAS PA GSM
116 MHz
AFC
1 kS/S
2
Keyb. lights slide position
232 MHz
13MHz
Vcobba VCTCXO RFCLK Vbb COBBACLK 13MHz COBBA RESET
3 SERIEL RF/CTR IF SERIAL AUDIO IF
PCM(3:0) LCDRSTX IRON HOOKDET, HEADDET
roller input KEYB.
BIAS
DET_FB
PA PCN
1785 MHZ 1710 ..
IMEI register
SERRFI(3:0)
BAND_SEL
FrACtrl
Vpp ctr. ROM (FLASH) 2M*16 SRAM 512k*8
RAMSELX MCUDA (15:8) ROM1SELX MCUAD (21:0) MCUWRX MCURDX MCUGENIO3 DSP GEN Out4
NC
NC
NC
TXP VCXOPWR BUZZER
Display/Driver Temp.sense (LCD)
DSP GEN Out2
RX Pwr
TX Pwr
Synth Pwr
DSP GEN Out5
DSP GEN Out3
SCU MCUIf
boot rom
CTSI
PUP
MBUS VIBRA
MCUDA (7:0)
BUSC
API RAM 2kx16
CS CELLULAR SYSTEM
ACC IF Tone Generator Sidetone
FBUS Rx/Tx ROW(5:0), Col(4:0), LCDCS, ROLLER_A, ROLLER_B, ROLLER_C
DSP
PCMSIO LCD driver IF COBBA IF RX RAM TXC RAM TXC Ramp GMSK modulator TXIQ RAM MFI FSM MFI UIF Keyb. IF CCONT IF
SYSTEM CONNECTOR INTERN VIBRA IRMODULE TFDU4100
UI USER INTERFACE
RSS Measurement and AGC RX Filtering ROM 68kx16 RAM 10kx16
8kHz
SNR Calculation and AFC Phase Demodu lation Matched Filter Channel Estimation Symbol Sync. BFI CRC DTX Convol. Encoding Convol. Decoding Inter leaving Deinter leaving Bit Detection De cryption
GENSCLK GENSDIO SIMCard CLK
CCONT
st 64 BGA SIM IF SIO Mux/ ADC
RSSI EAD BTEMP BSI VBAT ICHAR VCHAR VCXOT LCD Temp.
5
MCU
DDI DATA DEVICE INTERFACE
SIM CARD READER BATTERY
VIBRA BTEMP BSI
CCONTCSX
SIM IF
RF Vref BB
DEV DEVICE CONTROL
DSP DSP CONTROL
RX DTX Speech Decoding Speech Encoding VAD
Voltage Regulators
VSIM 3/5 Vref V2V Vcp Vbb V5V VBB VR1 VR1_SW VR2 Ram_ bck Vsyn_2 VR3 VR4 Vcobba VR5 VR6 Vtx VR7 SLEEPCLK, PURX, CCONTINT
HW HW DRIVERS
LOC LOCALS CONTROL 8kHz
HF AEC Transmit Control
Offset Counter & Comparator FrACtrl TXP
SYSTEM LOGIC
Vxo Vsyn_1 Vrx_1
CHAPS SO16
CHARG CHARGER CONTROL
LN LOCAL NETWORK
OS OPERATING SYSTEM
CharLim
Transmitburst every 4.615 ms
Burst Build
En cryption DSP IO DSP IF Coder
wd
RTC PWM
JTAG
JTAG
Vrx_2
PWM
MAD2PR1
ti 144 BGA
TEST IF
Vbb
OSC 32 kHz
HD945
Draft
Block Diagram
backup battery
v. 2.1+ 13 Aug 98
Draft 05
Page A 1
Schematics/Layouts (V13)
RF and BB Interconnections
NSE5
Draft 05
Page A 2
Schematics/Layouts (V13)
Baseband Block
NSE5
Draft 05
Page A 3
Schematics/Layouts (V13)
Audio
NSE5
Draft 05
Page A 4
Schematics/Layouts (V13)
CPU
NSE5
Draft 05
Page A 5
Schematics/Layouts (V13)
Infrared Module
NSE5
Draft 05
Page A 6
Schematics/Layouts (V13)
Power
NSE5
Draft 05
Page A 7
Schematics/Layouts (V13)
User Interface
NSE5
S end
E nd
1
2
3
S left oft
0
5
S right oft
##
4
8
*
6
7
9
Draft 05
Page A 8
Schematics/Layouts (V13)
CRFU3
NSE5
Draft 05
Page A 9
Schematics/Layouts (V13)
PA
NSE5
Draft 05
Page A 10
Schematics/Layouts (V13)
SUMMA
NSE5
Draft 05
Page A 11
Schematics/Layouts (V13)
Component Layout Top
NSE5
Draft 05
Page A 12
Schematics/Layouts (V13)
Component Layout Bottom
NSE5
Draft 05
Page A 13