Text preview for : BDAL_Alex_A3_C_L3_V1.1.pdf part of Motorola StarTac Star Tac mobile phone Service Manual
Back to : StarTac.rar | Home
GSM DualSlot StarTAC Audio Logic Block Diagram
to U501, 42 217 Hz 38 83 DUAL_CS 85 12 6 121 14 DP_EN RAM2CS U702 Eprom J101, 21 U704 SRam U704 SRam U702
LOGIC BOARD SIGNALS
SRAM U704 EEPROM U705 FLASH 26 U702 16
42 43 RAM2_CS RAM1_CS RX_EN
SIM Interface 1 7 14 15 J601 6 SIM Interface 2 U915 J900 1 - 10 SIM_VCC 1 U902 SIM_VCC 2
5 7
Measured in standby mode
2.8mVpp 10ms / cm From the CPU (U701). When high, Rx path enabled and low muted. 1. Enables the Rf switch (U400) for receive mode. 2. Biases the mixer Q420, and low noise amp (Q418). From CPU (U701), but inverted by Q501. High when 1. Enable the Rf switch for transmit mode & also the GIFSYN for transmit mode. 2. Supply Voltage for the PAC IC. 3. Isolates RF, by switching the PA Bias Circuitry ( Not shown). Controlled at power up by GCAP (U900) & CPU (U701). 1. Connected to CPU (U701), BIC (U703), Modem (U501) & Speech coder (U801). After power up sequence, any chip can hold RESET low to power phone off if there is a problem.
13_DCLK_B
from U201, 59
+ 2.75V
RESET
SPI DATA BUS
RX_ACQ to U501 DM_CS TX_KEY MDM_RD MDM_WR
20
37
17
48
35
TX_EN
7Vpp 10ms / cm
to U201, 97
RF_START RESET RX_EN
U701 CALL PROCESSOR
RAM1CS ROM1CS
DATA BUS ADDRESSS BUS
32 31 34 33 38 40 from J601, 11 39
1, 3, 97 41 120
U703 BIC
A/D
46
DATA BUS
ROM1_CS DUAL_CS
RESET
power on
2,8Vrms 200ms / cm
DUAL_CS
2.8Vpp 100ns / cm
From CPU (U701) to Eprom. 1. Chip Enable controlling read/write access to and from Eprom (U702).
ADDRESSS BUS D/A
64 58 1 U701, 16 BATT_SENSE DAC_OUT RAM2_CS
2.8Vpp 100ns / cm From CPU (U701) to SRAM. 1. Chip Enable controlling read/write access to and from 2nd half of SRAM (U704).
RAM1_CS
2.8Vpp 100ns / cm
From CPU (U701) to SRAM. 1. Chip Enable controlling read/write access to and from 1st half of SRAM (U704).
Y701
32.768 kHz 94 95 92 SC_INT 5 48 16 SCI_RX
UPLINK (non-voiced data)
DOWNLINK (non-voiced data)
46
49
37, 108-114
+ 2,75V BATT_FDBK
6
AD_THERM BATT_GND BATT+
11
DATA
ROM1_CS
2.8Vpp 100ns / cm
From CPU (U701) to Eprom. 1. Chip Enable controlling read/write access to and from Eprom (U702).
ADDRESSS BUS
DATA BUS
MF_INT BIC_INT
DP_EN
start up or press key
2.8Vpp 100ns / cm
From CPU (U701) to display, via connector J101. 1. Processor selects to enable display. When high, the display is enabled and low disabled.
CR605
DOWNLINK_AUD
TX_EN
C
E
Q501
B
+ 2,75V
J600
UPLINK_AUD
14
EXT_B+
12
11
4 Q601 Q602
1-5
12-16
EARPIECE (Only available with a complete flip assembly)
R2.75V
J601
SC_INT
start up or press key 2.8Vpp 2ns / cm
Speech Coder Interface. This is a signal from uP (U701) to Speech Coder (U801). 1) This is a 20ms timing signal from U701 which times the decoding and encoding function of the Speech Coder U801. From CPU (U701) to Clock Doubler U805. 1) This signal enables the Clock Doubler U805 which doubles the 13MHz clock to 26MHz to time the Speech Coder. When high U805 is enabled and low disabled. From BIC to uP. This signal periodically interrupts the uP at 217Hz. During Power Saving mode this signal is set to DC. From BIC to uP. This signal interrupts the uP for a number of reasons. 1. Keypad detection 2. Power Sense 3. SIM Functions 4. DSC Bus Status Indicators From butt plug (J600) to BIC chip (J600).. This is a comms link from an external peripherale and the phone, and could be either data information or speech information. It is also used to sense the presence of a DHFA and the ignition status of the DHFA with DC levels
Doubler_EN
power on
2.8vpp 100ms / cm
7, 19, 26, 50, 56 66, 75, 85, 100
Encoded Voice Data
U801 SPEECH CODER
78 83
R602
15
MF_INT
2.8Vpp 1ms / cm
CODEC
13 8 3
CHARGER
17 47 MIC 1 2
16 18 19 1 10
U803
A/D D/A VAG
ISENSE
-
BIC_INT
press a key
9
2.8Vpp 50us / cm
J802
J601
8 7
ALERT
UPLINK
2.8Vpp 10us / cm
4
21
+ -1
RX / TX SIGNAL PROCESSING
DOUBLER_EN
+
20 19 5
DOWNLINK
5Vpp 10us / cm
6 5 MUX 3
From BIC chip (U703) to butt plug (J600).This is a comms link from an external peripherale and the phone, . and could be either data information or speech information. It is also used to sense the presence of a DHFA and the ignition status of the DHFA with DC levels From GIF Syn to BIC IC - 13MHz clock.. This is the master clock reference required for the radio
+
B+
VSWITCH V3
28 22
CLK_13_IN
1.6Vpp 50ns / cm
U804 3 5
R+2.75V L+2.75V T902 VSWITCH 3.85V L500 R475 RESET RX SIGNAL PATH TX SIGNAL PATH MAIN VCO SIGNAL PATH TUNING VOLTAGES REFERENCE CLOCK Orderable Part Non - Orderable Part
AUDIO IN
test mode 08#, 10#, 36# 434#, 477# 2.7Vpp 5us / cm
SC_INT
45
512 KHz 81 8 KHz 33 FS_AUD CLK_AUD
MULTIPLEXER U802
25, 43
DC - DC V2
Measured in test mode
External audio from butt plug, directly to Speech Coder IC
37 3
4
DOUBLER U805 X2 Multiplexer 6 26 MHz 37
U900
32, 41 30
2 13_DCLK_B
GCAP
test mode
AUDIO OUT 08#, 10#, 36#
434#, 477#
2.8Vpp 5us / cm
External audio from Speech Coder via GCAP to butt plug
CLK_AUD
2.8Vpp 5us / cm
This signal is from the BIC to the Speech Coder It is a timing signal and runs at 512KHz, and times the transfer of speech information on the DSC Bus between BIC and Speech Coder.
FS_AUD
2.8Vpp 5us / cm
This signal is from the BIC to the Speech Coder IC. It is a timing signal at 8KHz and provides for frame synchronisation during speech transfer on the DSC bus.
A/L LAYER - ORDERABLE SPARES
Part Designator A2 / A3 AL800 CR605 J101 J600 J601 J802 J900 MIC Q501 Q601 Q602 R602 T902 Part Description Ground clips Ant. tube Alert Diode / Charger 32 Pin Display Connector 15 Pin Extern Connector Flip Flexprint Connector Microphone Connector SIM Connector 2 Microphone Transitor TX_EN Power Transistor Charger Transistor Batt Feedback Resistor / Charger Sensing Choke / Vswitch Part Number 4209480E01 5009473S01 4809653F03 2809454C02 0909449B04 0909201T01 0909195E01 4009169E01 5009536H15 4809607E05 4809579E17 4809939C04 0680195M64 2509306J01 Part Designator U703 U704 U801 U802 U803 U804 U805 U900 Y701 U702 S1 - S3 SH25 - 27 A1 Part Description IC BIC IC SRAM IC Speech Coder IC Multiplexer Codec IC IC Buffer IC Frquency Doubler IC GCAP XTAL 32.768KHZ Flash Prom With Bootcode Volume / Mute Switch Ground Clips Antenna Clip Part Number 5109962C11 5109688L09 5199305A01 5109632D44 5109920D19 5109522E10 5109781E47 5109632D69 4809995L05 5102486T01 4009060E01 4209189E01 4209233D01
TEST COMMANDS
# press 2 sec. 01 # 07 # 08 # 09 # 10 # 11 # 12 # 19 # 20 # 22 # 25 # 26xxxx # 31x # 33xxx # 36 # 37 # 45xxx # 46 # 47x # 58 / xxxxxx # Enter Manual Test Mode Exit Manual Test Mode Mute Rx Audio Path Unmute Rx Audio Path Mute Tx Audio Path Unmute Tx Audio Path Program Main Local Osc. to Channelbb Set Tx Power level to fixed valure Display SW Version Number of Call Processor Display SW Version Number of Modem Display SW Version Number of Speech Coder Set Continuous AGC Set Continuous AFC Initiate Pseudo-Random Sequence with Midamble Synchronize to BCH Carrier Initiate Acoustic Loopback Stop Test Serving Cell Power Level Display Current Valure od AFC DAC Set Audio Volume Display / Modify Security Code Display / Modify Lock Code Display IMEI
REVISIONS
Europe Middle East & Africa Customer Services LEVEL 3 COLOUR DIAGRAMS GSM Dual Slot Startac Colin Jack, Michael Hansen, Ray Collins, Ralf Lorenzen Page 1 of 2 21.04.99 Rev. 1.1
= Differences Startac 100 to Dual band Startac
59 / xxx # 60 #
Motorola Confidential Proprietary
GSM Dual Slot StarTAC RF BLOCK DIAGRAM
R275V DM_CS B+ 902,4 MHz 14 (- 4 dB) RF ATTN 902,4 MHz R393 TX VCO C Q300 (+15dB) 12-15 EXITER RX 2.75 Supplies 13 MHz oscillator PLL dividers & U501 DAC references PLL_VCC Q203 4 MAIN _VCO (794,4 CH 062) RF ATTN (-8dB) R221 S G Q202 B+ S G V2_OUT 19 REG_SPLY 17 MAIN_VCC 25 VI_DRIVE 13 V2_DRIVE 18 OFST_CP 10 LIM_OUT 4 CR 203 TX OFFSET LOCAL OSCILLATOR 216 MHz to U310, 8
Supplies limitor amps 2nd LO, IF circuts& references
RF BOARD SIGNALS
CH. 001 = 1.50 Vdc CH. 062 = 1.74 Vdc CH. 124 = 1.87 Vdc 7 9,10 2 ,12 1
Tx SIGNALS - 110062#, 1215#, 310#
Frequency 217Hz - 1ms/cm
SAT_DET
3Vpp
ANT
U301 IPA
(+15dB) 7 C Q303 B
U300 / TIC
8 CHARGE PUMP PHASE DET.
CR390
DM_CS R475 R275
B CR300
Signal from PAC to Speech Coder. When PA is at or near saturation signal is low, telling Speech Coder to reduce AOC drive When the PA is not near saturation this is high, telling Speech Coder to increase AOC drive. Signal from the Speech Coder to the PAC When this signal is low, the internal gain in the PAC is unity. When this signal is high, the internal gain in the PAC is 1. From uP to PAC. This is a timing signal to the PAC to provide the current path for the initial loop precharge Signal from SMOC to PAC. This is a linear control voltage for ramp up and ramp down of the PA output level. This controls the voltage on the exciter control output (EXC) from the PAC. Signal from uP but inverted via Q500 and used to time:4. PAC 1. GIF SYN 5. RF Switch 2. TIC Enables Tx Path when high 3. Tx VCO Signal from uP inverted via Q504. Enables TIC, PA and TX VCO. When high, this enables Tx path. From Speech Coder IC to GIF SYN This signal is the in-phase input to the I-Q Modulator of the GIF SYN.
DET_SW
Power Step: 04-11 - 50mVpp 12-15 - 900mVpp
D 5 1 6 3 8 RF_IN 2
RX SIGNAL PATH TX SIGNAL PATH MAIN VCO SIGNAL PATH TUNING VOLTAGES REFERENCE CLOCK Orderable Part Non - Orderable Part
DET_SW 66
TX_KEY
2,75Vpp
U400
4 7
D
AOC
Power Step: 04 - 520mVpp 15 - 280mVpp
108 MHz from U310, 12 to U310, 11
U310
DET
14 12 SAT_DET 11 10 8 TX_EN from U701 pin 5, & inverted by Q501
TX_EN
3Vpp
Q443
Q442
60
AOC_OUT 33
SAT_DET 67
SW_RF from J400 pin 16
DM_CS 13_DCLK_B 42 from U703, 37 TXI
2,8Vpp
2.1Vpp
DET_SW
TX_KEY
TX_EN RX_EN from U701 from U701 pin 21 pin 5, & inverted by Q501
SUPER FILTER
OFST_E 6 OFST_B 7
Osc. discrete circuty
73
RESET U310, 10
TXQ
2.1Vpp
From Speech Coder IC to GIF SYN This signal is the quadrature input to the I-Q Modulator of the GIF SYN.
Vref from U900, 11 AOC_DRIVE SUPER FILTER VOLTAGE
16 21 SF_OUT 26 PRSC_IN CH. 001 = 2,02 Vdc CH. 062 = 2,55 Vdc CH. 124 = 1.81 Vdc TXQ_P TXI_P 21 69 24
TXQ 61 TXI 63
TX_KEY from U701, 6 MDM_RD DM_CS 9
Modem Callprocessor Interface
2,8Vpp 500us/cm
MAIN VCO
782 - 807 MHz -24dBm CR 250 LOOP FILTER
From uP to SSpeech Coder. This signal indicates when the uP is reading data from the Speech Coder. High when enabled.
Q250
23 MAIN_CP
RF_SCK SPI_CLK 53 RF_SPI SPI_DATA 52 RF_START 51 78 77
FL 451
(- 3.5dBm)
794,4 MHz (CH 062) Q251 Q252
MODEM U501
MDM_WR RX_ACQ 17
2,8Vpp 500us/cm
From uP to Speech Coder. This signal indicates when the uP is writing data to the Speech Coder. High when enabled.
CR 431 43 LO2_CP RX LOCAL OSCILLATOR 41 LO2_BASE 306MHz 42 LO2_EMITTER
GIF_SYN U201
2, 5,10,18 25, 41, 44, 45, 53, 64, 70 B+ 75 R475V 15 14 16 CR 201 Y201 29 AFC 76
Rx SIGNALS - In Standby Mode
R275V RX_ACQ MDM_RD MDM_WR
2,8Vpp 500us/cm
17 11, 22, 44 RXI 46 RXQ 48 IQ_REF 47 59 CLK_OUT
From uP to Speech Coder This is an interrupt from the uP to the Speech Coder. When high this indicates to the Speech Coder the beginning of the receive burst. From uP to GIF SYN Signal to drive the GIFSYN IC. This is a pulsed signal which controls the sending of SPI data to the GIFSYN for all RF functions.-
FL453
(- 3,5dB)
Osc. discrete circuty
(+10dB)
RF_START
2,8Vpp 20us/cm
Rx SIGNALS - 11062#, 262000#, 25013#, 241#
Frequency 217Hz - 1ms/cm
RXI
1.8Vpp 500us/cm
(+13 dB) (- 3.5dB) B 947,4 MHz (CH 62) Q418 E C FL452
(- 6dB) 33 SW_VCC 31 PRE_IN B C Q420 FL420 153 MHz
XTAL_BASE 57
From GIF Syn to Speech Coder IC. This is a baseband analogue signal to A/D convertors of Speech Coder From GIF Syn to Speech Coder IC. This is a baseband analogue signal to A/D convertors of Speech Coder From Speech Coder to GIF Syn. This is a DC level from Speech coder for the RXI and Q signals to ride on.
RXQ
1.8Vpp 500us/cm
RX_EN
RX 2.75V
RX_EN (+7dB) Q421 153 MHz
SPI DATA BUS
13 MHz CLOCK
to U701
IQ_REF
1.38Vrms 500us/cm
U703,17
TEST COMMANDS
# press 2 sec. 01 # 07 # 08 # Enter Manual Test Mode Exit Manual Test Mode Mute Rx Audio Path Unmute Rx Audio Path Mute Tx Audio Path Unmute Tx Audio Path Program Main Local Osc. to Channelbb Set Tx Power level to fixed valure Display SW Version Number of Call Processor Display SW Version Number of Modem Display SW Version Number of Speech Coder Set Continuous AGC Set Continuous AFC Initiate Pseudo-Random Sequence with Midamble Synchronize to BCH Carrier Initiate Acoustic Loopback Stop Test Serving Cell Power Level Display Current Valure od AFC DAC Set Audio Volume Display / Modify Security Code Display / Modify Lock Code Display IMEI Display Error Code
RF LAYER - ORDERABLE SPARES
Part Designator
CR201 CR203 CR250 CR300 CR390 CR431 CR908 FL420 FL451 FL452 Q202 Q203 Q300 Q303 FL453
09 # 10 # 11 #
Part Description
Master Xtal Varactor TX Local VCO Varactor Main VCO Varactor TX VCO Varactor Transmit Diode RX Local VCO Varactor Signal Indicator LED IF SAW Filter 1st RX Filter 2nd RX Filter VCO Filter RX Power Transistor Tx VCO Transistor Tx Exciter Transistor GifSyn Power Transistor
Part Part Number Designator
4809641F04 4809641F03 4809642F02 4809641F02 4809948D06 4809641F03 4809118D01 9109449C01 9109450C01 9109450C01 9109451C01 4809579E18 4813827A02 4813827A02 9109451C01 Q442 Q443 Shield Shield Shield Shield Shield Shield SH60 - 63 U201 U300 U301 U301 U301 U310
Part Description
RF Switch Control RF Switch Control Can - Antenna Switch Can - Main VCO Can - Tx VCO Can - GIFSYN Can - PA Can - Modem Clips GIFSYN TIC PA / Motorola PA / Alpha PA / Siemans PAC
Part Number
4809939C08 4809939C08 2609225D01 2609226D01 2609277D01 2609228D01 2609229D01 2609230D01 4209388S01 5109632D92 5109632D94 5109908K07 5109908K27 5109908K30 5109632D08
12 # 19 # 20 # 22 # 25 # 26xxxx # 31x # 33xxx # 36 # 37 # 45xxx # 46 # 47x # 58 / xxxxxx # 59 / xxx # 60 # 7100 #
FREQUENCIES
CHANNEL 1-Low 62-Middle 124-High Tx 890.2 902.4 914.8 Rx 935.2 947.4 959.8 MAIN VCO 782.2 794.4 806.8 Rx I.F 153 153 153 Rx I.F L.O 306 306 306 Tx I.F 108 108 108 Tx I.F L.O 216 216 216
REVISIONS
Europe Middle East & Africa Customer Services LEVEL 3 COLOUR DIAGRAMS GSM Dual Slot startac Colin Jack, Michael Hansen, Ray Collins, Ralf Lorenzen Page 2 of 2 21.04.99 Rev. 1.1
Motorola Confidential Proprietary