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INTEGRATED CIRCUITS
DATA SHEET
TDA4672 Picture Signal Improvement (PSI) circuit with enhanced peaking function
Product specification Supersedes data of August 1993 File under Integrated Circuits, IC02 1996 Dec 11
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit with enhanced peaking function
FEATURES · Luminance signal delay from 20 ns to 1100 ns (minimum step 45 ns) · Selectable luminance signal peaking with symmetrical overshoots · Selectable 2.6 or 5 MHz peaking centre frequency and degree of peaking from -6 dB to +9 dB in 16 steps of 1 dB each · Selectable noise reduction by coring · Selectable 5 or 12 V sandcastle input voltage · All controls selected via the I2C-bus · Timing pulse generation for clamping and delay time control synchronized by sandcastle pulse · Automatic luminance signal delay correction using a control loop · Luminance input signal clamping with coupling capacitor · 4.5 to +8.8 V supply voltage · Minimum of external components. QUICK REFERENCE DATA SYMBOL VP IP(tot) td(Y) Vi(Y)(p-p) GY Tamb supply voltage (pin 1) total supply current Y signal delay time composite Y input signal (peak-to-peak value, pin 16) voltage gain of Y channel operating ambient temperature PARAMETER MIN. 4.5 26 20 - - 0 5 37 - 450 -1 - TYP. GENERAL DESCRIPTION
TDA4672
The TDA4672 delays the luminance signal. The luminance signal can also be improved by peaking and noise reduction (coring).
MAX. 8.8 46 1130 640 - 70 V
UNIT mA ns mV dB °C
ORDERING INFORMATION TYPE NUMBER TDA4672 PACKAGE NAME DIP18 DESCRIPTION plastic dual in-line package; 18 leads (300 mil) VERSION SOT102-1
1996 Dec 11
2
handbook, full pagewidth
1996 Dec 11
100 nF 2 1 I2C-BUS Y delay sandcastle 5 V/12 V VREF CORING 5 MHz
-0.5
sandcastle pulse SDA SCL 100 nF 15 10 9 I2C-BUS RECEIVER CTI on/off Vref coring on/off peaking frequency degree of peaking Vref GENERATION VP = 5 to 8 V
BLOCK DIAGRAM
Philips Semiconductors
17
SANDCASTLE PULSE DETECTOR Vref DELAY TIME CONTROL
BK
BK, H + V
Y 100 ns 90 ns
16
BLACK LEVEL CLAMP
+
CORING 11 100 nF
100 nF
2.6 MHz
Vref control signal
-0.5
5 MHz 2.6 MHz I2C-BUS PEAKING
Picture Signal Improvement (PSI) circuit with enhanced peaking function
3
I2C-BUS BLACK LEVEL CLAMP 180 ns
+1
450 ns
180 ns
90 ns
45 ns
90 ns
100 ns
BLACK LEVEL CLAMP
+
100 nF
13
Vref 12 Y
14
TDA4672
4 -(R - Y)
100 nF
-(R - Y)
3
-(B - Y)
7
6 -(B - Y)
8
18
5
MED756
n.c.
Product specification
TDA4672
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit with enhanced peaking function
PINNING SYMBOL VP CDL Vi(R - Y) Vo(R - Y) n.c. Vo(B - Y) Vi(B - Y) GND2 SDA SCL CCOR VoY CCLP1 CCLP2 Cref ViY SAND GND1 Notes 1. Pin 3 is connected directly to pin 4. 2. Pin 7 is connected directly to pin 6. PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 DESCRIPTION positive supply voltage capacitor of delay time control ±(R - Y) colour-difference input signal; note 1 ±(R - Y) colour-difference output signal; note 1 not connected ±(B - Y) colour-difference output signal; note 2 ±(B - Y) colour-difference input signal; note 2 ground 2 (0 V) I2C-bus serial data input/output I2C-bus serial clock input coring capacitor delayed luminance output signal black level clamping capacitor 1 black level clamping capacitor 2 capacitor of reference voltage luminance input signal sandcastle pulse input ground 1 (0 V) Fig.2 Pin configuration.
handbook, halfpage
TDA4672
VP CDL
1 2
18 GND1 17 SAND 16 ViY 15 Cref
Vi(R - Y) 3 Vo(R - Y) 4 n.c. 5
TDA4672
14 CCLP2 13 CCLP1 12 VoY 11 CCOR 10 SCL
Vo(B - Y) 6 Vi(B - Y) 7 GND2 SDA 8 9
MED757
1996 Dec 11
4
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit with enhanced peaking function
FUNCTIONAL DESCRIPTION The TDA4672 contains luminance signal processing. The luminance signal section comprises a variable, integrated luminance delay line with luminance signal peaking and noise reduction by coring. All functions and parameters are controlled via the I2C-bus. Y-signal path The video and blanking signal is AC-coupled to the input pin 16. Its black porch is clamped to a DC reference voltage to ensure the correct operating range of the luminance delay stage. The luminance delay line consists of all-pass filter sections with delay times of 45, 90, 100, 180 and 450 ns (see Fig.1). The luminance signal delay is controlled via the I2C-bus in steps of 45 ns in the range of 20 to 1100 ns, this ensures that the maximum delay difference between the luminance and colour-difference signals is ±22.5 ns. An automatic luminance delay time adjustment in an internal control loop (with the horizontal frequency as a reference) is used to correct changes in the delay time, due to component tolerances. The control loop is automatically enabled between the burst key pulses of lines 16 (330) and 17 (331) during the vertical blanking interval. The control voltage is stored in the capacitor CDL connected to pin 2.
TDA4672
The peaking section uses a transversal filter circuit with selectable centre frequencies of 2.6 and 5.0 MHz. It provides selectable degrees of peaking from -6 to +9 dB and noise reduction by coring, which attenuates the high-frequency noise introduced by peaking. The output buffer stage ensures a low-ohmic Video Blanking Synchronization (VBS) output signal on pin 12 (<160 ). The gain of the luminance signal path from pin 16 to pin 12 is unity. An oscillation signal of the delay time control loop is present on output pin 12 instead of the VBS signal. It is present during the vertical blanking interval of the burst key pulses in lines 16 (330) to 18 (332). This sync should not be applied for synchronization. Colour-difference signal paths The colour-difference input signals (on pins 3 and 7) are connected directly to the output pins. This is for compatibility with other Philips Semiconductors PSI-circuits.
1996 Dec 11
5
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit with enhanced peaking function
TDA4672
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). GND1 and GND2 are connected together. SYMBOL VP VI V9,10 V17 I8-18 I3-4 I6-7 Ptot Tstg Tamb VESD PARAMETER supply voltage (pin 1) input voltage (pins 2 to 7 and pins 11 to 16) input voltage at pins 9 and 10 input voltage at pin 17 current between pins 8 and 18 current between pins 3 and 4 current between pins 6 and 7 total power dissipation storage temperature operating ambient temperature electrostatic handling for pin 17 for other pins Note 1. Equivalent to discharging a 200 pF capacitor through a 0 series resistor. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 82 UNIT K/W note 1 - - - +250 -500 ±500 V V V CONDITIONS 0 -0.1 -0.1 -0.1 - - - 0 -25 0 MIN. MAX. 8.8 VP +8.8 +12 ±20 ±4 ±4 0.97 +150 70 UNIT V V V V mA mA mA W °C °C
CHARACTERISTICS VP = 5 V; nominal video amplitude VVB = 315 mV; tH = 64 µs; tBK = 4 µs (burst key); Tamb = 25 °C and measurements taken in Fig.4; unless otherwise specified. SYMBOL VP IP(tot) Y-signal path Vi(Y)(p-p) V16 I16 R16 C16 td(Y)(max) td(Y)(min) VBS input signal on pin 16 (peak-to-peak value) black level clamping voltage input current input resistance input capacitance maximum Y delay time minimum Y delay time set via I2C-bus set via I2C-bus during clamping outside clamping outside clamping - - ±95 - 5 - 1070 - 450 3.1 - - - 3 1100 20 640 - ±190 ±0.1 - 10 1130 - mV V µA µA M pF ns ns PARAMETER supply voltage (pin 1) total supply current CONDITIONS MIN. 4.5 26 5 37 TYP. MAX. 8.8 46 UNIT V mA
1996 Dec 11
6
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit with enhanced peaking function
SYMBOL td(Y) PARAMETER minimum delay step group delay time difference td(peak) GY minimum delay time for peaking VBS signal gain measured on output pin 12 (composite signal, peak-to-peak value) output current (emitter-follower with constant current source) output resistance frequency response for maximum delay f = 0.5 to 3 MHz f = 0.5 to 5 MHz LIN signal linearity for video contents of 315 mV (p-p) video contents of 450 mV (p-p) Luminance peaking, selected via I2C-bus fpeak Vpeak peaking frequency peaking amplitude for grade of peaking (fC amplitude over 0.5 MHz amplitude) selectable values from to each step no limitation of peaking Vn(rms) COR noise voltage on pin 12 (RMS value) coring of peaking (coring part referred to 315 mV) without peaking; f = 0 to 5 MHz COR-bit = 1 - - - - - - -6 +9 1 - - 20 fC1; LCF-bit = 0 fC2; LCF-bit = 1 Y delay = 215 ns; peaking delay only 4.5 2.3 5 2.6 min/max; note 1 VVBS = 450 mV (p-p) VVBS = 640 mV (p-p) 0.85 0.60 - - -2 -4 -1 -3 V12/V16; f = 500 kHz; maximum delay source current sink current set via CONDITIONS I2C-bus f = 0.5 to 5 MHz; maximum delay - 185 -2 MIN. 40 0 215 -1 TYP. 45
TDA4672
MAX. 50 ±25 245 0
UNIT ns ns ns dB
I12 R12 f
-1 0.4 -
- - -
- - 160 0 -1 - -
mA mA dB dB - -
5.5 2.9
MHz MHz
- - - - 1 -
dB dB dB % mV %
1996 Dec 11
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Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit with enhanced peaking function
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA4672
MAX.
UNIT
Sandcastle pulse, input voltage selectable via I2C-bus V17 input voltage threshold for H and V sync input voltage threshold for burst input voltage threshold for H and V sync input voltage threshold for burst R17 C17 tBK td np input resistance input capacitance burst key pulse width leading edge delay for clamping pulse number of required burst key pulses vertical blanking interval referenced to tBK note 2 SC5-bit = 0 (+12 V) SC5-bit = 0 (+12 V) SC5-bit = 1 (+5 V) SC5-bit = 1 (+5 V) +12 V input level +5 V input level 1.1 5.5 1.1 3.0 30 15 - 3.0 - 4 1.5 6.5 1.5 3.5 40 20 4 4.0 1 - 1.9 7.5 1.9 4.0 50 25 8 4.6 - 31 V V V V k k pF µs µs -
I2C-bus control, SDA and SCL VIH VIL I9,10 Vo(ACK) Io(ACK) Notes 1. min: minimum differential voltage gain of the luminance video signal; max: maximum differential voltage gain of the luminance video signal. 2. A number of more than 31 burst key pulses repeats the counter cycle of delay time control. HIGH level input voltage on pins 9 and 10 LOW level input voltage on pins 9 and 10 input current on pins 9 and 10 output voltage at acknowledge on Io(ACK) = 3 mA pin 9 output current at acknowledge on sink current pin 9 3 0 - - 3 - - - - - 5 1.5 ±10 0.4 - V V µA V mA
1996 Dec 11
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Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit with enhanced peaking function
I2C-BUS FORMAT S(1) Notes 1. S = START condition. 2. SLAVE ADDRESS = 1000 100X. 3. ACK = acknowledge, generated by the slave. 4. SUBADDRESS = subaddress byte, see Table 1. 5. DATA = data byte, see Table 1. 6. P = STOP condition. 7. X = read/write control bit. X = 0, order to write (the circuit is slave receiver). X = 1, order to read (the circuit is slave transmitter). If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed. Table 1 I2C-bus transmission; see Table 2 DATA FUNCTION Y delay/SC Peaking and coring Table 2 SUBADDRESS D7 00010000 00010001 0 COR D6 SC5 PEAK D5 0 LCF D4 DL4 0 D3 DL3 D2 DL2 SLAVE ADDRESS(2) ACK(3) SUBADDRESS(4) ACK(3)
TDA4672
DATA(5)
P(6)
D1 DL1
D0 DL0
PCON3 PCON2 PCON1 PCON0
Function of the bits DATA FUNCTION set delay in luminance channel LOGIC 1 45 ns 90 ns 180 ns 180 ns 450 ns select sandcastle pulse voltage set peaking frequency response set peaking delay set coring control set peaking amplification +5 V 2.6 MHz active (190 ns) active see Table 3 LOGIC 0 0 ns 0 ns 0 ns 0 ns 0 ns +12 V 5.0 MHz inactive inactive
DL0 DL1 DL2 DL3 DL4 SC5 LCF PEAK COR PCONx
1996 Dec 11
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Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit with enhanced peaking function
Table 3 Peaking amplification PCON2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 PCON1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 PCON0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
TDA4672
PCON3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
GRADE OF PEAKING (dB) -6 -5 -4 -3 -2 -1 0 +1 +2 +3 +4 +5 +6 +7 +8 +9
Remarks to the subaddress bytes Subaddresses 00H to 0FH are reserved for colour decoders and RGB processors. Subaddresses 10 and 11 only are acknowledged. General call address is not acknowledged. Power-on reset: D7 to D1 bits of data bytes are set to logic 0, D0 bit is set to logic 1.
1996 Dec 11
10
Product specification
TDA4672
Fig.3 Internal circuit.
handbook, full pagewidth
1996 Dec 11
Cref CCLP2 14 13 12 CCLP1 15 Y output
SC
Y input
17
16
Philips Semiconductors
INTERNAL CIRCUITRY
+ + + +
+
11
CCOR
GND
18
+
all input and output pins except pins 9, 10 and 17
Picture Signal Improvement (PSI) circuit with enhanced peaking function
11
TDA4672
4 CD output n.c. 5 6 CD output 7 CD input 8 GND
+
VP
1
+
10
SCL
+
2
3
9 SDA
MED759
CDL
CD input
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit with enhanced peaking function
TEST AND APPLICATION INFORMATION
TDA4672
handbook, full pagewidth
SDA I2C-bus SCL CCOR 0.1 µF (VBS) VoY 10 9 GND2 Vi(B - Y) 12 7 Vo(B - Y) SDA
11
8
CCLP1 0.1 µF CCLP2 0.1 µF Cref 0.1 µF (VBS) sandcastle pulse input ViY 0.1 µF SAND
13
6
14
TDA4672
5
n.c. Vo(R - Y) Vi(R - Y) CDL VP 0.1 µF +5 V 47 µF
15
4
16
3
17 GND1
2
18
1
MED758
15 VB
Fig.4 Test and application circuit.
1996 Dec 11
12
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit with enhanced peaking function
PACKAGE OUTLINE DIP18: plastic dual in-line package; 18 leads (300 mil)
TDA4672
SOT102-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 18 10 b2 MH w M (e 1)
pin 1 index E
1
9
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.7 0.19 A1 min. 0.51 0.020 A2 max. 3.7 0.15 b 1.40 1.14 0.055 0.044 b1 0.53 0.38 0.021 0.015 b2 1.40 1.14 0.055 0.044 c 0.32 0.23 0.013 0.009 D (1) 21.8 21.4 0.86 0.84 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.10 e1 7.62 0.30 L 3.9 3.4 0.15 0.13 ME 8.25 7.80 0.32 0.31 MH 9.5 8.3 0.37 0.33 w 0.254 0.01 Z (1) max. 0.85 0.033
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT102-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 93-10-14 95-01-23
1996 Dec 11
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Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit with enhanced peaking function
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA4672
with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1996 Dec 11
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