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Now downloading free:Philips TDA4672

Philips TDA4672 free download

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Mfg:Philips
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Descr:Philips Quality Data Sheet
Group:Electronics > Components > Integrated circuits
Uploaded:21-07-2004
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INTEGRATED CIRCUITS DATA SHEET TDA4672 Picture Signal Improvement (PSI) circuit with enhanced peaking function Product specification Supersedes data of August 1993 File under Integrated Circuits, IC02 1996 Dec 11 Philips Semiconductors Product specification Picture Signal Improvement (PSI) circuit with enhanced peaking function FEATURES · Luminance signal delay from 20 ns to 1100 ns (minimum step 45 ns) · Selectable luminance signal peaking with symmetrical overshoots · Selectable 2.6 or 5 MHz peaking centre frequency and degree of peaking from -6 dB to +9 dB in 16 steps of 1 dB each · Selectable noise reduction by coring · Selectable 5 or 12 V sandcastle input voltage · All controls selected via the I2C-bus · Timing pulse generation for clamping and delay time control synchronized by sandcastle pulse · Automatic luminance signal delay correction using a control loop · Luminance input signal clamping with coupling capacitor · 4.5 to +8.8 V supply voltage · Minimum of external components. QUICK REFERENCE DATA SYMBOL VP IP(tot) td(Y) Vi(Y)(p-p) GY Tamb supply voltage (pin 1) total supply current Y signal delay time composite Y input signal (peak-to-peak value, pin 16) voltage gain of Y channel operating ambient temperature PARAMETER MIN. 4.5 26 20 - - 0 5 37 - 450 -1 - TYP. GENERAL DESCRIPTION TDA4672 The TDA4672 delays the luminance signal. The luminance signal can also be improved by peaking and noise reduction (coring). MAX. 8.8 46 1130 640 - 70 V UNIT mA ns mV dB °C ORDERING INFORMATION TYPE NUMBER TDA4672 PACKAGE NAME DIP18 DESCRIPTION plastic dual in-line package; 18 leads (300 mil) VERSION SOT102-1 1996 Dec 11 2 handbook, full pagewidth 1996 Dec 11 100 nF 2 1 I2C-BUS Y delay sandcastle 5 V/12 V VREF CORING 5 MHz -0.5 sandcastle pulse SDA SCL 100 nF 15 10 9 I2C-BUS RECEIVER CTI on/off Vref coring on/off peaking frequency degree of peaking Vref GENERATION VP = 5 to 8 V BLOCK DIAGRAM Philips Semiconductors 17 SANDCASTLE PULSE DETECTOR Vref DELAY TIME CONTROL BK BK, H + V Y 100 ns 90 ns 16 BLACK LEVEL CLAMP + CORING 11 100 nF 100 nF 2.6 MHz Vref control signal -0.5 5 MHz 2.6 MHz I2C-BUS PEAKING Picture Signal Improvement (PSI) circuit with enhanced peaking function 3 I2C-BUS BLACK LEVEL CLAMP 180 ns +1 450 ns 180 ns 90 ns 45 ns 90 ns 100 ns BLACK LEVEL CLAMP + 100 nF 13 Vref 12 Y 14 TDA4672 4 -(R - Y) 100 nF -(R - Y) 3 -(B - Y) 7 6 -(B - Y) 8 18 5 MED756 n.c. Product specification TDA4672 Fig.1 Block diagram. Philips Semiconductors Product specification Picture Signal Improvement (PSI) circuit with enhanced peaking function PINNING SYMBOL VP CDL Vi(R - Y) Vo(R - Y) n.c. Vo(B - Y) Vi(B - Y) GND2 SDA SCL CCOR VoY CCLP1 CCLP2 Cref ViY SAND GND1 Notes 1. Pin 3 is connected directly to pin 4. 2. Pin 7 is connected directly to pin 6. PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 DESCRIPTION positive supply voltage capacitor of delay time control ±(R - Y) colour-difference input signal; not

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