Text preview for : M27C1001.pdf part of SGS-Thomson M27C1001 CMOS,1MBit(128kx8 Bit),UV EPROM and OTP ROM,100nS,32-DIP
Back to : M27C1001.pdf | Home
M27C1001
1 Megabit (128K x 8) UV EPROM and OTP ROM
VERY FAST ACCESS TIME: 45ns COMPATIBLE with HIGH SPEED MICROPROCESSORS, ZERO WAIT STATE LOW POWER "CMOS" CONSUMPTION: Active Current 30mA Standby Current 100µA PROGRAMMING VOLTAGE: 12.75V ELECTRONIC SIGNATURE for AUTOMATED PROGRAMMING PROGRAMMING TIMES of AROUND 12sec. (PRESTO II ALGORITHM)
28
1
FDIP32W (F)
LCCC32W (L)
DESCRIPTION The M27C1001 is a high speed 1 Megabit UV erasable and electrically programmable memory EPROM ideally suited for microprocessor systems requiring large programs. It is organized as 131,072 by 8 bits. The 32 pin Window Ceramic Frit-Seal Dual-in-Line and Leadless Chip Carrier packages have transparent lids which allow the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the M27C1001 is offered in both Plastic Dual-in-Line, Plastic Leaded Chip Carrier and Plastic Thin Small Outline packages. Table 1. Signal Names
A0 - A16 Q0 - Q7 E G P VPP VCC VSS Address Inputs Data Outputs Chip Enable Output Enable Program Program Supply Supply Voltage Ground
PLCC32 (C)
TSOP32 (N) 8 x 20mm
Figure 1. Logic Diagram
VCC
VPP
17 A0-A16
8 Q0-Q7
P E G
M27C1001
VSS
AI00710B
May 1995
1/15
M27C1001
Figure 2A. DIP Pin Connections
VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 VSS 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 M27C1001 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17
AI00711
Figure 2B. LCC Pin Connections
VCC P NC A14 A13 A8 A9 A11 G A10 E Q7 Q6 Q5 Q4 Q3 A12 A15 A16 VPP VCC P NC 1 32 A7 A6 A5 A4 A3 A2 A1 A0 Q0 A14 A13 A8 A9 A11 G A10 E Q7 9 M27C1001 25 17 VSS Q3 Q4 Q5 Q6
AI00712
Warning: NC = Not Connected.
Warning: NC = Not Connected.
Figure 2C. TSOP Pin Connections
A11 A9 A8 A13 A14 NC P VCC VPP A16 A15 A12 A7 A6 A5 A4 1 32 G A10 E Q7 Q6 Q5 Q4 Q3 VSS Q2 Q1 Q0 A0 A1 A2 A3
Read Mode The M27C1001 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of tGLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV-tGLQV. Standby Mode The M27C1001 has a standby mode which reduces the active current from 30mA to 100µA. The M27C1001 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input. Two Line Output Control
8 9
M27C1001 (Normal)
25 24
16
17
AI01151B
Warning: NC = Not Connected.
DEVICE OPERATION The modes of operationof the M27C1001 are listed in the Operating Modes table. A single 5V power supply is required in the read mode. All inputs are TTL levels except for VPP and 12V on A9 for Electronic Signature.
Because EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows : a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur.
2/15
Q1 Q2
M27C1001
Table 2. Absolute Maximum Ratings (1)
Symbol TA TBIAS TSTG VIO
(2)
Parameter Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltages (except A9) Supply Voltage A9 Voltage Program Supply Voltage
Value 40 to 125 50 to 125 65 to 150 2 to 7 2 to 7 2 to 13.5 2 to 14
Unit °C °C °C V V V V
VCC VA9
(2)
VPP
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is 0.5V with possible undershoot to 2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.
Table 3. Operating Modes
Mode Read Output Disable Program Verify Program Inhibit Standby Electronic Signature
Note: X = VIH or VIL, VID = 12V ± 0.5V
E VIL VIL VIL VIL VIH VIH VIL
G VIL VIH VIH VIL X X VIL
P X X VIL Pulse VIH X X VIH
A9 X X X X X X VID
VPP VCC or VSS VCC or VSS VPP VPP VPP VCC or VSS VCC
Q0 - Q7 Data Out Hi-Z Data In Data Out Hi-Z Hi-Z Codes
Table 4. Electronic Signature
Identifier Manufacturer's Code Device Code A0 VIL VIH Q7 0 0 Q6 0 0 Q5 1 0 Q4 0 0 Q3 0 0 Q2 0 1 Q1 0 0 Q0 0 1 Hex Data 20h 05h
DEVICE OPERATION (cont'd) For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.
System Considerations The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, I CC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capacitive and inductiveloading of the device at the output.
3/15
M27C1001
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 20ns 0.4 to 2.4V 0.8 to 2.0V
Figure 4. AC Testing Load Circuit
1.3V
1N914
Note that Output Hi-Z is defined as the point where data is no longer driven.
3.3k
Figure 3. AC Testing Input Output Waveforms
DEVICE UNDER TEST 2.0V 0.8V
AI00826
OUT CL = 100pF
2.4V
0.4V
CL includes JIG capacitance
AI00828
Note: For 45ns and 55ns class: input pulse voltages are 0V to 3V, input output test points are at 1.5V, CL is 30 pF.
Table 5. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol C IN C OUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
Note: 1. Sampled only, not 100% tested.
Table 6. Read Mode DC Characteristics (1) (TA = 0 to 70 °C, 40 to 85 °C or 40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Symbol ILI ILO ICC ICC1 ICC2 IPP VIL VIH
(2)
Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL Output High Voltage CMOS
Test Condition 0V VIN VCC 0V VOUT VCC E = VIL, G = VIL, IOUT = 0mA, f = 5MHz E = VIH E > VCC 0.2V VPP = VCC
Min
Max ±10 ±10 30 1 100 10
Unit µA µA mA mA µA µA V V V V V
0.3 2 IOL = 2.1mA IOH = 400µA IOH = 100µA 2.4 VCC 0.7V
0.8 VCC + 1 0.4
VOL VOH
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Maximum DC voltage on Output is VCC +0.5V.
4/15
M27C1001
Table 7A. Read Mode AC Characteristics (1) (TA = 0 to 70 °C, 40 to 85 °C or 40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
M27C1001 Symbol Alt Parameter Test Condition -45 Min tAVQV tELQV tGLQV tEHQZ
(2) (3)
-55
(3)
-60 Min Max 60 60 30 0 0 0 30 30 0 0 0
-70 Min Max 70 70 35 30 30
Unit
Max Min 45 45 25
Max 55 55 30
tACC tCE tOE tDF tDF tOH
Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition
E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 0
ns ns ns ns ns ns
25 25
0 0 0
25 25
tGHQZ (2) tAXQX
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested. 3. See specific AC Measurament Condition for -45 and -55 classes.
Table 7B. Read Mode AC Characteristics (1) (TA = 0 to 70 °C, 40 to 85 °C or 40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
M27C1001 Symbol Alt Parameter Test Condition -80 Min tAVQV tELQV tGLQV tEHQZ (2) tGHQZ
(2)
-90 Max 90 90 45 0 0 0 30 30 0 0 0
-10 Min Max 100 100 50 30 30
-12/-15/ -20/-25 Min Max 120 120 60 0 0 0 40 40
Unit
Max Min 80 80 40
tACC tCE tOE tDF tDF tOH
Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition
E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 0
ns ns ns ns ns ns
30 30
tAXQX
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested.
5/15
M27C1001
Figure 5. Read Mode AC Waveforms
A0-A16 tAVQV E tGLQV G tELQV Q0-Q7
VALID tAXQX
tEHQZ
tGHQZ Hi-Z DATA OUT
AI00713
Table 8. Programming Mode DC Characteristics (1) (TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol ILI ICC IPP VIL VIH VOL VOH VID Parameter Input Leakage Current Supply Current Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL A9 Voltage IOL = 2.1mA IOH = 400µA 2.4 11.5 12.5 E = VIL 0.3 2 Test Condition VIL VIN VIH Min Max ±10 50 50 0.8 VCC + 0.5 0.4 Unit µA mA mA V V V V V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
6/15
M27C1001
Table 9. Programming Mode AC Characteristics (1) (TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol tAVPL tQVPL tVPHPL tVCHPL tELPL tPLPH tPHQX tQXGL tGLQV tGHQZ
(2)
Alt tAS tDS tVPS tVCS tCES tPW tDH tOES tOE tDFP tAH
Parameter Address Valid to Program Low Input Valid to Program Low VPP High to Program Low VCC High to Program Low Chip Enable Low to Program Low Program Pulse Width Program High to Input Transition Input Transition to Output Enable Low Output Enable Low to Output Valid Output Enable High to Output Hi-Z Output Enable High to Address Transition
Test Condition
Min 2 2 2 2 2 95 2 2
Max
Unit µs µs µs µs µs
105
µs µs µs
100 0 0 130
ns ns ns
tGHAX
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested.
Figure 6. Programming and Verify Modes AC Waveforms
VALID tAVPL Q0-Q7 tQVPL VPP tVPHPL VCC tVCHPL E tELPL P tPLPH G tQXGL tGHAX tGLQV tGHQZ DATA IN tPHQX DATA OUT
A0-A16
PROGRAM
VERIFY
AI00714
7/15
M27C1001
Figure 7. Programming Flowchart
P are at TTL-low. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. VCC is specified to be 6.25V ± 0.25V. PRESTO II Programming Algorithm PRESTO II Programming Algorithm allows the whole array to be programmed, with a guaranteed margin, in a typical time of 13 seconds. Programming with PRESTO II involves in applying a sequence of 100µs program pulses to each byte until a correct verify occurs. During programming and verify operation, a MARGIN MODE circuit is automatically activated in order to guarantee that each cell is programmed with enough margin. No overprogram pulse is applied since the verify in MARGIN MODE provides necessary margin to each programmed cell. Program Inhibit Programming of multiple M27C1001s in parallel with different data is also easily accomplished. Except for E, all like inputs including G of the parallel M27C1001 may be common. A TTL low level pulse applied to a M27C1001's E input, with P low and VPP at 12.75V, will program that M27C1001. A high level E input inhibits the other M27C1001s from being programmed. Program Verify A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with E and G at VIL, P at VIH, VPP at 12.75V and VCC at 6.25V. Electronic Signature The Electronic Signature mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the M27C1001. To activate this mode, the programming equipment must force 11.5V to 12.5V on address line A9 of the M27C1001, with VPP=VCC=5V. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during Electronic Signature mode. Byte 0 (A0=VIL) represents the manufacturer code and byte 1 (A0=VIH) the device identifier code. For the SGS-THOMSON M27C1001, these two identifier bytes are given in Table 4 and can be read-out on outputs Q0 to Q7.
VCC = 6.25V, VPP = 12.5V
n =0
P = 100µs Pulse NO ++n = 25 YES NO VERIFY YES Last Addr NO ++ Addr
FAIL
YES CHECK ALL BYTES 1st: VCC = 6V 2nd: VCC = 4.2V
AI00715B
DEVICE OPERATION (cont'd) The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic capacitor be used on every device between VCC and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used between VCC and VSS for every eight devices. The bulk capacitor should be located near the power supply connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces. Programming When delivered (and after each erasure for UV EPROM), all bits of the M27C1001 are in the '1' state. Data is introduced by selectively programming '0' into the desired bit locations. Although only '0' will be programmed, both '1' and '0' can be present in the data word. The only way to change a '0' to a '1' is by die exposition to ultraviolet light (UV EPROM). The M27C1001 is in the programming mode when Vpp input is at 12.75V, and E and
8/15
M27C1001
ERASURE OPERATION (applies to UV EPROM) The erasure characteristics of the M27C1001 is such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately4000 Å. It should be notedthat sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 Å range. Research shows that constant exposure to room level fluorescent lighting could erase a typical M27C1001 in about 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the M27C1001 is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the M27C1001 window to prevent unintentional erasure. The recommended erasure procedure for the M27C1001 is exposure to short wave ultraviolet light which has a wavelength of 2537 Å. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 15 W-sec/cm2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with 12000 uW/cm2 power rating. The M27C1001 should be placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. Some lamps have a filter on their tubes which should be removed before erasure.
ORDERING INFORMATION SCHEME Example: M27C1001 -70 X C 1 TR
Speed -45 -55 -60 -70 -80 -90 -10 -12 -15 -20 -25 45 ns 55 ns 60 ns 70 ns 80 ns 90 ns 100 ns 120 ns 150 ns 200 ns 250 ns
VCC Tolerance X blank ± 5% ± 10% F L B C N
Package FDIP32W LCCC32W PDIP32 PLCC32 TSOP32 8 x 20mm
Temperature Range 1 3 6 0 to 70 °C 40 to 125 °C 40 to 85 °C TR X
Option Additional Burn-in Tape & Reel Packing
For a list of available options (Speed, VCC Tolerance, Package, etc...) refer to the current Memory Shortform catalogue. For further information on any aspect of this device, please contact SGS-THOMSON Sales Office nearest to you.
9/15
M27C1001
FDIP32W - 32 pin Ceramic Frit-seal DIP, with window
Symb Typ A A1 A2 B B1 C D E E1 e1 e3 eA L S N
FDIP32W
mm Min Max 5.71 0.50 3.90 0.40 1.27 0.22 1.78 5.08 0.55 1.52 0.31 42.78 15.40 14.50 2.54 38.10 16.17 3.18 1.52 9.65 4° 32 15.80 14.90 18.32 4.10 2.49 15° 0.380 0.100 1.500 Typ
inches Min Max 0.225 0.020 0.154 0.016 0.050 0.009 0.070 0.200 0.022 0.060 0.012 1.684 0.606 0.571 0.637 0.125 0.060 4° 32 0.622 0.587 0.721 0.161 0.098 15°
A2 A1 B1 B e3 D S
N 1
A L eA C
e1
E1
E
FDIPW-a
Drawing is not to scale
10/15
M27C1001
LCCC32W - 32 lead Leadless Ceramic Chip Carrier, square window
Symb Typ A B D E e e1 e2 e3 h j L L1 K K1 N
LCCC32W
mm Min Max 2.28 0.51 11.23 13.72 1.27 0.39 7.62 10.16 1.02 0.51 1.14 1.96 10.50 8.03 32 0.71 11.63 14.22 1.40 2.36 10.80 8.23 0.300 0.400 0.040 0.020 0.050 Typ
inches Min Max 0.090 0.020 0.442 0.540 0.015 0.045 0.077 0.413 0.316 32 0.028 0.458 0.560 0.055 0.093 0.425 0.324
e2 D e
N
j x 45o
1
L1 K E e3 e1 B K1 A h x 45o L
LCCCW-a
Drawing is not to scale
11/15
M27C1001
PDIP32 - 32 lead Plastic DIP, 600 mils width
Symb Typ A A1 A2 B B1 C D E E1 e1 eA L S N
PDIP32
mm Min Max 4.83 0.38 0.41 1.14 0.20 41.78 15.24 13.46 2.54 15.24 3.18 1.78 0° 32 0.51 1.40 0.30 42.04 15.88 13.97 3.43 2.03 15° 0.100 0.600 Typ
inches Min Max 0.190 0.015 0.016 0.045 0.008 1.645 0.600 0.530 0.125 0.070 0° 32 0.020 0.055 0.012 1.655 0.625 0.550 0.135 0.080 15°
A2 A1 B1 D S
N
A L eA C
B
e1
E1
1
E
PDIP
Drawing is not to scale
12/15
M27C1001
PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
Symb Typ A A1 B B1 D D1 D2 E E1 E2 e N Nd Ne CP
PLCC32
mm Min 2.54 1.52 0.33 0.66 12.32 11.35 9.91 14.86 13.89 12.45 1.27 32 7 9 0.10 Max 3.56 2.41 0.53 0.81 12.57 11.56 10.92 15.11 14.10 13.46 0.050 Typ
inches Min 0.100 0.060 0.013 0.026 0.485 0.447 0.390 0.585 0.547 0.490 32 7 9 0.004 Max 0.140 0.095 0.021 0.032 0.495 0.455 0.430 0.595 0.555 0.530
D D1
1 N
A1
B1
Ne
E1 E
D2/E2 B
e
Nd
A CP
PLCC
Drawing is not to scale
13/15
M27C1001
TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm
Symb Typ A A1 A2 B C D D1 E e L N CP
TSOP32
mm Min Max 1.20 0.05 0.95 0.15 0.10 19.80 18.30 7.90 0.50 0.50 0° 32 0.10 0.17 1.50 0.27 0.21 20.20 18.50 8.10 0.70 5° 0.020 Typ
inches Min Max 0.047 0.002 0.037 0.006 0.004 0.780 0.720 0.311 0.020 0° 32 0.004 0.006 0.059 0.011 0.008 0.795 0.728 0.319 0.028 5°
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
Drawing is not to scale
A1
L
14/15
M27C1001
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. © 1995 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
15/15